Chapter 7: Conclusions
7.2 Suggestions for Future Work
A variety of electrical characterization methods have been adopted to draw the complete picture of charge trapping and de-trapping in the pre-existing traps in Hf-based high-k gate dielectrics, including the physical model of charge trapping, the charge trapping and de-trapping behaviors of slow and fast high-k traps, and the space and energy distribution of fast high-k traps. With all these pieces of information, we could have a better understanding of the over-all charge trapping and de-trapping in Hf-based high-k gate dielectrics. However, there are some topics which have not yet been understood clearly nor verified with strong evidence support. Therefore, these topics deserve to be further studied in the near future:
1. In chapter 2, the physical meaning of the charge trapping model with dispersive capture time constants (stretched exponential growth) and its model parameters should be further studied. It is important to understand why this physical model could well describe the charge trapping behavior in high-k gate dielectrics and how this model could be used to predict the device lifetime under normal operation conditions. Also, this model could be re-arranged as the Weibull distribution (weakest link relation) which is commonly used in time-dependent dielectric breakdown (TDDB) studies. The similarity and discrepancy between these two reliability issues should be understood as well.
2. In chapter 3, the repetitive, reversible charge trapping and de-trapping behaviors indicate the charge carriers are trapped in the pre-existing high-k traps without
generating new high-k traps during the stress/recovery cycles or the amount of generated high-k traps is negligible as compared to the pre-existing high-k traps.
Moreover, the transient charging effect could be observed within 10-50 ns even for the slow high-k traps, and this asymmetric capture and emission time constants imply that these trapped charge carriers are located deeply in space distance or in energy levels. These uncertainties deserve to be clarified.
3. In chapter 4, the physical origin of dynamic energy loss tanδ and its relationship to the composition of high-k dielectrics (such as HfO2, HfSiO, and HfSiON) should be studied. Furthermore, the severe capacitance drop due to tunneling leakage current could not be completely recovered by the two-frequency C-V correction only. New circuit element should be added or higher measurement frequencies (Agilent 4294A, f= 40~110M Hz) should be used with appropriate phase compensation and OPEN/SHORT/LOAD calibrations.
4. In chapter 5 and 6, much effort should be made to understand the correlation between the border trap properties (such as the magnitude of border trap density, the space and energy distribution, and the transient charging and discharging behaviors) by low-frequency C-V measurement and by low-frequency charge pumping, and these results could be further verified by pulse Id-Vg technique in some extent. Moreover, the application limits of these two characterization methods should also be studied in terms of the frequency, gate area, and applied gate voltage since both methods may suffer measurement errors under testing conditions of huge tunneling leakage current. Also, the assumption of elastic direct tunneling at single energy level could be modified as the direct tunneling from multiple sub-bands in the Si conduction band states to obtain more accurate energy distribution of border traps.
5. Much effort should be made to study the charge trapping and de-trapping behaviors under static and dynamic negative bias stress in pMOSFETs with Hf-based high-k gate dielectric. Since gate electrons from metal gate electrode and channel holes from inverted n-Si substrate may be injected into the high-k gate dielectric simultaneously, threshold voltage instability should be considered as the combinational effect of both electron and hole trapping in the high-k gate dielectric, and charge recombination may also occur. This may lead to the faulty understanding of charge trapping and de-trapping behaviors under negative bias stress if the respective contributions of electrons and holes have not been clearly separated.
6. Optimized process conditions should be studied to reduce the number of the pre-existing traps in Hf-based high-k gate dielectric. Oxygen vacancies or crystalline defects in the grain boundaries have been identified as the possible causes to explain the physical origin of these pre-existing high-k traps, which seems to be an intrinsic materials problem regardless of deposition technique, post-deposition annealing temperature, or heat treatment ambient. Effective measures such as the Si incorporation, plasma nitridation, and fluorine implantation have to be taken to passivate these trapping centers, and the low-frequency C-V measurement in chapter 5 or low-frequency charge pumping method in chapter 6 could be readily used to monitor the amount of high-k traps located near the high-k/base oxide interface.
7. The function form of charge trapping model should be further clarified to explain different time dependences (power law, logarithmic, and stretched exponential growth) observed in this dissertation. An appropriate function form should be the basis to describe and to determine the charge trapping behavior and related
mechanisms with consistent physical concepts. In addition, the implications of time dependence should be further studied to understand the charge trapping behavior (charge filling in the pre-existing traps or additional trap generation).
8. The tunneling path into and out of high-k traps deserves to be further studied to realize the actual energy distribution of high-k bulk traps. Since the temperature and time dependences of charge trapping and de-trapping behaviors suggest the two-step thermal-assisted tunneling process (elastic direct tunneling plus lattice- relaxation multi-phonon emission), the thermal transition among different energy levels (ground and many excited states) by cascade phonon emission should be considered to determine the more accurate energy distribution of high-k traps.
9. Charge trapping and de-trapping into and out of the pre-existing high-k traps should be studied in terms of the 1/f low-frequency noise and random telegraph signal (RTS) methods, which have been widely used in the study of oxide traps.
In-depth understanding of different analysis methods could help us distinguish the similarities and discrepancies of charge trapping and de-trapping behaviors in conventional oxides and Hf-based high-k gate dielectrics.
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Chapter 3
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Chapter 4
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Chapter 5
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Solid-State Circuits, vol. 29, no. 3, pp. 239-252, Mar. 1994.
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Schwank, M. R. Shaneyfelt, and L. C. Riewe, “Effects of oxide traps, interface traps and border traps on metal-oxide-semiconductor devices,” J.
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Chapter 6
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IEEE Trans. Electron Devices, vol. 41, no. 7, pp. 1213-1216, Jul. 1994.
[6.5] Y. Maneglia and D. Bauza, “Extraction of slow oxide trap concentration profiles in metal-oxide-semiconductor transistors using the charge pumping method,” J. Appl. Phys., vol. 79, no. 8, pp. 4187-4192, Apr. 1996.
[6.6] D. Bauza and Y. Maneglia, “In-depth exploration of Si-SiO2 interface traps in MOS transistors using the charge pumping technique,” IEEE Trans.
Electron Devices, vol. 44, no. 12, pp. 2262-2266, Dec. 1997
[6.7] D. M. Fleetwood, P. S. Winokur, R. A. Reber, Jr., T. L. Meisenheimer, J. R.
Schwank, M. R. Shaneyfelt, and L. C. Riewe, “Effects of oxide traps, interface traps, and border traps on metal-oxide-semiconductor devices,” J.
Appl. Phys., vol. 73, no. 10, pp. 5058-5074, May 1993.
[6.8] F. P. Heiman and G. Warfield, “The effects of oxide traps on the MOS
capacitance,” IEEE Trans. Electron Devices, vol. 12, no. 4, pp. 167-178, Apr. 1965.
[6.9] I. Lundstrom and C. Svensson, “Tunneling to traps in insulators,” J. Appl.
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