• 沒有找到結果。

Suggestions for Future Works

在文檔中 中 華 大 學 (頁 55-73)

CHAPTER 4 Conclusions

4.2 Suggestions for Future Works

Base on the above results. Several works are worthy to do in the future and are recommended here.

1. The goal of low leakage current and low EOT:

We must by to reduce the defects and suppress the leakage current in LaAlO3 thin film Moreover , we should try to achieve the goal of the low EOT with the low leakage current.

2. To low leakage current and VCC of TLAO MIM by higher work-function metals (Ni, Ir or Pt).

3. To modify the Vfb and Vt of LAO MOS capacitor by using high work-function gates.

4. To use varied interfacial layer (SiO2 or GeO2) to improve the thermal stability on Ge substrate.

5. LAO MOSFET fabrication and related reliability investigation.

45

Reference Chaper1

[1.1] Wang Bin, J. S. Suehle, E. M. Vogel and J. B. Bernstein, ”Time-dependent breakdown of ultra-thin SiO2 gate dielectrics under pulsed biased stress,” IEEE Electron Device Lett., 22, pp. 224-226, 2001.

[1.2] J. H. Stathis, A. Vayshenker, P. R. Varekamp, E. Y. Wu, C. Montrose, J. McKenna, D. J. DiMaria, L. -K. Han, E. Cartier, R. A. Wachnik and B. P. Linder, “Breakdown measurements of ultra-thin SiO2 at low voltage,” in IEDM Tech. Dig., 2000, pp.

94-95.

[1.3] M. Koyama, K. Suguro, M. Yoshiki, Y. Kamimuta, M. Koike, M. Ohse, C.b Hongo and A. Nishiyama, “Thermally stable ultra-thin nitrogen incorporated ZrO2 gate dielectric prepared by low temperature oxidation of ZrN,” in IEDM Tech. Dig., 2001, pp. 20.3.1-20.3.4.

[1.4] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A.

Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H.

Okorn-Schmidt, C. D Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. -A.

Ragnarsson and Rons, “Ultrathin high-κ gate stacks for advanced CMOS devices,”

in IEDM Tech. Dig., 2001, pp. 20.1.1-20.1.4.

[1.5] International Technology Roadmap for Semiconductor, 2001, pp. 38.

[1.6] S. Song, J. H. Yi, W. S. Kim, J. S. Lee, K. Fujihara, H. K. Kang, J. T. Moon and M.

Y. Lee, “CMOS device scaling beyond 100 nm,” in IEDM Tech. Dig., 2000, pp.

235-238.

[1.7] International Technology Roadmap for Semiconductor, 1999.

[1.8] International Technology Roadmap for Semiconductors, 2002.

46

[1.9] D.-G. Park, T.-H. Cha, K.-Y. Lim, H.-J. Cho, T.-K. Kim, S.-A. Jang, Y.-S. Suh, V.

Misra, I.-S. Yeo, J.-S. Roh, J. W. Park, and H.-K. Yoon, “Robust ternary metal gate electrodes for dual gate CMOS devices,” in IEDM Tech. Dig., 2001, pp. 671–674.

[1.10] Y. H. Kim, C. H. Lee, T. S. Jeon, W. P. Bai, C. H. Choi, S. J. Lee, L. Xinjian, R.

Clarks, D. Roberts, and D. L. Kwong, “High quality CVD TaN gate electrode for sub-100 nm MOS devices,” in IEDM Tech. Dig., 2001, pp. 667–670.

[1.11] J. H. Lee, H. Zhong, Y.-S. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra,

“Tunable work function dual metal gate technology for bulk and nonbulk CMOS,”

in IEDM Tech. Dig., 2002, pp. 359–362.

[1.12] C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, “Fermilevel pinning at the polySi/metal oxide interface,” in Symp. VLSI Tech.Dig., 2003, pp. 9–10.

[1.13] H. Y. Yu, Chi Ren, Yee-Chia Yeo, J. F. Kang, X. P. Wang, H. H. H. Ma, Ming-Fu Li, D. S. H. Chan, and D.-L. Kwong, “Fermi Pinning-Induced Thermal Instability of Metal-Gate Work Functions,” IEEE Electron Device Lett., vol. 25, no.5, pp.337-339, 2004.

[1.14] C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, S. B. White, and P. Tobin, “Fermi-level pinning at the poly-Si–Metal oxide interface,” in Symp. VLSI Tech. Dig., 2003, pp. 9–10.

[1.15] S. Pidin, Y. Morisaki, Y. Sugita, T. Aiyama, K. Irino, T. Nakamura, and T. Sugii,

“Low standby power CMOS with HfO gate oxide for 100-nm generation,” in Symp.

VLSI Tech. Dig., 2002, pp. 28–29.

[1.16] Y. Morisaki, T. Aoyama, Y. Sugita, K. Irino, T. Sugii, and T. Nakamura, “Ultrathin

47

(Teffinv= 1.7 nm) poly-Si-gated SiN/HfO2/SiON high-κ stack dielectrics with high thermal stability (1050 oC),” in IEDM Tech. Dig., 2002, pp.861–864.

[1.17] E. P. Gusev, D. A. Buchanan, E. Cartier,A. Kumar,D. DiMaria, S. Guha, A.

Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H.

Okorn-Schmidt, C. D’Emic, P. A. Mocuta, and A. Ajmera,“Ultrathin high-κ gate stacks for advanced CMOS devices,” in IEDM Tech. Dig., 2001, pp. 20.1.1–20.1.4.

[1.18] Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Rieley, J. Chen, K. Torres, J. Lim,B.

Foran, F. Shaapur, A. Agarwal, P. Lysagt, G. A. Brown, C. Young, S. Borthakur, H.

J. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, A.

Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C.

Werkhoven, “Conventional n-channel MOSFET devices using single layer HfO2

and ZrO2 as high-κ gate dielectrics with polysilicon gate electrode,” in IEDM Tech.

Dig., 2001, pp. 20.2.1–20.2.4.

[1.19] L. Kang, K. Onishi, Y. Jeon, B. H. Lee, C. Kang, W. J. Qi, R. Nieh, S. Gopalan,R.

Choi, and J. C. Lee, “MOSFET devices with polysilicon on single-layer HfO2

high-κ dielectrics,” in IEDM Tech. Dig., 2000, pp. 35–38.

[1.20] S. J. Lee, H. F. Luan, W. P. Bai, C. H. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L. Kwong, “High quality ultra thin CVD HfO2 gate stack with poly-Si gate electrode,” in IEDM Tech. Dig., 2000, pp. 31–34.

[1.21] C. Hobbs, J. Grant, S. Kher, V. Dhandapani, B. Taylor, L. Dip, R. Hegde, C.

Metzner, H. Tseng, D. Gilmer, A. Franke, R. Garcia, L. Hebert, M. Azrak, D. Sing, T. Stephens, C. Scrogum, R. Rai, V. Becnel, J. Conner, B. White, and P. Tobin.

Poly-Si gate CMOS with hafnium silicate gate dielectric. presented at 203rd Meeting of the Electrochemical Society.

[1.22] C. S. Kang, H. J. Cho, K. Onisho, R. Choi, R. Nieh, S. Goplan, S. Krishnan, and J.

48

C. Lee, “Improved thermal stability and device performance of ultrathin (EOT<10Å) gate dielectric MOSFETs by using afnium oxynitride (HfOXNY),” in Symp. VLSI Tech. Dig., 2002, pp. 146–147.

[1.23] C. H. Choi, S. J. Rhee, T. S. Jeon, N. Lu, J. H. Sim, R. Clark, M. Niwa, and D. L.

Kwong, “Thermally stable CVD HfOXNY advanced gate dielectrics,” in IEDM Tech.

Dig., 2002, pp. 857–860.

[1.24] A. L. P. Rotondaro, M. R. Visokay, J. J. Chambers, A. Shanware, R. Khamankar,H.

Bu, R. T. Laaksonen, L. Tsung, M. Douglas, R.Kuan, M. J. Bevan, T. Grider, J.

McPherson, and L. Colombo, “Advanced CMOS transistors with a novel HfSiON gate dielectric,” in Symp. VLSI Tech. Dig., 2002, pp. 148–149.

[1.25] M. Koyama, A. Kaneko, T. Ino, M. Koike, Y. Kamata, R. Iijima, Y. Kamiuta, A.

Takashima, M. Suzuki, C. Hongo, S. Inumiya, M. Takayanagi, and A. Nishiyama,

“Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics,” in IEDM Tech. Dig., 2002, pp. 849–852.

[1.26] M. Houssa, M. Naili, V. V. Afanas'ev, M. M. Heyns and A. Stesmans, ” Electrical and physical characterization of high-κ dielectric layers,” in Symp. on VLSI Technology, 2001, pp. 196-199.

[1.27] J. H. Stathis and D. J. DiMaria, “Reliability projection for ultra-thin oxides at low voltage,” in IEDM Tech. Dig., 1998, pp. 167-170.

[1.28] R. Degraeve, N. Pangon, B. Kaczer, T. Nigam, G. Groeseneken and A.

Naem, ”Temperature acceleration of oxide breakdown and its impact on ultra-thin gate oxide reliability,” in Symp. on VLSI Technology, 1999, pp. 59-60.

[1.29] R. B. van Dover, R. M. Fleming, L. F. Schneemeyer, G. B. Alers and D. J.

Werder, ”Advanced dielectrics for gate oxide, DRAM and RF capacitors,” in IEDM Tech. Dig., 1998, pp. 823-826.

49

[1.30] T. P. Ma, ”High-κ gate dielectrics for scaled CMOS technology,” in Solid-State and Integrated-Circuit Technology, 2001, pp. 297-02.

[1.31] S. A. Campbell, D. C. Gilmer, Wang Xiao-Chuan, Hsieh Ming-Ta, Hyeon-Seag Kim, W. L. Gladfelter and Jinhua Yan, ”MOSFET transistors fabricated with high permitivity TiO 2 dielectrics,” IEEE Electron Device Lett., 22, pp. 104-109, 1997.

[1.32] C. Hobbs, R. Hegde, B. Maiti, H. Tseng, D. Gilmer, P. Tobin, O. Adetutu, F. Huang, D. Weddington, R. Nagabushnam, D. O'Meara, K. Reid, L. La, L. Grove and M.

Rossow, ”Sub-quarter micron CMOS process for TiN-gate MOSFETs with TiO2 gate dielectric formed by titanium oxidation,” in Symp. on VLSI Technology, 1999, pp. 133-134.

[1.33] Kee-Won Kwon, Chang-Seok Kang, Soon Oh Park, Ho-Kyu Kang and Sung Tae Ahn, ”Thermally robust Ta2O5 capacitor for the 256-Mbit DRAM,” IEEE Electron Device Lett., 43, pp. 919-923, 1996.

[1.34] Kwang Ming Lin, CheeYee Kwok and Ruey Shing Huang, “An integrated thermo-capacitive type MOS flow sensor,” IEEE Electron Device Lett., 17, pp.

247-249, 1996.

[1.35] E. Dusinski, J. Szmidt, K. Zdunek, M. Elert and A. Barcz, “Titanium oxide produced by plasma technology for MOS structures,” Wide Bandgap Layers, pp.

206-207, 2001.

[1.36] Ma Tiezhong, S. A. Campbell, R. Smith, N. Hoilien, He Boyong, W. L. Gladfelter, C. Hobbs, D. Buchanan, C. Taylor, M. Gribelyuk, M. Tiner, M. Coppel and Lee Jang Jung, ”Group IVB metal oxides high permittivity gate insulators deposited from anhydrous metal nitrates,” IEEE Electron Device Lett., 48, pp. 2348-2356, 2001.

[1.37] H. -J. Cho, C. S. Kang, K. Onishi, S. Gopalan, R. Nieh, R. Choi, E. Dharmarajan

50

and J.C. Lee, ”Novel nitrogen profile engineering for improved TaN/HfO2 Si MOSFET performance,” in IEDM Tech. Dig., 2001, pp. 30.2.1-30.2.4.

[1.38] Y. Abe, T. Oishi, K. Shiozawa, Y. Tokuda and S. Satoh, ”Simulation study on comparison between metal gate and polysilicon gate for sub-quarter-micron MOSFETs,” IEEE Electron Device Lett., 20, pp. 632-634, 1999.

[1.39] K. Onishi, Chang Seok Kang, Rino Choi, Hag-Ju Cho, S. Gopalan, R.. Nieh, E.

Dharmarajan and J. C. Lee, ”Reliability characteristics, including NBTI, of polysilicon gate HfO2 MOSFET's,” in IEDM Tech. Dig., 2001, pp. 30.3.1-30.3.4.

[1.40] L. Manchanda, B. Busch, M. L. Green, M. Morris, R. B. van Dover, R. Kwo and S.

Aravamudhan, ”High K gate dielectrics for the silicon industry,” in Gate Insulator, 2001, pp. 56-60.

[1.41] G. Wilk, R. M. Wallace and J. M. Anthony, “Hafnium and Zirconium Silicates for advanced gate dielectrics,” J. Applied Physics, 87, pp. 484-492, 2000.

[1.42] W. Zhu, T. P. Ma, T. Tamagawa, Y. Di, J. Kim, R. Carruthers, M. Gibson and T.Furukawa, ”HfO2 and HfAlO for CMOS: thermal stability and current transport,”

in IEDM Tech. Dig., 2001, pp. 20.4.1-20.4.4.

[1.43] L. Kang, K. Onishi, Y. Jeon, Byoung Hun Lee, C. Kang, Wen-Jie Qi, R. Nieh, S.

Gopalan, R Choi and J. C. Lee, ”MOSFET devices with polysilicon on single-layer HfO2 high-κ dielectrics,” in IEDM Tech. Dig., 2000, pp. 35-38.

[1.44] Rino Choi, Chang Seok Kang, Byoung Hun Lee, K. Onishi, R. Nieh, S. Gopalan, E.

Dharmarajan and J. C. Lee, ”High-quality ultra-thin HfO2 gate dielectric MOSFETs with TaN electrode and nitridation surface preparation,” in IEDM Tech. Dig., 2001, pp. 15-16.

[1.45] W. J. Zhu, Tso-Ping Ma, T. Tamagawa, J. Kim and Y. Di, ”Current transport in metal/hafnium oxide/silicon structure,” IEEE Electron Device Lett., 23, pp. 97-99,

51

2002.

[1.46] Z. J. Luo, T. P. Ma, E. Cartier, M. Copel, T. Tamagawa and B. Halpern, ”Ultra-thin ZrO2 (or silicate) with high thermal stability for CMOS gate applications,” in Symp.

on VLSI Technology, 2001, pp. 135-136.

[1.47] H. Shang, K. -L. Lee, P. Kozlowski, C. D’Emic, I. Babich, E. Sikoki, M. Ieong, H.-S. P. Wong, K. Guarini and W. Haensch, “Self-Aligned n-Channel Germanium MOSFETs With a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate,” IEEE Electron Device Lett. vol. 25, no. 3, pp. 135-137, 2004.

[1.48] H. Shang, H. Okorn-Schimdt, J. Ott, P. Kozlowski, S. Steen, E. C. Jones, and H.-S.

P. Wong, “Eletrical characterization of germanium p-channel MOSFETs,” IEEE Electron Device Lett., vol. 24, pp. 245–247, 2003.

[1.49] M. Hiratani, T. Hamada, S. Iijima, Y. Ohji, I. Asano, N. Nakanishi and S.

Kimura, ”A heteroepitaxial MIM-Ta2O5 capacitor with enhanced dielectric constant for DRAMs of G-bit generation and beyond,” in Symp. on VLSI Technology, 2001, pp. 166-169.

[1.50] Kee-Won Kwon, Chang-Seok Kang, Soon Oh Park, Ho-Kyu Kang and Sung Tae Ahn, “Thermally robust Ta2O5 capacitor for the 256-Mbit DRAM,” IEEE Electron Device Lett., 43, pp. 919-923, 1996.

[1.51] K. Stein, J. Kocis, G. Hueckel, E. Eld, T. Bartush, R. Groves, N. Greco, D.Harame and T. Tewksbury, ”High reliability metal insulator metal capacitors for silicon germanium analog applications,” in Bipolar/BiCMOS Circuits and Technology Meeting, 1997, pp. 191-194.

[1.52] P. Zurcher, P. Alluri, P. Chu, A. Duvallet, C. Happ, R. Henderson, J. Mendonca, M.

Kim, M. Petras, M. Raymond, T. Remmel, D. Roberts, B. Steimle, J. Stipanuk, S.

Straub, T. Sparks, M. Tarabbia, H. Thibieroz and M. Miller, ”Integration of thin

52

film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies,” in IEDM Tech. Dig., 2000, pp. 153-156.

[1.53] C. P. Yue and S. S. Wong, “A study on substrate effects of silicon-based RF passive components,” in IEEE MTT-S Intl. Microwave Symp., 1999, pp. 1625-1628.

[1.54] Jae-Hak Lee, Dae-Hyun Kim, Yong-Soon Park, Myoung-Kyu Sohn and Kwang-Seok Seo,” DC and RF characteristics of advanced MIM capacitors for MMIC's using ultra-thin remote-PECVD Si3N4 dielectric layers,” IEEE Microwave and Guided Wave Letters, 9, pp. 345-347, 1999.

[1.55] A. Kar-Roy, Chun Hu, M. Racanelli, C. A. Compton, P. Kempf, G. Jolly, P. N.

Sherman, Jie Zheng, Zhe Zhang and Aiguo Yin, “High density metal insulator metal capacitors using PECVD nitride for mixed signal and RF circuits,” in IEEE International Conference , 1999, pp. 245-247.

[1.56] T. Yoshitomi, Y. Ebuchi, H. Kimijama, T. Ohguro, E. Morifuji, H. S. Momose, K.

Kasai, K. Ishimaru, F. Matsuoka, Y. Katsumata, M. Kinugawa and H. Iwai, ”High performance MIM capacitor for RF BiCMOS/CMOS LSIs,” in Bipolar/BiCMOS Circuits and Technology Meeting, 1999, pp. 133-136.

[1.57] C-M Hung, Y.-C. Ho, I.-C. Wu, and K. O, “High-Q capacitors implemented in a CMOS process for low-power wireless applications, ” in IEEE MTT-S Int.

Microwave Symp. Dig., pp. 505-511, 1998.

[1.58] J. A. Babcock, S. G. Balster, A. Pinto, C. Dirnecker, P. Steinmann, R. Jumpertz, and B. El-Kareh, “Analog characteristics of metal-insulator-metal capacitors using PECVD nitride dielectrics,” IEEE Electron Device Lett., vol. 22, pp.230-232, May 2001.

[1.59] C. H. Ng, K. W. Chew, and S. F. Chu, “Characterization and comparison of PECVD silicon nitride and silicon oxynitride dielectric for MIM capacitors,” IEEE Electron

53

Device Lett., vol. 24, pp. 506-508, Aug. 2003.

[1.60] L. Y. Tu, H. L. Lin, L. L. Chao, D. Wu, C. S. Tsai, C. Wang, C. F. Huang, C. H. Lin, and J. Sum, “Characterization and comparison of high-κ     metal-insulator-metal(MIM) capacitors in 0.13 μm Cu BEOL for mixed-mode and RF applications,” in Symp. VLSI Tech. Dig., 2003, pp. 79-80

[1.61] Z. Chen, L. Guo, M. Yu, and Y. Zhang, “A study of MIMIM on-chip capacitor using Cu/SiO2 interconnect technology,” IEEE Microwave and Wireless Components Lett., vol. 12, pp. 246-248, July 2002.

[1.62] C. Zhu, H. Hu, X. Yu, A. Chin, M. F. Li, and D. L. Kwong, “Dependences of VCC (voltage coefficient of capacitance) of high-κ HfO2 MIM capacitors: an unified understanding and prediction,” in IEDM Tech. Dig., pp. 379-382, Dec. 2003.

[1.63] S. J. Kim, B. J. Cho, M-F. Li, C. Zhu, A. Chin and D. L. Kwong, “HfO2 and Lanthanide-deoped HfO2 MIM capacitors for RF/mixed IC applications,” in Symp.

on VLSI Tech. Dig., 2003, pp. 77-78.

[1.64] S. J. Kim, B. J. Cho, S. J. Ding, M-F. Li, M. B. Yu, C. Zhu, A. Chin, and D.-L.

Kwong, “Engineering of voltage nonlinearity in high-κ ΜΙΜ capacitor for analog/mixed-Signal ICs,” in Symp. On VLSI Tech. Dig., 2004, pp. 218-219

[1.65] H. Hu, S. J. Ding, H. F. Lim, C. Zhu, M.F. Li, S.J. Kim, X. F. Yu, J. H. Chen, Y.

F.Yong, B. J. Cho, D.S.H. Chan, S. C. Rustagi, M. B. Yu, C. H. Tung, A. Du, D. My, P. D. Fu, A. Chin, and D. L. Kwong, “High Performance Hf02-Al203 Laminate MIM Capacitors by ALD for RF and Mixed Signal IC Applications,” in IEDM Tech.

Dig., 2003, pp. 879-882.

[1.66] T. Ishikawa, D. Kodama, Y. Matsui, M. Hiratani, T. Furusawa, and D. Hisamoto,

“High-capacitance Cu/Ta2O5/Cu MIM structure for SoC applications featuring a single-mask add-on process, ” in IEDM Tech. Dig., 2002, pp. 940-942.

54

[1.67] M.Y. Yang, C.H. Huang, A. Chin, C. Zhu, B.J. Cho, M.F. Li, and D. L. Kwong,

“Very high density RF MIM capacitors (l7fF/μm2) using high-κ A1203 doped Ta205

dielectrics, ” IEEE Microwave & Wireless Comp. Lett., vol. 13, pp. 431-433, Oct.

2003.

[1.68] C. H. Huang, M.Y. Yang, A. Chin, C. X. Zhu, M. F. Li, and D. L. Kwong, “High density RF MIM capacitors using High-κ AlTaOx dielectrics, ” in IEEE MTT-S Int.Microwave Symp. Dig., vol. 1, 2003, pp. 507-5 10.

[1.69] S. B. Chen, J. H. Lai, K. T. Chan, A. Chin, J. C. Hsieh, and J. Liu,

“Frequency-dependent capacitance reduction in high-κ AlTiOx and Al203 gate dielectrics from IF to RF frequency range, ” IEEE Electron Device Lett., vol. 23, pp.

203 -205, April 2002.

[1.70] S. J. Kim, B. J. Cho, M. B. Yu, M.-F. Li, Y.-Z. Xiong, C. Zhu, A. Chin, and D. L.

Kwong, “High capacitance density (>l7fF/μm2) Nb205-based MIM capacitors for future RF IC applications, ” in Symp. on VLSI Tech. Dig., 2005, pp. 56-57.

[1.71] K. C. Chiang, C. H. Lai, Albert Chin, T. J. Wang, H. F. Chiu, Jiann-Ruey Chen, S. P.

McAlister, and C. C. Chi, “Very high density (23fF/μm2) RF MIM capacitors using high-κ TiTaO as the dielectric, ” IEEE Electron Device Lett., vol. 26, pp. 728-730, October 2005.

[1.72] K. C. Chiang, Albert Chin, C. H. Lai, W. J. Chen, C. F. Cheng, B. F. Hung, and C .C.

Liao, “Very high-κ and high density TiTaO MIM capacitors for analog and RF applications, ” in Symp. on VLSI Tech. Dig., 2005, pp. 62-63.

[1.73] K. C. Chiang, C. C. Huang, Albert Chin, W. J. Chen, S. P. McAlister, H. F. Chiu, Jiann-Ruey Chen, and C. C. Chi, “High-κ Ir/TiTaO/TaN capacitors suitable for analog IC applications, ” IEEE Electron Device Lett., vol. 26, pp. 504-506, July 2005.

55

[1.74] K. C. Chiang, C. C. Huang, H. C. Pan and C. N. Hsiao, J. W. Lin, I. J. Hsieh, C. H.

Cheng, C. P. Chou, Albert Chin, H. L. Hwang and S. P. McAlister, “Thermal Leakage Improvement by Using a High Work-Function Ni Electrode in High-κ TiHfO MIM Capacitors, ”J Electrochem. Soc., vol. 154, p. G54-57, 2007.

Chaper2

[2.1] C. H. Cheng, H. C. Pan, H. J. Yang, C. N. Hsiao, C. P. Chou,S. P. McAlister, and A.

Chin, “Improved high-temperature leakage inhigh-density MIM capacitors by using a TiLaO dielectric and an Irelectrode,” IEEE Electron Device Lett., vol. 28, no. 12, pp. 1095–1097,Dec. 2007.

Chaper3

[1.1] J. A. Babcock, S. G. Balster, A. Pinto, C. Dirnecker, P. Steinmann, R. Jumpertz and B. El-Kareh, IEEE Electron Device Lett., 2001;22:230-2.

[3.2] C. H. Ng, K. W. Chew and S. F. Chu, IEEE Electron Device Lett., 2003;24:506-8.

[3.3] T. Ishikawa, D. Kodama, Y. Matsui, M. Hiratani, T. Furusawa and D. Hisamoto, IEDM Tech. Dig., 2002, p. 940-2.

[3.4] S. B. Chen, J. H. Lai, A. Chin, J. C. Hsieh and J. Liu, IEEE Electron Device Lett., 2002;23:185-8.

[3.5] C. H. Cheng, S. H. Lin, K. Y. Jhou, W. J. Chen, C. P. Chou, F. S. Yeh, J. Hu, T.

Arikado, S. P. McAlister and Albert Chin, IEEE Electron Device Lett., 2008;29:845-7.

[3.6] X. Yu, C. Zhu, H. Hu, A.Chin, M. F. Li, B. J. Cho, D.-L. Kwong, P. D. Foo and M.

B. Yu, IEEE Electron Device Lett., 2003;24:63-5.

[3.7] H. Hu, S. J. Ding, H. F. Lim, C. Zhu, M.F. Li, S.J. Kim, X. F. Yu, J. H. Chen, Y. F.

Yong, B. J. Cho, D.S.H. Chan, S. C. Rustagi, M. B. Yu, C. H. Tung, A. Du, D. My, P. D. Fu, A. Chin and D. L. Kwong, IEDM Tech. Dig., 2003, p. 379-82.

56

[3.8] S. J. Kim, B. J. Cho, M.-F. Li, C. Zhu, A. Chin and D. L. Kwong, Symp. On VLSI Tech. Dig., 2003, p. 77-8.

[3.9] S. J. Kim, B. J. Cho, M. B. Yu, M.-F. Li, Y.-Z. Xiong, C. Zhu, A. Chin and D. L.

Kwong, Symp. on VLSI Tech. Dig., 2005, p. 56-7.

[3.10] K. C. Chiang, Albert Chin, C. H. Lai, W. J. Chen, C. F. Cheng, B. F. Hung and C. C.

Liao, Symp. on VLSI Tech. Dig., 2005, p. 62-3.

[3.11] K. C. Chiang, C. C. Huang, A. Chin, W. J. Chen, H. L. Kao, M. Hong, and J. Kwo, Symp. on VLSI Tech. Dig., 2006, p. 126-7.

[3.12] C. C. Huang, C. H. Cheng, K. T. Lee, and B. H. Liou, Electrochem. Solid-State Lett., 2007;12(4):H123.

[3.13] C. H. Cheng, H. C. Pan, H. J. Yang, C. N. Hsiao, C. P. Chou, S. P. McAlister and Albert Chin, IEEE Electron Device Lett., 2007;28:1095-7.

[3.14] P. Sivasubramani, M. J. Kim, B. E. Gnade, R. M. Wallace, L. F. Edge, D. G.

Schlom, H. S. Craft, and J.-P. Maria, Appl. Phys. Lett., 2005;86:201901.

[3.15] L. F. Edge, D. G. Schlom, S. A. Chambers, E. Cicerrella, J. L. Freeouf, B. Holländer, and J. Schubert, Appl. Phys. Lett., 2004;84:726,.

[3.16] C. H. Cheng, H. C. Pan, C. C. Huang, C. P. Chou, C. N. Hsiao, J. Hu, M. Hwang, T.

Arikado, S. P. McAlister and Albert Chin, IEEE Electron Device Lett., 2008;29:1105-7.

[3.17] L. F. Edge, D. G. Schlom, R. T. Brewer, Y. J. Chabal, J. R. Williams, S. A.

Chambers, Y. Yang, S. Stemmer, M. Copel, B. Hollander, and J. Schubert, Appl.

Phys. Lett., 2004;84:4629.

[3.18] X. B. Lu, Z. G. Liu, Y. P. Wang, Y. Yang, X. P. Wang, H. W. Zhou, and B. Y.

Nguyen, J. Appl. Phys. 2003;94:1229.

[3.19] Y. H. Wu, C. K Kao, B. Y. Chen, Y. S. Lin, M. Y. Li and H. C. Wu, Appl. Phys.

57

Lett., 2008;93:033511.

[3.20] C. H. Cheng, H. C. Pan, S. H. Lin, H. H. Hsu, C. N. Hisao, C. P. Chou and F. S. Yeh and Albert Chin, Journal of the Electrochemical Society, 2008;155:G295.

[3.21] K. Xiong and J. Robertson, Microelectron. Eng. 2005;80:408.

[3.22] P. Gonon and C. Vallée, Appl. Phys. Lett., 2007;90:142906.

[3.23] Bing Miao, Rajat Mahapatra, Nick Wright, and Altton Horsfall, J. Appl. Phys., 2008;104:054510.

[3.24] Chun-Chen Yeh, T. P. Ma, Nirmal Ramaswamy, Noel Rocklein, Dan Gealy, and Thomas Graettinger, and Kyu Min, Appl. Phys. Lett., 2007;91:113521.

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