中 華 大 學

中 華 大 學 碩 士 論 文

高介電層氧化鑭鋁基底在金屬氧化物半導 體與金屬電容之研究與應用

High-κ LaAlO-Based Dielectrics for MIM and MOS Application

系 所 別：電機工程學系碩士班 學號姓名：M09701025 陳柏君 指導教授：謝焸家 教授

荊鳳德 教授

中 華 民 國 九 十 九 年 七 月

i

摘 要

隨著IC製程的演進，元件尺寸越做越小，絕緣層的厚度也相對地必須變薄，以符 合元件的要求。但薄膜的絕緣能力卻因而變差，使得直接穿隧漏電流(Direct Tunneling) 的增加，造成元件漏電流與功率損耗，故使用高介電常數材料(High dielectric constant)

取代SiO2，能夠有效降低直接穿隧漏電流，一般稱為High-κ材料。High-κ材料可有效

降低等效氧化層厚度(EOT)，提升驅動電流密度及降低臨界電壓，進而得到大的驅動

電流元件特性。許多研究顯示，鑭系(lanthanum，La)元素目前最有希望取代SiO2作為

閘極介電層之材料，因此選定La系元素作為研究主題。

在MIM 實驗中，將 TiO2摻雜LaAlO3形成高介電係數介電質(TLAO)，作為金屬

(MIM)電容器中的绝緣體。製作出的電容器特徵顯示：高电容密度 23.2 fF/μm²和在-1

V 時的低漏電流 7.5×10^-7 A/cm²，相對於高介電質TiLaO (TLO)， TLAO 因含有 Al203

而造成更低的漏電流、更小的非線形性電壓和更好的時間相依介電崩潰(TDDB)特性。

TDDB (Time Dependent Dielectric Breakdown) 在半導體可靠度中，是一個研究故障機 制的重要方法，其目的在於檢測出閘極介電層的生命期，提供規劃最佳製程設計。故

本研究的重要突破在於以高介電係數介電質 TiLaO 結合 Al2O3 來改善 MIM 電容特

性。

在MOS實驗中為了不斷地改善金氧半電晶體特性，如何提高電晶體的驅動電流 及較小的漏電流為重點所在。雖然高介電絕緣層可以大幅降低閘極漏電流，但對於高 品質特性電路而言卻急遽降低了元件的遷移率。為了解決這個問題，本研究利用

High-κ LaAlO3結合鍺/矽基板高載子遷移率特性發展出鍺/矽電晶體，可達到低缺陷和

高遷移率。對於提升電洞及電子的遷移率有重大改善，並有效阻止高介電絕緣層的結 晶化、介面反應及等效氧化層的減少。本研究所發展之鍺/矽電晶體的遷移率大約比 一般矽元件大兩倍。

為了進一步發展矽鍺電晶體的製程，本研究發展出結合自我對準的金屬閘極/高 介電絕緣層/鍺高遷移率電晶體於矽基板元件上，希望此製程對未來超大型積體電路

ii

能有相當貢獻。

關鍵詞:金屬閘極 ; 金屬電容器 ; 金屬氧化物半導體電容 ; 氧化鑭鋁 ; 矽鍺矽基 板。

iii

Abstract

In the scaling of CMOS, reducing the thickness of gate stack with lower leakage current plays an important role. Although the leakage current of the devices with the same gate dielectric reduces with the scaling gate length and width, that leakage current density increases with the scaling of gate dielectrics exponentially. Therefore, the gate leakage current increases with the size decreasing. The larger leakage current not only causes the high power consumption but also degrade the reliability of the devices. Many studies have pointed out that the lanthanum oxide (La2O3) is a good candidate to replace of conventional SiO2 to gain thinner EOT and lower the gate leakage. Therefore, we fabricate the La2O3-based dielectrics by MOS and MIM structure and investigate the electrical and reliability characteristics.

For the MIM experiment, we studied a TiO2 mixed LaAlO3 dielectric (TLAO) by metal-insulator-metal (MIM) capacitors. The capacitor characteristics showed a high capacitance density of 23.2 fF/μm² and a low leakage current of 7.5×10^-7 A/cm² at -1V.

Compared to the control samples of TiLaO (TLO), TLAO dielectrics with Al2O3 doping exhibited lower leakage current, smaller voltage nonlinearity and better time-dependent dielectric breakdown (TDDB) performance. Therefore, the TiO2-based dielectrics with the introduction of Al2O3 might be favorable for the improved engineering of MIM capacitors.

For the high performance Ge MOSFET, both large drive current and high mobility are reached but poor interface stability is a major issue for the process integration. To overcome this problem, we have developed a low temperature Si capping Ge/Si substrate (SGS) to achieve low dislocation Ge channel. Both hole and electron mobility can be largely enhanced by this SGS substrate. In this study, we have demonstrated a Ge nMOSFET using a LaAlO3 (LAO) dielectric on Ge/Si substrate. The nMOSFET device

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shows the well-behaved C-V behavior, small EOT of ~1.5nm and low leakage current of 3.97×10^-5 A/cm² at Vfb -1V. Therefore, the LAO dielectric can be integrated into to Ge substrate successfully and may be a good candidate material for new channel MOSFET.

Index: Metal Gate ; Metal-Oxide-Semiconductor(MOS) ; Metal-Insulator-Metal (MIM) ; LaAlO3 ; Silicon-Germanium-Silicon substrate.

v

誌謝

首先，我要向我的指導教授，荊 鳳德老師與謝 焸家老師致上最高的敬意。感謝 過去這兩年中，他們在課業、研究與生活上，不停的給我指導與鼓勵。在這二年的學 習生涯中，無論是在課業、研究或平日會議時，讓我學習到研究應有的態度和方法，

也使我在專業研究以及待人處事上獲益匪淺，這兩年的學習也讓我幸運考取清大工科 博士班，有機會繼續深造。

感謝陳 維邦、鄭 淳護及蘇 迺超學長帶我進入半導體領域，感謝張明峯、林士 豪、劉思麟、周坤億、蔡竣揚、謝博璿、羅方鴻、唐建智學長對我不斷的給予建議與 指導，感謝一起做實驗的同學李宗翰、林智偉，有你們的陪伴與討論，實驗過程不再 枯燥乏味而是充滿著歡樂，在實驗過程協助與照顧，此論文是大家幫忙、努力出來的 成果。

再者，由衷地感激中華大學(CHU)、國立交通大學奈米中心(NFC)以及國家奈米 元件實驗室(NDL)提供研究的環境和設備以及技術人員熱心的協助，使我的研究可以 順利進行。有了你們的大力幫忙，使我順利地完成此論文，在此獻上我最深的敬意。

最後，感謝支持、關心與幫助過我的女朋友、朋友、埔心幫兄弟們、湖口幫六人組、

以及長輩們。尤其是我的家人跟女友，有了他們的支持與鼓勵，陪我度過許多挫折和 難關；在我開心時，能一起分享我的喜悅。因為有你們的相伴，使我順利完成碩士學 業與論文。在此，我願將這份榮耀與你們一同分享，感謝你們，我愛你們。

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Contents

Abstract (in Chinese) ……… i

Abstract (in English) ……… iii

Acknowledgement ……… v

Contents ……… vi

List of Figure ……… viii

List of Tables ……… x

CHAPTER 1 Introduction 1.1 Motivation to Study Metal-Gate and High-κ Technology………… 1

1.2 Which Dielectric could be a Good Candidate Beyond 22 nm…… 3

1.3 The Application of Metal Electrodes and High-κ Dielectrics…… 7

1.3.1 Using a High-κ materials for MIM Capacitors……… 9

CHAPTER 2 Experimental Procedure 2.1 The fabrication of Metal-Insulator-Metal capacitors……… 12

2.2 The Electrical Measurement of High-κ MIM Capacitors Using TLAO Dielectric……… 13

2.3 The process flow of MIM capacitor……… 14

2.4 The fabrication of MOS devices……… 21

2.5 The Electrical Measurement of High-κ MOS Using LaAlO3 Dielectric……… 22

2.6 The process flow of MOS capacitors……… 23

CHAPTER 3 Results and Discussion 3.1 Metal-Insulator-Metal device Characteristics……… 34

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3.1.1 CONCLUSIONS……… 40

3.2 C-V and J-V Characteristics of MOS devices……… 40

CHAPTER 4 Conclusions 4.1 Conclusions……… 43

4.2 Suggestions for Future Works……… 44

Reference Chaper1 ……… 45

Chaper2 ……… 55

Chaper3 ……… 55

著作 ……… 58

Vita ……… 62

viii

List of Figures CHAPTER 1

Fig.1-1 The band offset of popular high-κ materials.

CHAPTER 2

Fig.2-1 200nm Silicon dioxide growth.

Fig.2-2 The lower electrodes were formed by depositing a 200nm Ta layer.

Fig.2-3 The lower electrodes were formed by depositing a 50nm TaN on a 200nm Ta layer.

Fig.2-4 The TaN layer was treated by NH3 plasma nitridation at 100W to improve the electrode interface.

Fig.2-5 Depositing TiLAO dielectric by PVD.

Fig.2-6 TaN was deposited on the dielectric and patterned to form the top capacitor electrode(step 1).

Fig.2-7 TaN was deposited on the dielectric and patterned to form the top capacitor electrode(step 2).

Fig.2-8 TaN was deposited on the dielectric and patterned to form the top capacitor electrode(step 3).

Fig.2-9 RCA Clean.

Fig.2-10 Deposit Si buffer 200nm.

Fig.2-11 Deposit Ge 5nm.

Fig.2-12 Deposit Si capping layer 1.5nm.

Fig.2-13 Deposit LaAlO3 5nm.

Fig.2-14 LaAlO3 PDA 400^oC.

Fig.2-15 Spin photoresist.

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Fig.2-16 Photoresist deposition and exposure by mask.

Fig.2-17 Develop by FHD-5 Fig.2-18 TaN deposition.

Fig.2-19 Remove photoresist.

Fig.2-20 RTA 450^oC and 550^oC.

Fig.2-21 Backside Aluminum deposition 5000A.

CHAPTER 3

Fig. 3-1 (a) C-V and (b) J-V characteristics of TaN/[TLO and TLAO]/TaN MIM capacitors. Measured and simulated J-E^1/2 of TaN/[TLO and TLAO]/TaN capacitors is shown in the inset.

Fig. 3-2 (a) ΔC/C-V (b) TCC characteristics of TaN/[TLO and TLAO]/TaN MIM capacitors.

Fig. 3-3 (a) ΔC/C0-E and (b) ln(ΔC(f)/C0) versus ln(f) plots for MIM capacitors with TLO and TLAO dielectrics

Fig. 3-4 (a) Stress time dependence of VCC-α and (b) TDDB characteristics for TLO and TLAO MIM capacitors.

Fig. 3-5 C-V of TaN/LaAlO3/Si/Ge/Si n-MOS capacitors at 450 and 550^oC RTA.

Fig. 3-6 J-V of TaN/LaAlO3/Si/Ge/Si n-MOS at 450 and 550^oC RTA.

x

List of Tables CHAPTER 1

Table1-1 The International Technology Roadmap of SIA for Semiconductor 1999.

CHAPTER 3

Table 3-1 A comparison of MIM capacitors with various high-k dielectrics and high work-function top electrodes.

1

Chapter 1

Introduction

1.1 Motivation to Study Metal-Gate and High-κ Technology

In the scaling of CMOS, reducing the thickness of gate stack with lower leakage current plays an important role. Although the leakage current of the devices with the same gate dielectric reduces with the scaling gate length and width, that leakage current density increases with the scaling of gate dielectrics exponentially. Therefore, the gate leakage current increases as the device size decreases. The larger leakage current will not only cause the higher power consumption but also degrade the reliability of the devices [1.1]-[1.2].

Using the material with high dielectric constant (high-κ), the physical thickness of the dielectric in the devices can be increased without the reduction of capacitance density.

Since the leakage current is related to the physical thickness, the increasing thickness of high-κ dielectric can reduce the leakage current of the devices. Although high-κ dielectrics often exhibits smaller band gap, weaker bond, and higher defect density than SiO2, the high-κ dielectrics with the same effective oxide thickness (EOT) with SiO2 still shows lower leakage current than SiO2 by several orders [1.3]-[1.4]. That is the reason why high-κ dielectrics have drawn much attention for future gate dielectrics.

According to the ITRS (International Technology Roadmap for Semiconductor) of SIA as shown in Table. 1-1 [1.5]-[1.6], the thickness of gate oxide have to be below 15 Å

2

after 2005. Moreover, the gate length and bias voltage reduces by 11 % every year while the drive current has to be maintained. Therefore, the continual scaling of gate dielectric is an inevitable trend in proceeding CMOS technology. However, the operation frequency of the device below the generation of 100 nm will be over GHz [1.7] and the electrical characteristic of high-κ dielectrics at that frequency plays an important role for the use of high-speed devices. Even some high-κ dielectrics show good electrical characteristics at low frequency, the performance of those at RF region could possibly degrade. Therefore, it is important to find out the high-κ dielectric that exhibits superior characteristics at both high and low frequency.

Recently, some high-κ dielectrics have been widely studied and the characteristics and issues of those materials have also been reported. The high-κ dielectrics show good performances are always accompanied by another drawbacks. Finding out the most suitable high-κ dielectric for the use of device and altering the device structure or process to meet the requirement of the high-speed device are significant tasks to implant high-κ dielectrics to the next VLSI generation.

The poly depletion reduces the gate capacitance in the inversion regime and hence the inversion charge density, leading to a lower gate over drive and thus degrading the device performance. As the result, metal-gate electrodes will be required for Complementary Metal–Oxide–Semiconductor (CMOS) transistors to eliminate the gate depletion and dopant penetration problems that are associated with the conventional polycrystalline silicon (poly-Si) gate electrode [1.8]. In selecting metal-gate materials for device integration, the metal work function is an important consideration since it directly affects the threshold voltage and the performance of a transistor [1.9]- [1.11].

However, thermal instability of the effective metal electrode work function (Φ) on underlying gate dielectric as well as the equivalent oxide thickness (EOT) of the gate stack

3

remains a major concern for CMOS integration. In addition, an understanding of how the gate dielectric affects Φ of the metal gate stack is scientifically and technologically important. Although the interfacial dipole theory was proposed to describe the dependence of Φ on underlying gate dielectrics [1.12], it is not clear whether it can be applied to explain the work functions instability during high-temperature source/drain annealing. The high-temperature annealing could lead to the creation of extrinsic states at the metal-dielectric interface for particular combinations of metal-gate and gate-dielectric materials, and result in metal Fermi-level pinning [1.13]. The Fermi-level pinning shifts the original low or high work-function to midgap that causes the intolerable ۋ VTۋ increase.

The possible mechanism of Fermi-level pinning is due to the interface reaction and dipole creation of high-κ dielectric with poly-Si or metal-nitride at high RTA temperatures.

Recently, the Fermi-level pinning effect caused by the threshold voltage (Vt) shifts has been reported for poly-Si gate CMOS processes with hafnium dioxide (HfO2) [1.14]–[1.20], hafnium silicate HfSiXOY [1.21], hafnium oxynitride HfOXNY [1.22], [1.23] and hafnium silicate oxynitride HfSiXOYNZ [1.24], [1.25] follow the same trend.

1.2 Which Dielectric could be a Good Candidate Beyond 22 nm

Dielectrics with higher dielectric constant than SiO2 exhibit the potential to replace the conventional thermal oxide for sub-100nm node. Not only the gate leakage current can be reduced without the reduction of drain current drive and transconductance, but also the reliability of gate dielectrics can be improved effectively [1.26], [1.27]-[1.28]. Over the recent decade, many kinds of high-κ materials have been proposed and the electrical characteristics or the related issues have been studied extensively, as shown in Fig. 1-1.

Among the high-κ simple metal oxide, Tantalum oxide (Ta2O5) and Titanium oxide

4

(TiO2) have the higher dielectric constant ranging from 25 to 80 [1.29]-[1.30], [1.31]-[1.32]. In addition, Ta2O5 still exhibits other merits including the better capacitance linearity than that of SiO2, the lower process temperature and the larger bandgap (4.65 eV) than that of the other high-κ dielectrics. However, some other issues about Ta2O5 should be noticed. First of all, crystallization and interface state will cause from post implant RTA.

Moreover, interface oxide layer between Ta2O5 and Si occurred after crystallization. Thus, effective oxide thickness increases while interface oxide layer occurred and capacitance density also decreases [1.29]. It has been reported that titanium oxide exhibits some better properties than other dielectrics in addition to the higher dielectric constant [1.33]-[1.34].

One of that is the good thermal stability when it was integrated with TiN electrode. It allows TiO2 shows dielectric characteristics after high temperature process for silicide formation [1.32]. Besides, the heat conduction rate for TiO2 is higher than that for SiO2. With the scaling of integrated circuits, the issue of power dissipation should also be taken into account [1.35]. Although TiO2 exhibits the above merits, there are still some other issues that should be considered and overcome such as the higher leakage current than that of other dielectrics with the same effective oxide thickness, lower breakdown voltage and interface oxide layer formation after post implant RTA. However, it has been reported that thickness of the interface oxide layer can be reduced by using NH3 annealing, but the flatband voltage shift and the degradation of channel mobility still occurred [1.36].

Recently, HfO2 and ZrO2 have attracted much attention due to their thermal stability with poly or TiN and TaN [1.32], [1.37]-[1.38]. In addition, they also exhibits suitable dielectric constant (25~30) and energy band gap [1.32], [1.39], for the use of MOSFET in sub-micron generation. However, oxygen tends to diffuse though HfO2 and form oxide interlayer after high temperature process and it becomes difficult to achieve the effective oxide thickness below 15 Å [1.37]. Furthermore, it exists an important issue for the

5

integration of HfO2 and ZrO2. The boron penetration effect is severe when single HfO2

serves as gate dielectric of transistors, while ZrO2 reacts with poly silicon to form Zr silicide after post implant annealing. This Zr-silicide defects increase the leakage current and degrade the reliability [1.32]. Besides, both HfO2 and ZrO2 will crystallize at the temperature higher than 500^oC. After source/drain activation, this property increases the leakage current and power dissipation of the device. The merits of high-κ dielectrics are compensated by this phenomenon [1.40]. The method to improve these characteristics of HfO2 and ZrO2 can be divided into two parts.

First of all, dense and thin capping layer was formed on the top of HfO2 or ZrO2 by sputtering thin metal film (Hf, Zr) on the top of these dielectrics followed by rapid thermal annealing at 600^oC in N2 to oxidize the nitrided layer [1.37]. Not only boron penetration can be reduced effectively, but also the properties of high oxygen diffusion coefficient for both of the two dielectrics can be improved. This method can be used for some high-κ dielectrics with high oxygen diffusion coefficient [1.37]. Secondly, to overcome the thermal unstable properties and to remain the amorphous phase for HfO2 and ZrO2 after high temperature process, doping some thermal stable material into high-κ dielectrics has been proposed and shows the promising results [1.40]-[1.41]. Due to the thermal stability at high temperature for both SiO2 and Al2O3, they are suitable for the use of doping component for multi-component dielectrics [1.42]-[1.43]. Although both SiO2 and Al2O3

can be used in multi-component dielectrics, SiO2 still has some other issues due to its low dielectric constant and high oxygen diffusion coefficient. These properties of SiO2 are the obstacles to reduce the effective oxide thickness below 15 Å. Although SiO2 increases the crystallization temperature of high-κ dielectrics effectively, large effective oxide thickness makes it impossible to implant SiO2 into the high-κ gate stack integration. Because Al2O3

exhibits the higher dielectric constant than SiO2 and the similar bandgap as well as

6

band-offset with SiO2, it is more suitable than SiO2 to serve as the dopant in high-κ dielectrics. It shows the low leakage current and high breakage voltage due to the large bandgap (>8.8 eV) and band-offset (>2 eV). It has been reported that NH3 annealing prior to dielectric deposition prevents the penetration of oxygen and reduces the formation of the excessive interfacial layer. [1.44] Similarly, extremely low oxygen diffusion coefficient (5×10^-25 cm²/s) of Al2O3 can also reduce the formation of interface oxide and achieve the effective oxide thickness below 12 Å [1.45]-[1.46]. By reason of the physical and electrical characteristics of Al2O3 mentioned above, depositing Al metal layer prior to alternate high-κ dielectrics followed by oxidation and annealing could be a simple method to acquire the thermal stability of dielectrics and the formation of minimum oxide interface layer at the same time. However, the Al2O3 with only a small κ value of ~9, limiting its application for device scaling.

Recently, lanthanum aluminate (LaAlO3, LAO), combing a high-κ La2O3 and Al2O3, has been identified as a high-κ candidate beyond Hf-based dielectrics due to its high κ ~20–25, thermodynamics stability on silicon, band gap of >5 eV, and suitable valence- and conduction-band offsets. The thermal stability of a high-κ dielectric film in direct contact with the underlying Si substrate is essential because outdiffusion of metal impurity atoms into the channel region during processing can cause carrier mobility degradation. It is well known that La2O3 has a high-dielectric constant and Al2O3 has a good thermal stability. LAO may combine their desirable chemical and electrical properties while eliminating the deficiencies of each material. It seems that LAO may have a great potential as an alternative gate dielectric material to replace SiO2 in next-generation MOSFET applications.

7

1.3 The Application of Metal Electrodes and High-κ Dielectrics

The most significant application for high-κ dielectrics is to extend the scaling of SiO2

and reduces the short channel effect and the power consumption. Without high-κ dielectric, it is impossible to prevent the exponential increase of the gate leakage current as the device scaling progresses continuously. Once the scaling is stopped due to the unacceptable power consumption and bad device reliability, the operation frequency of the device cannot have chances to be raised to higher value. Not only the bandwidth of communication cannot be broadened, but also the limits of operation speed of microprocessors appear. The gate dielectrics, no doubt, are the core of CMOS devices, while CMOS transistors are the basics of any integrated circuits. Therefore, to replace conventional oxide with high-κ dielectric is an inevitable and significant application in the next generation of VLSI technology.

Recently, the germanium substrate has attracted much attention due to the inherent merit of both much higher electron and hole mobility than Si (two times higher mobility for electrons and four times for holes)[1.47] -[1.48]. At the same time, it is also a candidate for supply voltage scaling due to its narrower band-gap than that of silicon. Many high-κ /metal-gate stacks have been investigated and gained the high-mobility devices. However thicker EOT and high-cost substrate may be the issues for the low-power and –cost CMOS devices. To lower the cost of substrate, the expensive germanium was replaced by epitaxial Si-capping germanium substrate with a compatible mobility in this study.

The continuous scaling of design rules for DRAM leaves us some difficulties to overcome. In the G-bit DRAM generation, the memory cell density is so high that the cell space can only allow dielectrics no thicker than 20nm. This requirement of thickness for dielectrics makes it impossible to use complex metal oxide such as BST as the dielectric layers. Because of the difficulty of conformal CVD for complex metal oxide, the high

8

aspect ratio of the trench for DRAM seems to be the other challenge to integrate the complex metal oxide into G-bit DRAM generation [1.49]. Owing to the high dielectric constant, good step coverage and minimum thickness limit, simple metal oxide such as Ta2O5, Al2O3 and TiO2 are thought the promising materials in the application of DRAM [1.49]-[1.50]. Among the simple metal oxide, Ta2O5 exhibits better step coverage than others do but higher leakage current and degradation after high temperature process. The former can be reduce using oxygen annealing while the latter can be solve utilizing a new electrode material reported in the literature [1.50]. Recently, there has been much attention on TiO2 due to its high dielectric constant (40~180) and well thermal stability. High temperature crystallization can cause not only the increase of leakage current but also reduce the breakdown voltage as well as non-uniform leakage current. Therefore, thermal stability is a critical issue in the choice of a high-κ dielectric for trench capacitor DRAMs.

In addition to TiO2, Al2O3 also attracts much attention due to its thin effective oxide thickness even in the trench with the aspect ratio of 60 and top critical dimension of 80 nm.

These results indicate that simple metal oxide is suitable to enhance the performance and density of DRAM.

To fabricate monolithic microwave integrated circuits successfully, both active and passive components with reliable, repeatable and predictable performance are required.

Among them, the capacitor used in filtering, decoupling and network matching plays a significant role in front end or mixed signal circuits. The requirement for capacitors includes high capacitance density, low voltage coefficients, good capacitor matching, precision control of values and low parasitic effects. The method to increase the capacitance density, in other words, to reduce the area occupied by capacitors, is utilizing thin dielectrics with high dielectric constant. Recently, some kinds of dielectrics and approaches have been proposed to achieve the goal of high capacitance and the other good

9

performance [1.51]-[1.55]. Instead of SiO2 with low dielectric constant, Si3N4 deposited by plasma enhanced chemical vapor deposition (PECVD) has been studied in the past years [1.52], [1.54]-[1.55].

Although Si3N4 shows good linearity and reliability, the capacitance density still needs to be increased. However, Si3N4 fabricated by PECVD has the minimum thickness limit and the defect density of nitride is higher than that of other high-κ dielectrics.

Therefore, high-κ dielectrics with good linearity and quality can be a choice to develop the innovative and useful RF capacitors [1.56]. The searches for new memory device have attracted much attention. The current DRAM scaling is limited by the available high-κ dielectrics, while the scaling of flash memory is also limited by the required relatively thick gate oxide.

1.3.1 Using a High-κ materials for MIM Capacitors

Dielectrics with higher dielectric constant then SiO2 exhibit the potential to reolace the conventional thermal oxide. While scaling down the device size of Metal-Insulator-Metal(MIM) capacitors used for Analog, RF and DRAM function in ICs, there are two methods to achieve higher capacitance desity(ε⁰ κ/td) for scaling down device size. One is to decrease the dielectric thickness(td)and the other is to use high-κ materials. The former way will rapidly increase the undesired leakage current and voltage dependence of capacitor (ΔC/C). Properly, the latter one is the only way to make it without increasing leakage current. The performance requirements of MIM capacitors are the high capacitance density, low leakage current, small voltage dependence of the capacitance (ΔC/C) are also necessary for analog functions. In order to meet these requirements, high dielectric constant (High-κ) materials [1.57]-[1.74] provide the only solution. This is because the decreasing of the dielectric thickness (td) increases the capacitance density and degrades both the leakage current and ΔC/C performance.

10

Therefore the high-κ dielectrics used in MIM capacitors have evolved form SiON(κ∼4-7) [1.58]-[1.60], Al2O3 (κ∼10) [1.67], HfO2 (κ∼22) [1.62]-[1.65], Ta2O5 (κ∼25) [1.66]-[1.67]

to Nb2O5 (κ∼40) [1.70]. These good performances also have potential for DRAM and embedded SoC, along with Analog functions using simple process.

(1) Lower parasitic resistance in storage nodes.

(2) Lower temperature process.

(3) Higher stored charge per unit area with high-κ dielectrics.

(4) Enables lower aspect ratio structures.

Therefore, MIM capacitors are especially suitable for mass production in semiconductor fabrication processes.

In this study, to overcome this problem, we report two high-ΔEC dielectrics, which mixing higher-κ TiO2 with La2O3 (TLO) or LaAlO3 (TLAO) as dielectrics to further reduce the leakage current, without sacrificing the capacitance densities. The TiLaO (TLO) MIM capacitors have reported a low leakage current and small thermal leakage variation at a high capacitance density of 24 fF/μm² by using a high work-function Ir electrode. Recently, the La2O3 film with the introduction of Al2O3 to improve the moisture issue have been demonstrated and the reported LaxAlyO3 dielectrics as gate dielectrics also show a high permittivity near La2O3, good thermal stability and large band gap (~6 eV).

Therefore, we proposed TiO2-based dielectrics (TLO and TLAO) with the introductions of lanthanide oxides (LaAlO3 and La2O3) for MIM capacitors and showed their potential in comparison with other MIM capacitors. For constant-voltage stress induced degradation, the TLAO dielectrics exhibit a smaller degree of degradation in voltage linearity and better TDDB performance than TLO without Al2O3 doping.

11

Fig. 1-1 The band offset of popular high-κ materials.

Table 1-1 The International Technology Roadmap of SIA for Semiconductor 1999.

12

Chapter 2

Experimental Procedure

2.1 The fabrication of Metal-Insulator-Metal capacitors

The MIM capactiors were fabricated on 200 nm SiO2 which had been deposited on a Si wafer. The capacitor electrodes were formed by depositing 50nm TaN on a 200nm Ta layer, where the thick Ta was chosen to reduce the parasitic resistance of the electrode and the TaN served as a barrier layer for the TLAO. After patterning the lower electrode, the TaN was treated by NH3 plasma nitridation at 100 W, to improve the lower interface. Then the TLAO dielectric was deposited by PVD dielectric layers were then deposited using dual E-GUN. Finally, TaN was deposited and patterned to form the top capacitor electrode.

The MIM capacitor area is 180 μm × 180μm. The fabrication process is listed as follows:

1. 4 inch p-type or n-type Si wafer (100).

2. RCA clean.

3. 200nm Silicon dioxide growth.

4. The lower capacitor electrodes were formed by depositing 50 nm TaN on a 200nm Ta layer.

5. The TaN was treated by NH3 plasma nitridation at 100W, to improve the lower interface.

6. Then the TLAO dielectric were deposited by Dual E-gun and followed by a 400℃

PDA to activate the dielectric.

7. Finally, sputtered TaN was deposited and patterned to form the top capacitor electrode.

13

2.2 The Electrical Measurement of High-κ MIM Capacitors Using TLAO Dielectric

The fabricated MIM capacitors were characterized by current-voltage (J-V)and capacitance-voltage(C-V) measurements using a HP4156C curve analyzer and HP4284A precision LCR meter, respectively.

14

2.3 The process flow of MIM capacitor

Fig.2-1 200nm Silicon dioxide growth.

Fig.2-2 The lower electrodes were formed by depositing a 200nm Ta layer.

15

Fig.2-3 The lower electrodes were formed by depositing a 50nm TaN on a 200nm Ta layer.

16

Fig.2-4 The TaN layer was treated by NH3 plasma nitridation at 100W to improve the electrode interface.

17

Fig.2-5 Depositing TiLAO dielectric by PVD.

18

Fig.2-6 TaN was deposited on the dielectric and patterned to form the top capacitor electrode(step 1).

19

Fig.2-7 TaN was deposited on the dielectric and patterned to form the top capacitor electrode(step 2).

20

Fig.2-8 TaN was deposited on the dielectric and patterned to form the top capacitor electrode(step 3).

21

2.4 The fabrication of MOS devices

After standard cleaning, an undoped 200-nm Si buffer, an undoped 5-nm Ge, and an undoped 1.5-nm Si capping layer were grown on p-type (100) Si wafers (5 × 10¹⁵ cm⁻³ doping) by ultrahigh-vacuum chemical vapor deposition at 500 ^◦C and 5 × 10⁻⁴ torr.

The native oxide of the Si capping layer was removed using a dilute HF solution.

Since Ge can be oxidized by water and air and GeO2 is dissolvable by water, the Si capping layer in this design is necessary to prevent the loss of the thin Ge layer during the cleaning process. A 5-nm-thick LaAlO3 [2.1] with κ of 45 was deposited and followed by 400 ^◦C postdeposition annealing in an oxygen ambient. A 200-nm TaN layer was then deposited by PVD and patterned to form the MOS. The fabricated devices were characterized by capacitance–voltage (C–V ) and current–voltage (J–V ) measurements.

1. Initial standard RCA cleaning for (100) 6 inch p-type(100) oriented silicon wafers. The resistivity was ranging from 1~10 Ω-cm.

2. An undoped 200-nm Si buffer, an undoped 5-nm Ge, and an undoped 1.5-nm Si capping layer were grown on p-type (100) Si wafers (5 × 10¹⁵ cm⁻³ doping) by ultrahigh-vacuum chemical vapor deposition at 500 ^◦C and 5 × 10⁻⁴ torr.

3. The native oxide of the Si capping layer was removed by dilute HF solution.

4. Then the LaAlO3 5nm dielectric was deposited by Dual E-gun.

5. After post-deposition anneal (PDA) at furnace 400℃for 5 minute in O2 ambient.

6. TaN was deposited and patterned to form the top electrode by sputter.

7. Backside Aluminum deposition 5000A.

8. Finally, MOS at 450 ^oC and 550^oC RTA.

22

2.5 The Electrical Measurement of High-κ MOS Using LaAlO

Dielectric

The fabricated MOS capacitors were characterized by current-voltage (J-V)and capacitance-voltage(C-V) measurements using aHP4156C curve analyzer and HP4284A precision LCR meter, respectively.

23

2.6 The process flow of MOS capacitors

Fig.2-9 RCA Clean.

Fig.2-10 Deposit Si buffer 200nm.

24

Fig.2-11 Deposit Ge 5nm.

Fig.2-12 Deposit Si capping layer 1.5nm.

25

Fig.2-13 Deposit LaAlO3 5nm.

26

Fig.2-14 LaAlO3 PDA 400^oC.

27

Fig.2-15 Spin photoresist.

28

Fig.2-16 Photoresist deposition and exposure by mask.

29

Fig.2-17 Develop by FHD-5.

30

Fig.2-18 TaN deposition.

31

Fig.2-19 Remove photoresist.

32

Fig.2-20 RTA 450^oC and 550^oC.

33

Fig.2-21 Backside Aluminum deposition 5000A.

34

Chapter 3

Results and Discussion

3.1 Metal-Insulator-Metal device Characteristics

In Fig. 3-1(a) and (b) we show the C-V and J-V characteristics of TLO and TLAO MIM capacitors. A high capacitance density of 23.2 fF/μm² at 500 kHz is obtained for TLAO dielectrics while its corresponding leakage current of 7.5×10^-7 A/cm² at -1 V reduces nearly 1 order of magnitude compared to TLO case with a slightly higher 24-fF/μm² density. The asymmetric current-voltage curve seen in Fig.3-1(b) may be associated with a partially oxidation of the lower TaN electrode.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 16

18 20 22 24 26 28 30 32

20 22 24 26 28 30 32 34

100 kHz 300 kHz 500 kHz

TaN/TLAO/TaN, C~23.2 fF/μm² TaN/TLO/TaN, C~ 24 fF/μm²

Voltage (V)

Capacitance density(fF/μm2 ) (a)

-2 -1 0 1 2

10^-7 10^-5 10^-3 10^-1 10¹ 10³

(b)

TaN/TLO/TaN, C~ 24 fF/μm² TaN/TLAO/TaN, C~ 23.2 fF/μm²

Current density (A/cm2 )

Voltage(V)

Gate injection Bottom injection

Fig. 3-1 (a) C-V and (b) J-V characteristics of TaN/[TLO and TLAO]/TaN MIM capacitors. Measured and simulated J-E^1/2 of TaN/[TLO and TLAO]/TaN capacitors is shown in the inset.

Table 3-1 summarizes the reported MIM capacitors with various high-κ dielectrics and work-function electrodes. As shown in Table 3-1, the leakage current measured for TaN/TLAO/TaN is three times lower than that of Ir/TiTaO/TaN MIM capacitor at a comparable capacitance density of ~23 fF/μm². Since the work function of the TaN (4.6 eV)

35

is much lower than Ir (5.27 eV) on dielectrics, the comparable leakage current indicates that the TLAO dielectric is a better candidate for MIM capacitors than TiTaO. Thus, we suggest that this improved leakage current is due to the LaAlO3 doping with a high ΔEC of

> 2eV [3.17]-[3.18] to lower the leakage current.

In addition, we also can see that the laminated MIM capacitors (Table 3-1), such as Al2O3-HfO2, Al2O3/TiO2/Al2O3 and ZrO2/Al2O3/ZrO2 [3.19], use a high-ΔEC (~3.2eV) Al2O3 as an inserted layer to improve the leakage current and voltage dependence but sacrificing the overall κ value seems to be unavoidable. However, our TLAO dielectrics with Al2O3 doping presents only a slightly 3% capacitance degradation and provides a higher-κ value of 39.3, mainly ascribed to the mixed dielectrics giving rise to a larger dielectric polarization.

The analog characteristics are important for MIM devices, especially quadratic voltage coefficient of capacitance (VCC-α). The VCC-α can be obtained by fitting the measured C-V curve with a second order polynomial equation:

　C(V)=C0 (VCC-αV² + VCC-αV) (2) Here C0 is the capacitance at 0 V, VCC-α and VCC-α represent the quadratic and linear voltage coefficients of capacitance, respectively. Since the linear VCC-α term can be compensated by circuit design, the quadratic VCC-α is the main factor in the voltage dependence. As shown in Fig. 3-2(a), the VCC-α　value of 7130 ppm/V² at 100 kHz for the TLAO dielectric is much lower than that 17736 ppm/V² of TLO capacitor.

Since VCC-α can be largely improved with decreasing capacitance density [3.20], a reduced α is expected at the lower capacitance density. Therefore, the VCC results imply that the introduction of Al2O3 into TiO2-based dielectrics is favorable for lowering voltage nonlinearity caused by mobile charges in the dielectrics or interface. The mobile charges involved in the formation of the double layer was appealed to be free electrons that are

36

injected at electrodes or to be oxygen vacancies that are inherently created during oxide growth [3.21]

Furthermore, because the integrated circuit (IC) chips are usually operated at higher temperature due to power dissipation, the temperature coefficient of capacitance (TCC) is another important index to evaluate the MIM capacitors. Fig. 3-2(b) shows the TCC characteristic obtained from normalized capacitance of TLO and TLAO capacitors as a function of temperatures. Again, better TCC characteristic measured at 500 kHz for TLAO dielectrics is found. From the above results, the Al2O3 doping seemingly plays a major role in the voltage or temperature nonlinearity.

0.0 -0.5 -1.0 -1.5 -2.0 0.0

20.0k 40.0k 60.0k 80.0k 100.0k 120.0k 140.0k 160.0k 180.0k 200.0k

(a)

TLO MIM

@100 kHz, α = 17767 ppm/V² @500 kHz, α = 7518 ppm/V²

TLAO MIM

@100 kHz, α = 7130 ppm/V² @500 kHz, α = 6120 ppm/V²

ΔC/C

Voltage (V)

275 300 325 350 375 400

0.0 5.0x10⁴ 1.0x10⁵ 1.5x10⁵

(b)

TLO MIM, TCC= 1232 ppm/K TLAO MIM, TCC=850 ppm/K

Temperature (K)

Normalized capacitance

at 500 kHz

Fig. 3-2 (a) ΔC/C-V (b) TCC characteristics of TaN/[TLO and TLAO]/TaN MIM capacitors.

To gain insight into the voltage dependence in TLO and TLAO dielectrics further, a model based on electrode polarization mechanism, which has successfully fitted the experimental results of HfO2 MIM capacitors [3.22]-[3.23] was performed on this work.

The model can be expressed as

/ ) 1 1

( _{2n 2n}

m

C A

C +ω τ

+ ′

= (3) Where Cm is the capacitance in the absence of electrode polarization, C_m =ε₀ε_rA/t_ox, A is the area of top electrode, tox is the dielectric thickness and n is an exponent introduced for a

37

Jonscher response, which means the Debye response (ω²τ²) is substituted by Jonscher response (ω^{2n 2}τ ⁿ , with 0 < n < 1). The parameters of A′ and τ are equal to

D ox

L

A t ₂

) 2 (

2 ρ

= +

′ ,

D ox

L t τ ρ

τ = +

2 1

0 , where parameter ρ is the blocking parameter that account for the electrode transparency and L_D = εε₀k_BT/ Nq² is the Debye length, where N is the density of mobile charges. Finally, by approximating C ≈C_m[3.22], the relative variation of the capacitance can be expressed as

] 1 ) / [exp(

1 )

2 ( ) 1 ) (

(

2 2

2 0 ) 1 ( 2 2

1 2

0 0

− + ×

Δ =

−

− nqEs k T

L L C

C

B n

n n n

D

n σ

ω ρ

εε (4)

According to Equations (1) and (2), the ΔC/C0 should decreases with frequency (ω , ⁻²ⁿ 0 < n < 0.5) and increase with the leakage current (σ ) [3.22]. The capacitance at ₀²ⁿ

constant voltage as a function of frequency _⎥

⎦

⎢ ⎤

⎣

⎡ Δ f

C f C( ) ~ln ln

0

has been plotted in the Fig.

3-3(a). The two fitted slopes in Fig. 3-3(b) give the value of 2n, which is 0.27 and 0.13 for TLO and TLAO dielectrics, respectively. The ΔC/C0 can be well fitted with an exponential distribution, which give the exponential factor nqEs/k_BT , and the hopping distance (s) is calculated using the value of n. The density of defects can be estimated from N ≈1 s/ ³ [3.22].

38

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0

20 40 60 80 100 120 140 160 180

TLO MIM, N = 1.7 x10²⁰(cm^-3) TLAO MIM, N = 1.2 x10²⁰(cm^-3)

ΔC/C0 (*1000 )

Electric Field (MV cm^-1) Top injection, at 100kHz

Exponential Fitting

(a)

11.5 12.0 12.5 13.0 13.5

-2.6 -2.4 -2.2 -2.0 -1.8

(b) TLO MIM, 2n=0.27 TLAO MIM, 2n=0.13

Ln (ΔC(f)/C0), V fixed at -2V

Ln (Frequency) (Hz)

Fig. 3-3 (a) ΔC/C0-E and (b) ln(ΔC(f)/C0) versus ln(f) plots for MIM capacitors with TLO and TLAO dielectrics.

After calculating, the hopping distances of mobile charges are 1.8 and 2.1 nm in TLO and TLAO dielectrics, respectively and the defects density at the measured frequency of 100 kHz for TLAO dielectrics is lower than TLO case, suggesting that TLAO with deeper trap energy due to Al2O3 doping [3.24] increase relaxation time of mobile charges, which responsible for capacitance variation (ΔC/C0) and frequency dispersion and hence lower the voltage nonlinearity.

Subsequently, we examine the stress behavior and time-dependent dielectric breakdown (TDDB) lifetime for the TLO and TLAO samples. The VCC-α as a function of stress voltage under constant voltage stress (CVS) was performed and plotted in Fig. 3-4(a).

At a stress voltage of -3V, TLO dielectrics show a large VCC-α variation and a sudden rise occurs as the stress time continues to ~10⁴ sec, suggesting that excess mobile charges generated in TLO dielectrics during CVS cause the VCC-α degradation rapidly. Therefore, we can know that the additional Al2O3 doping not only lowers intrinsic VCC-α, but also increase the stability of voltage linearity during voltage stress. In Fig. 3-4(b), based on TDDB stress, the TLAO capacitors demonstrate the higher breakdown strength than TLO during negative constant voltage stress. Thus, a clear breakdown characteristic indicates TiO2-based dielectrics with Al2O3 doping show a distinct effect in improving TDDB

39

degradation.

10³ 10⁴

3000 4000 5000 6000 7000 8000 9000 10000 11000 12000

(a)

TLO MIM TLAO MIM

Quadratic VCC

Stress time (sec) at 500 kHz

CVS at -3V

-3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 10²

10³ 10⁴ 10⁵ 10⁶

(b)

TLO MIM, C= 24 fF/μm² TLAO MIM, C= 23.2 fF/μm²

tBD (sec)

Voltage (V)

Fig. 3-4 (a) Stress time dependence of VCC-α and (b) TDDB characteristics for TLO and TLAO MIM capacitors.

Table 3-1 A comparison of MIM capacitors with various high-κ dielectrics and high work-function top electrodes.

MIM Caps HfO2

[3.6]

Al2O3-HfO₂ [3.7]

TiTaO [3.10]

Al2O3/TiO2/ Al2O3 [3.14]

ZrO2/Al2O3/ ZrO2 [3.19]

TLAO

(this work) Top

Electrode Ta TaN Ir Pt TiN TaN

Bottom

Electrode TaN TaN TaN TaN TiN TaN Cap.

Density (fF/μm²)

13 12.8 23 18.3 21.6 23.2

J (A/cm²) 6×10^-7 (2V)

8×10^-9 (2V)

2×10^-6 (-1V) 2×10^-5 (-2V)

6.4×10^-9 (1V) 7×10^-8 (2V)

2×10^-6 (2V)

7×10^—7 (-1V)

value ~15 ~18 ~45 ~22 29.7 39.3

40

3.1.1 CONCLUSIONS

The TLAO devices show the advantages in improving the voltage- and temperature-dependence characteristics of MIM capacitors. Moreover, the stress induced degradation caused by voltage stress can be effectively suppressed by Al2O3 doping with both high ΔEC and deeper trap energy.

3.2 C-V and J-V Characteristics of MOS devices

The electrical measurements were conducted on the films in Metal - Insulator - Semiconductor (MIS) capacitors by sputtering TaN gate with the contact area of 100μm×100μm.

Fig. 3-5 shows the C-V curves of the high-κ LaAlO3 films on Si-capped Ge/Si substrate as functions of RTA temperature. Due to RTA 550°C can repair the defect and trap, so the C-V curve become beautiful but devices showed severe degradation in capacitance density, because the LaAlO3/ Si-capped Ge/Si interface become thick than devices after 450 ^◦C RTA and Vfb shift after 550 ^◦C RTA, these changes were related to interfacial layer formation. Fig. 3-6 shows the J-V curves of the high-κ LaAlO3 films on Si-capped Ge/Si substrate as a function of RTA temperature. The high leakage current density increases with the RTA temperature. The higher leakage current is suggested that there is serious oxidization near the LaAlO3/ Si-capped Ge/Si interface due to metal inter diffusion.

41

The static dielectric constant (κ) and the equivalent-oxide thickness (EOT) of LaAlO3

films can be determined by following equation:

d C_{OX =}

κε

(4.1)

ox o

C 3.9 A EOT ₌ ε

(4.2)

ε

d：the thickness of LaAlO3 films.

From the C-V curves, we get a large gate-capacitor about 1.79μF/cm² ,we get the EOT of LaAlO3 is around 1.6nm.Combining the EOT with a physical thickness of 5nm, the dielectric of this PVD LaAlO3 is about 12, which is a high value to overcome the more severe gate leakage current problem compared to MOSFETs.

And the effective oxide charge (Q_eff) includes fixed oxide charge (Q_f), oxide trap charge (Q_ot) and mobile ion (Q_m) can be determined by the following equation:

ox eff MS

FB

C

- Q

V = Φ

Where V_FB is the flat band voltage, Φ_msis the difference in work function between TaN

and p-type Si-capped Ge/Si. For p-type Si-capped Ge/Si, positive Q_effcauses the C-V curve to shift to more negative values of gate bias with respect to the ideal C-V curve, while negative Q_effcauses the C-V curve to shift to more positive gate voltage.

42

Fig. 3-5 C-V of TaN/LaAlO3/Si/Ge/Si n-MOS capacitors at 450 and 550^oC RTA.

-2.0 -1.5 -1.0 -0.5 0.0

10

10

10

10

10

10

10

10

10

LaAlO₃ 450⁰C RTA LaAlO₃ 550⁰C RTA

J (A/ c m

)

Voltage (V)

Fig. 3-6 J-V of TaN/LaAlO3/Si/Ge/Si n-MOS at 450 and 550^oC RTA.

-2 -1 0 1 2

0.0 0.5 1.0 1.5 2.0 2.5

LaAlO₃ on Si-capped Ge/Si

450⁰C RTA 550⁰C RTA

C (

F/c m

)

Voltage (V)

43

Chapter 4 Conclusions 4.1 Conclusions

The LaAlO3 (LAO) dielectric on a Si capping Ge/Si substrate (SGS) followed by a gate-first process with a thermal budget of 550^oC have been implemented. The obtained 1.5-nm-EOT n-MOS capacitor present a low leakage current and near ideal swepted C-V behavior. The good performance can be ascribed to the La2O3 with a doping of Al2O3. It is well known that the Al2O3 have a large band gap (8.9eV) and conduction band offset (2.8eV). Thus, the Al2O3 doping play a important role for lowering the leakage current from dielectric itself and interface defects between dielectric (LAO)/SGS.

The LAO with a Al2O3 doping, one of potential candidates for CMOS application, have been implemented in our study by using a gate-first process on SGS substrate. Also, the LAO SGS n-MOS with a good capacitance performance have been demonstrated.

In addition, we combined the good thermal-stability LAO with TiO2 as a higher-κ dielectric (TLAO) for DRAM application. The TLAO with a high-κ value of 39.3 exhibit a low leakage current and good analog characteristics (VCC, TCC).

We concluded that LAO with a Al2O3 doping play a role factor in these improved MOS and MIM devices.

44

4.2 Suggestions for Future Works

Base on the above results. Several works are worthy to do in the future and are recommended here.

1. The goal of low leakage current and low EOT：

We must by to reduce the defects and suppress the leakage current in LaAlO3 thin film Moreover , we should try to achieve the goal of the low EOT with the low leakage current.

2. To low leakage current and VCC of TLAO MIM by higher work-function metals (Ni, Ir or Pt).

3. To modify the Vfb and Vt of LAO MOS capacitor by using high work-function gates.

4. To use varied interfacial layer (SiO2 or GeO2) to improve the thermal stability on Ge substrate.

5. LAO MOSFET fabrication and related reliability investigation.

45

Reference Chaper1

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[1.2] J. H. Stathis, A. Vayshenker, P. R. Varekamp, E. Y. Wu, C. Montrose, J. McKenna, D. J. DiMaria, L. -K. Han, E. Cartier, R. A. Wachnik and B. P. Linder, “Breakdown measurements of ultra-thin SiO² at low voltage,” in IEDM Tech. Dig., 2000, pp.

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