In order to find the positions of oxide traps in the channel under the stress experimentally, the random trap profiling technique (RTP) has been proposed to characterize the distributions of random trap densities in the channel of a small dimensional bulk-trigate device. Trigate devices show better RDF variability but poorer reliability than the conventional planar devices. The HC stress and NBTI stress have been also conducted to study the mechanisms of random-traps-fluctuation (RTF) which induced the Vth aggravation for both trigate nMOS and pMOS devices. We conclude that NBTI stress dominates the degradation of trigate pMOS devices due to the surface roughness on the sidewall with reference to the HC stress on trigate nMOS devices. However, by taking good care of the sidewall process, the reliability of trigate devices might be improved. These results provide us a direction on a good control of the reliability for future 3D trigate devices.
Moreover, the variability of different Fin-height trigate devices with high and low series resistances are investigated in this thesis. Several salient features can be drawn: (1) For HC stress with low electric-field, since the corner effect plays a more important role in the degradation of trigate devices, an alternative approach is provided to alleviate the corner effect by increasing the S/D resistance of trigate devices to achieve an acceptable reliability.
(2) For nMOS devices, devices with shorter fin-height shows more serious Vth degradation after the HC stress than those with taller ones; on the contrary, for pMOS devices, devices
the fin-width.
These results provide us a good understanding of the random traps fluctuation (RTF) of trigate devices and a guideline to achieve a high performance and good reliability of bulk trigate CMOS devices beyond 28nm generation.
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