Base on the nMOSFET enhancement on (110) orientation substrate for ideal CMOS structure. Microwave technology activate the dopant and enhance tensile stress shift are effective for our nMOSFET. Recess source/drain structure and microwave enhance tensile strain method are obvious for gate length scaling down to 200nm.
Subthreshold swing show the interface state density for control sample is higher than the SiN deposition samples. And the DIBL is similar for all sample, it indicate the short channel characteristics would not be worse for microwave process and PECVD SiN deposition process. We extract the interface state density by charge pumping method, and the interface state density of SiN deposited samples is lower than control sample. It indicates hydrogen diffuse to the oxide and silicon interface to passivated dangling bonds at the PECVD deposition process.
Discussion of series resistance for recess source/drain and normal structure indicate that recess structure would not increase the resistance of source and drain region.
But hot carrier degradation is the most serious problem for recess structure. Hot electrons trap in the spacer induce large electron field to scattering the transport at device operation mode, and a large degradation for drive current as shown in the result of Fig.3-27.
Even through recess S/D structure with microwave enhance tensile stress technique improved the current-voltage characteristics, the recess S/D structure make
devices degrade easily. The device characteristics and reliability should be improved by fabrication processes. But from our result, microwave enhance tensile stress technique should be a feasible technique for improving nMOS performance.
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Fig. 1-1 The transistors count of CPU increases with year, and doubles every 2 years [1].
Fig. 1-2 Transistor size scale down for high speed and high density CPU [2].
Fig. 1-3 ITRS 2009 Process Integration Deviced and Structures Logic Potential Solution [3].
Fig. 1-4 Electron mobility decrease with gate length [4].
(a)
(b)
(c)
Fig.1-5 The conduction band valley in k space with and without biaxial tensile strain. (The energy band diagram of electron split for biaxial tensile strain.)
(a)
(b)
(c)
(d)
Fig.1-6 The valance band in k space with and without biaxial tensile strain.
Fig. 1-7 (a) Strain silicon technique to enhance electron mobility [8].
Fig. 1-7 (b) Raised source and drain to enhance hole mobility [9] .
(a)
(b) Fig. 1-8 Strain silicon and raise source/drain technique for nMOS and Pmos enhancement. [8-9]
Fig.1-9 The CMOS performance for strain enhancement structure [16].
Table.1-1 The stress types for FET enhancement on general <110>/(100) substrate [16].
Fig. 1-10 Channel direction on three type of orientation substrate [18] .
(a)
(b)
Fig.1-11 The carrier mobility for different channel direction on different orientation substrate [19-20].
Fig. 1-12 Two types of Hybrid-Orientation Technology (HOT) substrates [19-20].
Fig.1-13 Symmetrical current versus voltage characteristics for HOT substrates
Fig. 1-14 TEM cross section of FET with recess Source/Drain about 20nm. [22]
Fig. 1-15 The Ion − Ioff performance for NFET and PFET by recess S/D [22].
Fig. 1-16 The SIMS profile of boron that before and after (RTA or microwave) annealing [25].
Fig. 1-17 The stress shift by RTA anneal for difference composition of SiN [15].
Fig. 1-18 The model of stress shift after thermal annealing [15].
Intrinsic MW. annealed 0
200 400 600 800 1000 1200 1400
Stress (MPa)