Chapter 1 Introduction 1.1 Motivation
The allowance of the FCC regarding frequencies between 3GHz and 10GHz for Ultra-Wideband (UWB) applications has led to an increased level of interest and scope of research on this band and its various applications. The availability of such high bandwidth would allow higher data throughput up to 500Mbps in possible short distance, which is desirable for HDTV and other wireless multimedia applications.
Apart from higher data rates, the other main features of UWB are lower cost and higher level of integrations. Several different approaches were proposed to establish a universal standard for this application [5].
LNA is the first stage in the receiver, after antenna in the receiver block of a communication system. It is widely used in the front-end of narrow band communication system. For UWB application, the criteria to judge its performances are slightly different. Whereas in narrowband systems there is tight requirement on linearity, this parameter is relaxed in UWB wireless systems, which ranges from 3.1GHz to 10.6GHz, because transmitted power spreads over a wide range and is restricted to be less than -41.3dBm per MHz, The most important requirement for UWB applications are input impedance match, low power consumption, low noise
performance, enough gain to suppress noise of the next stages and small size.
For the overwhelming majority DSP chips, most designer introduces the CMOS process to achieve system on chip (SOC). But for analog and radio frequency chips, due to the electricity, noise and other parameters have strict demands. In order to achieve the specification of the products, different communication systems have different demands in process. In the past, due to GaAs process has excellent high frequency parameters, so most designer introduces the GaAs process to design theirs products. But the deep sub-micro CMOS process has acceptable high frequency parameters. Recently there are designers introduce 0.18 micrometer, 0.13 micrometer or 0.09 micrometer CMOS process to design radio frequency transceivers. Because CMOS process’s cost is less expensive than other process’s. And that radio frequency transceiver introduces CMOS process is facile integration with base-band circuit.
Achieving perfection of the SOC is feasible in future.
In the second section, we will analyze the noise effect and the nonlinear effect in the ratio frequency integrated circuit design. In the section three, a cascode R-C feedback structure will be introduced. Then, the forth section, is another structure, a low power current-reused LNA. It consumes very low power, in the LNA core only 7mW. It also has good input matching and high gain. Finally, in the section five, we will summarize a conclusion to our study.
Chapter 2
Noise and Nonlinear effect in RF Design 2.1 Noise
Noise is usually generated by the random motions of charges or charge carriers in devices and materials. Because the noise process is random, one cannot identify a specific value of voltage at a particular time, and the only recourse is to characterize the noise with statistical measures, such as the mean-square or root-mean-square values. Because of having various noise sources in the circuit, we need to simplify calculation of the total noise at the output [2]. Obviously, the output-referred noise does not allow a fair comparison of the performance of different circuits because it depends on the gain. According the circuit theory, we can use the input-referred noise of circuits to represent the noise of behavior in the circuits. To overcome the above confusion, we specify the “input-referred noise” of circuits. Illustrate conceptually in Fig. 2-1. To represent the effect of all noise sources in the circuit by a single noise source. The input-referred noise and the input signal are both multiplied by the gain as they are processed by the circuit. Thus, the input-referred noise indicates how much the input signal is corrupted by the circuit’s noise. The input-referred noise is a spurious quantity in that in cannot be measured at the input of the circuit. The two circuits of Figs. 2-1(a) and (b) are equivalent in mathematics but the real physical
circuit is still that in Fig. 2-1(b). The noise of a two-port network can be modeled by two input noise sources: a series voltage source and a parallel current source.
Generally, the correlation between the two sources must be taken into account.
The situation is shown in Fig. 2-2, where a two-port network containing noise sources is represented by the same network with internal noise sources removed and with a noise voltage and current source connected at the input. It can be shown that this representation is valid for any source impedance, provided that correlation between the two noise sources is considered [3].
The signal-to-noise ratio (SNR), defined as the ratio of the signal power to the total noise power, is an important parameter. In RF circuit, most of the front-end receiver blocks are characterized in terms of their “noise figure” rather than the input-referred noise. Noise figure has many different definitions. The most commonly accepted definition is
noise figure
out in
SNR
= SNR , (1)
Noise figure is a measure of how much the SNR degrades as the signal passes through a circuit. If a circuit has no noise source, the SNRout = SNRin, regardless of the gain.
The noise figure of a two-port amplifier is given by s opt
s
n y y
g F r
F = min + − (2)
where rn = Rn / Z0 is the equivalent normalized noise resistance of the two-port,
ys = Rn / Z0 = gs + jbs represents the normalized source admittance, and yop t = gopt+ jbopt represents the normalized source admittance which results in the
minimum noise figure, called Fmin.
If we express ys and yopt in terms of the reflection coefficients Гs and Гopt.
Substitute (3) and (4) into (2) results in the relation
2 2 bias current and operating frequency [4].
For a cascade of stages, the overall noise figure can be obtained in terms of the
where Apm is the available power gain of the m-th stage. This is called the Friis equation. The Friis equation indicates that the noise contributed by each stage decreases as the gain preceding the stage increases, implying that the first few stages in a cascade are the most critical [1].
(a)
(b)
Fig. 2-1 Determination of input-referred noise voltage.
(a)
(b)
Fig. 2-2 Representation of noise in a two-port network by equivalent input voltage and current sources.
2.2 Nonlinear effect
While many RF circuits can be approximated with a linear model to obtain their response to small signals, nonlinearities often lead to interesting and important phenomena. For simplicity, we assume that
y ( t ) ≈ α
1x ( t ) + α
2x
2( t ) + α
3x
3( t )
(7) If a sinusoid is applied to a nonlinear system, the output generally exhibits frequency components that are integer multiples of the input frequency.Ifx
(
t) =
Acos ω
t, thenIn Eq. (9), then term with the input frequency is called the “fundamental” and the higher-order terms the “harmonics.” The amplitude of the nth harmonic consists of a term proportional to An.
decreasing function of A. In most circuits, the output is a “compressive” or
“saturating” function of the input; that is, the gain approached zero for sufficiently high input levels. This effect is quantified by the “1-dB compression point,” defined as the input signal level that causes the small-signal gain to drop by 1 dB. If plotted on a log-log scale as a function of the input level, the output level falls below its ideal
value by 1 dB at the 1-dB compression point.
When two signals with different frequencies are applied to a nonlinear system, the output in general exhibits some components that are not harmonics of the input frequencies. Called intermodulation (IM), this phenomenon arises from multiplication of the two signals when their sum is raised to a power greater than unity. We assume that
Expanding the left side and discarding DC terms and harmonics, we obtain the intermodulation products: test, A1=A2=A, and the ratio of the amplitude of the output third-order products to α
1A defines the IM distortion. If a weak signal accompanied by two strong interferers experiences third-order nonlinearity, then one of the IM products falls in the band of
interest, corrupting the desired component.
Use IP3 to characterize this behavior. Called the “third intercept point” (IP3), this parameter is measured by a two-tone test in which A is chosen to be sufficiently small so that higher-order nonlinear terms are negligible and the gain is relatively constant and equal to α1. The third-order intercept point is defined to be at the intersection of the two lines [1].
(a)
(b)
(c)
Fig. 2-3 (a) Definition of the 1-dB compression point, (b) Corruption of a signal due to intermodulation, (c) The third-order intercept point.
2.3 Cascaded Nonlinear Stages
Since in RF systems, signals are processed by cascaded stages, it is important to know how the nonlinearity of each stage is referred to the input of the cascade.
Consider two nonlinear stages in cascade. As shown in Fig.2-4. Assuming that the input-output relationship is
y1(t)=α1x(t)+α2x2(t)+α3x3(t) (14) y2(t)=β1y1(t)+β2y12(t)+β3y13(t) (15) Substitute (14) into (15) results in the relation
y2(t)=α1β1x(t)+(α3β1+2α1α2β2+α13β3)x3(t) (16) If we consider only the first- and third-order terms, then
From equation (17) can be simplified if the two sides are inverted and squared:
where AIP3,1 and AIP3,2 represent the input IP3 points of the first and second stages, respectively. From the above result, we note that as α increases, the overall IP1 3
decreases. This is because with higher gain in the first stage, the second stage senses larger input levels, thereby producing much greater IM3 products [1].
Fig. 2-4 Cascaded nonlinear stages.
Chapter 3
Design of UWB LNA with cascode feedback structure 3.1 Circuit topology
In designing a broadband amplifier, feedback and distributed configuration are most widely used. In the chapter, feedback configuration was used instead of distributed configuration because it is more adequate for integration due to better uniformity and stability at frequencies below 12GHz. In addition, the cascode structure has been considered as the best topology for wideband applications because of its advantages [11].
We design UWB LNA with cascode R-C feedback structure. There are two types in this structure. The feedback1 structure is the R-C feedback connected between Lg and MOS1’s gate, like Fig. 3-1(a). The feedback2 structure is the R-C feedback connected between input and Lg, like Fig. 3-1(b).
From Fig. 3-1 (a) and (b), we can observe that they are two stage low noise amplifier. First stage used the cascode R-C feedback structure. The advantages of cascode structure are high gain, wider bandwidth, better stability and reverse isolation.
The cascode configuration is being used to reduce the high frequency roll-off of the input devices due to the Miller effect [11]. It can also be performed the input/output matching independently. The R-C feedback (Rf & Cf) in cascode circuit improves the
S11 of the circuit and stabilizes the common-gate without reducing the gain. Above all, it can satisfy the requirements of wideband system for both noise and power simultaneously by carefully feedback resistance.
The MOS M1 dominates the noise performance. These two MOS (M1 and M2) have little effects with each other.
The two LNA (feedback1 and feedback2) for UWB applications were designed using TSMC 0.18um RF CMOS technology.
(a)
(b)
Fig. 3-1 Proposed UWB LNA schematic (a) feedback1, (b) feedback2.
3.2 Design procedures
3.2.1 Transistor sizing and bias condition
Since the size of transistor and bias condition determine the power dissipation, it is often recommended to decide them with a certain power budget. However, we should evaluate the size of the transistor versus bias condition carefully, because they are also related to the impedance seen by the input gate. Thus, the first choice is to determine the size and bias condition that satisfies both impedance and noise matching with limited bias current.
Fig. 3-2(a) shows a simulation circuit of MOS NFmin. In Fig. 3-2(a), the input transistor M1 (W/L = 160/0.18 um) is chose and is biased at 7.5mA. In Fig. 3-1(a) and (b), the size of the cascode transistor M2 (W/L = 64/0.18 um) is decided considering a trade-off between gain (S21) and -3dB bandwidth. The size of the second stage transistor M3 is W/L = 64/0.18 um. The total power consumption is 18.8mW.
Fig. 3-2(b) shows the Vgs versus NFmin at 3.1GHz, 6.85GHz and 10.6GHz.
From Fig. 3-2(b), we can observe that when Vgs = 0.7V, the transistor M1 has the minimum noise figure. Thus, the bias condition is decided to Vgs = 0.7V.
(a)
(b)
Fig. 3-2 (a) Simulation circuit of MOS NFmin, (b) Vgs v.s. NFmin at 3.1GHz、
6.85GHz and 10.6GHz.
3.2.2 Noise analysis
The noise performance of the R-C cascode feedback topology is determined by three main contributors: the feedback resistor Rf, the gate inductor Lg and the noise of the amplifying device M1. The optimization of the noise contribution from M1 relies on the choice of its width for a given bias current.
MOS transistor noise sources are shown in Fig. 3-3(a). The noise generator i2d The input-referred in a conventional way and replaced with two correlated noise
generators, as shown in Fig. 3-3(b), because the current gain of the source degeneration is
Fig. 3-4(a) and (b) show the equivalent circuit of the input stage for noise calculation.
In Fig. 3-4(a), the feedback1 topology: Thus, the total equivalent noise voltage and current of feedback1 is
21 2 2 2 2 2 2 In Fig. 3-4(b), the feedback2 topology:
vib2 =via +iia⋅RLg +vLg (29) iib2 =iia (30)
Then,
vi2 =vib2 =via +iia ⋅RLg +vLg (31) ii2 =iib2 +if =iia +if (32) Thus, the total equivalent noise voltage and current of feedback2 is
2 2 2 2 2 2
R f The noise factor is
R f
From equation (27) and (33), we can observe that the total noise of feedback1 is greater than feedback2 due to the i2f
⋅
RLg2 item. Fig. 3-5 shows the noise figure:feedback1 versus feedback2. We can observe that the noise figure of feedback2 topology is better than feedback1.
(a)
(b)
Fig. 3-3 Noise model for the amplifying transistor M1 (a) M1 noise sources, (b) Input-referred equivalent noise generators.
(a)
(b)
Fig. 3-4 Equivalent circuit of the input stage for noise calculation (a) feedback1, (b) feedback2.
0 2 4 6 8 10 12 14 16 2
3 4 5 6 7 8 9 10
Noise Figure (dB)
Frequency (GHz)
feedback1 feedback2
Fig. 3-5 Noise figure: feedback1 v.s. feedback2.
3.2.3 Input and output match
Input matching:
In feedback1 topology, the small signal equivalent is shown in Fig. 3-6(a), where
1 For this configuration, the input impedance and the gain can be calculated to be
1
And in feedback2 topology, the small signal equivalent is shown in Fig. 3-6(b), where the input impedance and the gain can be calculated to be
1
f L
L f eff m L
V Z Z
Z Z g A Z
−
⋅
⋅
= + ,
2 (48) Since the circuit parameters Z ' and in A are frequency dependant, the V characteristics of Z will vary accordingly over the frequency band. Thus, select f
Z and combination of R、C components，perfect matching and gain can be f
achieved.
Output matching:
The second stage is decided to use L-C section for output match.
(a)
(b)
Fig. 3-6 (a) Feedback1 configuration, (b) Feedback2 configuration.
3.2.4 Shunt peaking
A model of shunt peaking amplifier is shown in Fig. 3-7(a). The capacitance C may be taken to represent all the loading on the output node, including that of a subsequent stage. The resistance R is the effective load resistance at that node and the inductor provides the bandwidth enhancement. It’s clear from the model that the transfer function
in outi
v is just the impedance of the RLC network, so it should be
straightforward to analyze. The addition of an inductance in series with the load resistor provides an impedance component that increases with frequency, which helps offset the decreasing impedance of the capacitance, leaving net impedance that remains roughly constant over a broader frequency range than that of the original RC network. The impedance of the RLC network may be written as
( )
to place the zero frequency (d The shunt peaking is shown in Fig. 3-7(b).
(a)
Fig. 3-7 (a) Model of shunt-peaked amplifier, (b) Gain compare with shunt-peaking.
3.3 Simulation and Measurement Result
Fig. 3-8 shows the s-parameters of simulation and measurement in feedback1 and feedback2. Fig. 3-9 shows the noise figure and Fig. 3-10 shows the linearity. Fig.
3-11 is the die photo.
In feedback1, the forward gain (S21) is less than simulation about 5dB due to the L1 without connecting bypass capacitors and process variation. When measured, the Vg1 dc probe without bypass capacitors may cause signal loss and have parasitical effects so that the gain is less than simulation. And, the ripple in 3 to 6GHz is due to the M2’s gate bypass capacitor layout which cause parasitic inductor and capacitor resonated in 3 to 6GHz. The reverse isolation (S12) is below -32 dB. The magnitude of S11 is below -7.5dB and S22 is below -10dB in entire operation frequency band. The S12, S11 and S22 are very close to the simulation result. The average noise figure is about 8dB and the minimum noise figure is 6.7dB at 5GHz. The IIP3 is 2dBm at 5.5GHz. The total power consumption is about 18mW with a power supply of 1.8 volts. And the die area including the pads is 0.77 mm2.
In feedback2, the forward gain (S21) is less than simulation about 2dB due to the L1 without connecting bypass capacitors. The reason is the same with feedback1. And, the ripple in 3 to 6GHz is also the same, because their basic structure and layout are slightly different. The reverse isolation (S12) is below -45 dB. The magnitude of S11 is
below -7.2dB and S22 is below -8.2dB in entire operation frequency band. The S12, S11
and S22 are very close to the simulation result. The noise figure is very flat about 5.5dB and the minimum noise figure is 4.55dB at 9GHz. The IIP3 is -2dBm at 5.5GHz. The total power consumption is about 18mW with a power supply of 1.8 volts. And the die area including the pads is 0.77 mm2.
From feedback1 and feedback2 structure, we can observe that the noise figure in feedback2 is better than feedback1 and the gain is also better. By the feedback2 structure, a low power, low noise amplifier can be achieved.
3.1~10.6 (GHz)
Gain (dB)
NF (dB)
S11
(dB)
S22
(dB)
IIP3 (dBm)
Pdc (mW)
Feedback1 5 8 <-7.5 <-10 2 18 Feedback2 9 5.5 <-7.2 <-8.2 -2 18
Table 3.1 Measurement results summary.
0 2 4 6 8 10 12 14 16 -15
-10 -5 0 5 10 15 20
S21 (dB)
Frequency (GHz)
simulation measurement
feedback1
0 2 4 6 8 10 12 14 16
0 5 10 15 20
S21 (dB)
Frequency (GHz)
simulation measurement
feedback2
(a)
0 2 4 6 8 10 12 14 16 -80
-60 -40 -20 0
S12 (dB)
Frequency (GHz)
simulation measurement
feedback1
0 2 4 6 8 10 12 14 16
-80 -60 -40 -20 0
S12 (dB)
Frequency (GHz)
simulation measurement
feedback2
(b)
0 2 4 6 8 10 12 14 16
0 2 4 6 8 10 12 14 16 -20
-15 -10 -5 0 5
S22 (dB)
Frequency (GHz)
simulation measurement
feedback1
0 2 4 6 8 10 12 14 16
-20 -15 -10 -5 0
S22 (dB)
Frequency (GHz)
simulation measurement
feedback2
(d)
Fig. 3-8 S-parameters of feedback1 and feedback2 (a) S21, (b) S12, (c) S11, (d) S22.
0 2 4 6 8 10 12 14 16 0
5 10 15 20 25 30
Noise Figure (dB)
Frequency (GHz)
simulation measurement
feedback1
0 2 4 6 8 10 12 14 16
0 5 10 15 20
Noise Figure (dB)
Frequency (GHz)
simulation measurement
feedback2
Fig. 3-9 Noise figure of feedback1 and feedback2.
-35 -30 -25 -20 -15 -10 -5 0 5
Fig. 3-10 Linearity of feedback1 and feedback2.
(a)
(b)
Fig. 3-11 Die photo (a) feedback1, (b) feedback2.
Chapter 4
Design of a low power UWB LNA with current-reused structure
4.1 Circuit topology
Fig. 4-1 shows the proposed current-reused high gain two stage amplifier topology. In Fig. 4-1, R 、d1 L and d1 L are the loads for each common-source d2 amplifier, Cg2 is the coupling capacitor, Cbypass is the bypass capacitor, and Rbias is the bias resistor. The proposed amplifier is the current-reused cascaded common-source amplifier with capacitive inter-stage coupling except the extra inductorL . In Fig. 4-1, the value of g2 L is adjusted for the series resonance with g2 the input capacitance of the second stage. Accordingly, the first stage is designed to resonate at the lower bound of the frequency band. The second stage, on the other hand, resonates at the higher bound of the frequency band.
To achieve the goal of power saving, the second stage is stacked on top of the first stage. A coupling capacitor and a bypass capacitor are required for this topology.
The capacitor Cg2 provides signal coupling between the two stages and the capacitor Cbypass functions as an ac ground at the source of transistor M2. The capacitance of capacitor Cbypass is chosen to be as large as possible to provide ideal ac ground in conventional narrow band designs as well.
Fig. 4-1 Proposed UWB LNA schematic.
4.2 Design procedures
4.2.1 Transistor sizing and bias condition
Since the size of transistor and bias condition determine the power dissipation, it is often recommended to decide them with a certain power budget. However, we should evaluate the size of the transistor versus bias condition carefully, because they are also related to the impedance seen by the input gate. Thus, the first choice is to determine the size and bias condition that satisfies both impedance and noise matching with limited bias current.
Fig. 4-2(a) shows a simulation circuit of MOS NFmin. In Fig. 4-2(a), the input transistor M1 (W/L = 78/0.18 um) is chose and is biased at 3.89mA. In Fig. 4-1, the
Fig. 4-2(a) shows a simulation circuit of MOS NFmin. In Fig. 4-2(a), the input transistor M1 (W/L = 78/0.18 um) is chose and is biased at 3.89mA. In Fig. 4-1, the