Summary

We have characterized the programmed charge lateral distribution in a two-bit storage nitride flash cell by channel hot electron program. The charge pumping measurement reveals that the charge distribution of each bit extends into the channel for tens of nanometers. This suggests the possibility of further scaling down the nitride flash cell with respect to the concern of the overlap of two bit charges. Our study also shows that the charge distribution of the secondly programmed bit is influenced by the stored charge of the first bit. A broader second bit charge distribution is obtained.

Fig. 3.1 (a) Schematic diagram of a two-bit storage nitride flash cell and (b) charge pumping measurement waveform. The dashed line in the substrate represents the depletion region caused by Vd. The thickness of the ONO gate stack is 9nm (top oxide), 6nm and 6nm, respectively.

Vd Vg

V gh

V gl

0

(b)

P-substrate

oxide oxide nitride

n

⁺

n

⁺

floating V ^d

I

_B

= I ^cp V ^g

P-substrate

oxide oxide nitride

n

⁺

n

⁺

floating V ^d

I

_B

= I ^cp V ^g

(a)

Fig. 3.2 The dependence of normalized charge pumping current (Icp/f) on measurement frequency. In charge pumping measurement, the Vt window (∆Vt) is 2.7V and Icp is measured at V^gl=2.5V.

1.0 1.5 2.0 2.5

1.00 1.25 1.50 1.75

Frequency (MHz)

Icp/f (1 0 -1 7 C) Prog. state

∆V ^t =2.7V

Fig. 3.3 Icp versus Vgl in a fresh cell, in program-state and in erase state, respectively. The Vt window (∆Vt) is 2V. Vd in CP measurement is 0V.

-2 0 2 4

1p 10p 100p

fresh

Prog. state Erase state

Vgl(Volts)

Icp(A m p)

Vgl(Volts)

Icp(A m p) nitride charge

trapping

∆V ^t =2V

Fig. 3.4 Icp versus Vgl for different Vt window. The program-state Icp bump increases with Vt window due to more injected charges.

-2 0 2 4

1p 10p 100p

Erase

Prog. state

∆V ^t =2.7V

∆V ^t =2V

V ^gl (Volts)

I cp (A m p )

-2 0 2 4

1p 10p 100p

Erase

Prog. state

∆V ^t =2.7V

∆V ^t =2V

-2 0 2 4

1p 10p 100p

Erase

Prog. state

∆V ^t =2.7V

∆V ^t =2V

V ^gl (Volts)

I cp (A m p )

Fig. 3.5 Icp versus Vgl with different Vd in CP measurement. The program-state

Fig. 3.6 The program state Icp measured at V^d=1.8V & V^s floating and at V^s=1.8V and V^d floating.

-2 0 2 4

1p 10p 100p

Vs Vd

1.8V floating floating

1.8V

∆ V _t =2V Erase

Vgl (Volts)

Icp(A mp)

Vgl (Volts)

Icp(A mp) Prog. state

Fig. 3.7 The Icp versus Vgl of the four states of two-bit storage. “11” represents both bits in erase-state and “10” represents one bit in erase-state and one bit in program-state.

-2 0 2 4

1p 10p 100p

"00"

"01"&"10"

"11"

V ^gl (Volts)

I cp (A m p )

∆V ^t =2V

Fig. 3.8 Comparison of the Icp versus Vgl of the first programmed bit and the secondly programmed bit. The 2nd bit Icp is measured with the first bit erased.

Fig. 3.9 Comparison of the second bit Icp-Vgl from two approaches. One is to measure Icp after the first bit is erased. The second approach is to subtract the fist bit Icp from the “00” state Icp.

-2 0 2 4

1p 10p 100p

1st bit erased

Vgl (Volts)

Icp (A m p)

Erase

subtraction

from “00” state

-2 0 2 4

1p 10p 100p

1st bit erased

Vgl (Volts)

Icp (A m p)

Vgl (Volts)

Icp (A m p)

Erase

subtraction

from “00” state

Fig. 3.10 Lateral profiling of the programmed charge distribution of the first programmed bit and the secondly programmed bit. A uniform interface trap distribution along the channel is assumed. Icp,max in Eq. (3-1) is 195pA.

0.00 0.01 0.02 0.03 0.04 0.0

5.0x10

¹²

1.0x10

¹³

1st prog. bit 2nd prog. bit

“cross-over”

Q N /q (c m -2 )

Distance (µm)

0.00 0.01 0.02 0.03 0.04 0.0

5.0x10

¹²

1.0x10

¹³

1st prog. bit 2nd prog. bit

“cross-over”

0.00 0.01 0.02 0.03 0.04 0.0

5.0x10

¹²

1.0x10

¹³

1st prog. bit 2nd prog. bit

“cross-over”

Q N /q (c m -2 )

Distance (µm)

Fig. 3.11 Simulated channel field distribution in 2nd bit programming from 2D device simulation. x=0 is at the n⁺ source edge and x=0.4 is at the n+

drain edge. Vs=6.5V and Vg=11 in 2nd bit programming.

0.0 0.1 0.2 0.3 0.4 0.0

2.0x10

⁵

4.0x10

⁵

6.0x10

⁵

Distance (µm)

C h an n el f iel d (V /cm )

due to 1st bit charge

Fig. 3.12 The difference in Icp between program-state and erase-state as a function of drain bias for the 1st bit and source bias for the 2nd bit. The

∆cp is obtained from Fig. 3.7 and Fig. 3.8 at Vgl=1.6V.

0.0 0.5 1.0 1.5 2.0 0.0

5.0p 10.0p 15.0p 20.0p

1st prog.bit 2nd prog. bit

∆ Icp (A m p )

Applied junction bias (Volts) ^{0.0 0.5 1.0 1.5 2.0}

0.0 5.0p 10.0p 15.0p 20.0p

1st prog.bit 2nd prog. bit

∆ Icp (A m p )

Applied junction bias (Volts)

Fig. 3.13 The difference in Icp between program state and erase state as a function of V^d in CP measurement at various P/E cycle numbers. ∆Icp is measured at Vgl=1.6V and is normalized to its value at Vd=0V to take into account interface trap creation in cycling.

0.0 0.5 1.0 1.5 2.0

0.0 0.5

1.0 fresh

50 P/E 1K P/E 50K P/E

V d (Volts)

Nor m al iz ed ∆ Icp (Am p)

Fig. 3.14 Threshold voltage versus reverse read Vd for different cycle numbers.

0.0 0.4 0.8 1.2 1.6

1 2 3 4

5 fresh

50 P/E 1K P/E 50K P/E

V ^d (Volts)

Threshold voltage (V)

0.0 0.4 0.8 1.2 1.6

1 2 3 4

5 fresh

50 P/E 1K P/E 50K P/E

V ^d (Volts)

Threshold voltage (V)

Chapter 4

Reliability Mechanisms of Data Retention and Read-Disturb in Nbit Flash Memory Cells

4.1 Introduction

The major advantages of the Nbit cell, as compared with the conventional SONOS flash EEPROM, has a better retentivity due to a thick bottom oxide thickness [4.1]. The bottom oxide in the Nbit cell is normally thicker than 40Å. Such oxide is sufficiently thick to avoid charge direct tunneling [4.2]. The Nbit cell exhibits no window loss before P/E cycling. However, after P/E cycled stress, the retentivity behavior is degraded, showing a window closure with time (Fig. 4.1). As previously stated, the retention loss characteristics are determined by two factors. (a) oxide charge (Qox) de-trapping in erase state [4.3], strongly dependent on P/E stress and oxide quality [4.4], and (b) nitride charge (QN) loss in program state [4.5], closely related to temperature and electric field.

In this chapter, the reliability issues of the Nbit flash cell including low-Vt state threshold voltage instability (room temperature threshold voltage drift, RT drift), read-disturb, and high-Vt state charge loss will be reviewed. Responsible mechanisms and possible solution will be discussed.

4.2 Room-Temperature Threshold Voltage Drift

In a P/E stressed cell, the erase-state threshold is found to possess a positive drift with storage time (Fig. 4.1). This retention loss exhibits logarithmic

time-dependence but weak temperature dependence (Fig. 4.2). This is why the drift is referred to as RT drift [4.6]. Unlike a SONOS cell, the bottom oxide is sufficiently thick and thus this drift cannot be explained by nitride hole back tunneling [4.7].

Furthermore, we find that the Vt drift exhibits a peak around 10k P/E cycles in Fig.

4.3. To understand this peculiar cycle number dependence, the readers should be reminded that it is well published in literature that positive trapped charge creation is dominant in tunnel oxide in the initial period of P/E stress [4.8]. The appearance of the peak gives a clue that the Vt drift is related to positive charge creation in the bottom oxide. To explore the origin of the RT drift, Vt and GIDL techniques are used to monitor the charge, as shown in Fig.4.4 (a) and Fig.4.4 (b). From the change of Vt and GIDL, it can be deduced that after P/E stress the net ONO charge above the n⁺ region is positive and the net ONO charge above the channel region is negative.

More exactly speaking, the ONO charge in the channel region comprises positive oxide charge (Qox) and negative nitride charge (QN). In storage, trapped holes in the bottom oxide (Qox) can escape to the Si substrate with time. The total ONO charge in the channel region therefore becomes more negative and thus threshold voltage increases with time. To measure positive oxide charge de-trapping directly, the charge separation technique (Fig. 4.5(a)) is employed in large area devices with two different ONO processes (A and B). Process B is known to have a thinner bottom oxide, thereby causing a smaller Qox. The substrate current (Ib) before and after FN stress was measured in these two samples, as shown in Fig. 4.5(b). According to the hole tunneling front model [4.9], the post-stress substrate current resulting from positive oxide charge de-trapping follows a 1/t time-dependence,

1

where Q^ox is the positive oxide charge density, φ^ox denotes the energy barrier of positive trapped charges and A is the area of the device. Note that process B exhibits a smaller post-stress substrate current because of less positive oxide charge creation.

The corresponding Vt drift thus has a logarithmic time-dependence,

)

Fig. 4.6 shows the measured Vt drift in two 10k P/E cycled cells. By comparing the two ONO processes, a correlation between the Vt drift and Ib is obtained. Fig. 4.7 shows the RT drift versus bottom oxide thickness and demonstrates that an effective approach to reducing Qox is to use a thinner oxide. In addition, we can vary the erase time of the last-shot to study the dependence of the RT drift on QN. For a prolonged erase time, QN is less and the RT drift is smaller, as shown in Fig. 4.8.

4.3 Read-Disturb Effects in Erase State

Read-disturb effect is twofold in the NROM. The word-line voltage during read may enhance the RT drift in the neighboring bit. On the other side, the relatively large read bit-line voltage may cause channel hot electron injection and result in a significant threshold voltage shift of the neighboring bit. The hot electron injection caused Vt shift follows either power-law time-dependence or logarithmic

time-dependence. An analytical model based on positive oxide charge assisted channel hot electron injection is proposed to explain the observed power law time-dependence.

4.3.1 Commonality between Vt Drift and Read-Disturb

The RT drift and read-disturb have something in common. For example, the read-disturb caused Vt shift is also smaller when the bottom oxide thickness is reduced (Fig. 4.9). Secondly, we performed RT drift measurement and the read-disturb measurement in the same device (10k P/E cycles) sequentially. No matter the RT drift or the read-disturb is measured first, the subsequent read-disturb or RTdrift is significantly reduced (Fig. 4.10). Fig. 4.10 gives strong evidence that the mechanisms of RT drift and read-disturb should share the same physical origin.

From the study in the preceding section, we believe that read-disturb is also related to positive trapped charge in the bottom oxide.

4.3.2 Gate and Drain Bias Dependences on Read-Disturb Behavior

At read Vg, the channel is inverted and another current component flowing from the gate to the source and the drain (Isd) arises due to positive oxide charge assisted electron tunneling (Fig. 4.11). When Vg is large, Isd becomes dominant (Fig.

4.12). Our previous work has shown that Isd has a t^-n time-dependence with n~0.7 [4.10]. The gate-disturb induced ∆Vt∝∫I^sd(t)dt should follow a power law time dependence with the power factor of 1-n~0.3. The gate-disturb effect and the RT Vt drift are compared in Fig. 4.13.

Moreover, since the bit-line voltage in reverse read must be sufficiently large to

overcome the stored charge of the second bit, hot electron injection during read should be considered. The hot electron read disturb is worsened in a P/E cycled cell because of positive oxide charge enhanced electron injection. Fig. 4.14 shows the Vt shift versus read bit-line voltage in a fresh device and in a 10k P/E cycled Nbit cell.

The read disturb increases drastically as the read voltage is above 2V.

4.4 Program state Charge Loss

The most advantage of trapping storage cells, as compared to floating gate flash cells, is the better charge retentivity. Fig. 4.15 and Fig. 4.16 show that high-Vt state charge loss has temperature, cycle number and gate bias dependence, respectively.

These observations suggest that the nitride charge escape is through thermionic-field emission and subsequently oxide trap assisted tunneling was proposed (Fig. 4.17). To characterize nitride charge escape current, a large area device was stressed at –Vg

(FN stress) and then was programmed to a high-Vt state by uniform FN injection.

Trapped charge lateral migration in this case is excluded due to the uniform charge injection [4.11]. According to the FP emission model, the nitride trapped charge emission time is written below,

)

where A* is the Richardson constant, φN is the nitride trap energy, EN is the electric field in nitride and other variables have their usual definition. The nitride charge emission current and the corresponding Vt shift can be derived as follows [4.1],

t

where QN(cm^-2eV^-1) represents trapped charges in nitride. In the above derivation, we make the following assumptions. First, we assume that at measurement time t all nitride traps with time constants less than t are completely emptied and all other traps are unaffected. Secondly, we assume that nitride trapped charge escape is limited by the FP emission. Third, we assume that emitted nitride charges in the measurement interval from 1sec. to 100 sec. (Fig. 4.18) have a uniform distribution in trap energy, i.e., QN is a constant. This assumption is also reasonable since the trap energy span in the measurement period is only about kTln(100)~0.12eV. For a constant energy distribution of nitride-trapped charges, the nitride charge emission current obeys a 1/t relationship (Eq. (4-5) & Fig. 4.18) and the Vt loss is proportional to the square root of the electric field (Eq. (4-6) & Fig. 4.19).

4.5 Summary

In a low-Vt state, P/E stress created positive oxide charge plays a major role in various reliability issues. ONO process condition is critical to the improvement of the cell reliability. High-Vt state charge retention mechanism, FP excitation followed by oxide-trap assisted tunneling, is investigated. In next chapter, a detail numerical analysis for the program state charge loss is described.

Fig. 4.1 Typical Vt retention characteristics in a fresh and a 100k P/E cycled cell.

Fig. 4.2 Temperature-dependence of the erase-state Vt drift in a 10k P/E cycled cell at 10⁴s. No significant change in Vt drift by varying temperature.

10¹ 10² 10³ 10⁴

0 1 2 3 4 5 6

fresh

P/E cycled

Retention time (sec)

V t (V ol ts)

300 350 400 450

0.0 0.1 0.2 0.3

Temp (K)

Vt (V ol ts )

t=10⁴s

Fig. 4.3 Cycling number dependence of the erase-state Vt drift. The thickness of bottom oxide is 5nm. It shows that the peak is around 10k P/E cycles.

Fig. 4.4 (a) Illustration of charge distribution in a 10k P/E cell. (b) Measured Vt and GIDL in a fresh device and in a cycled device.

10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 0.0

0.1 0.2

P/E Cycle

∆ Vt (Vol ts)

t=10⁴s

V

_t

GIDL

(a)

V

_t

GIDL

(a) (b)

positive

21.4pA 28.9pA

GIDL

negative

1.6 1.74

V_t

Net charge 1k P/E

Fresh

(a)

Fig. 4.5 (a) Measurement setup of positive oxide charge de-trapping induced substrate current (I^b). (b) Pre-stress and post-stress substrate currents in two large area devices (500µm×500µm). FN stress was at V^g=-18V for 3000s. Substrate current was measured at V^g=VFB.

I

_b

Fig. 4.6 Room temperature Vt drift in two 10k P/E cycled NROM cells fabricated with different ONO process. The cell size is L=0.5µm and W=0.35µm.

10 ¹ 10 ² 10 ³ 10 ⁴ 1.5

1.6 1.7 1.8 1.9 2.0

Process B Process A

Vt (V ol ts)

Retention time(sec)

Fig. 4.7 RT drift versus bottom oxide thickness in a 10k P/E cycled device.

Retention time is 10⁴s.

Fig. 4.8 Dependence of RT drift on erase time in a 10k P/E cycled cell.

4.5 5.0 5.5 6.0 6.5 7.0 0.0

0.1 0.2 0.3

Bottom oxide thickness (nm)

∆ V t (Vo lts)

t=10⁴s

10^-3 10^-2 10^-1 10⁰ 0.0

0.1 0.2 0.3

∆ Vt (V ol ts)

Erase time of the last-shot (sec.)

Fig. 4.9 Read-disturb caused Vt shift as a function of bottom oxide thickness in a 10k P/E cycled cell. The read bias condition is V^g=2.75V, V^d=1.6V and read-disturb time is 10⁴ sec.

Fig. 4.10 Temporal evolutions of Vt drift and read-disturb caused Vt shift. These two measurements are performed sequentially.

4.5 5.0 5.5 6.0 6.5 7.0 0.0

0.1 0.2 0.3

Bottom oxide thickness (nm)

∆ Vt (V ol ts )

t=10⁴s

10¹ 10² 10³ 10⁴ 1.5

2.0 2.5

Vt drift RD

10¹ 10² 10³ 10⁴ Vt drift

RD

Measurement time (sec.)

V t(V olts )

Fig. 4.11 Illustration of positive oxide charge assisted electron tunneling current (I^sd) at gate disturb. The time-dependence of Isd and corresponding Vt shift was derived in [4.1].

Fig. 4.12 Gate bias dependence of positive oxide de-trapping current (Ib) and electron tunneling current (Isd). The current is measured at t=0.6sec after Vg is applied.

I

_b

I

_sd

Q

_p

I

_b

I

_sd

Q

_p

0 2 4 6

10

^-12

10

^-11

10

^-10

I

_b

I

_sd

V

_g

-V

_FB

(Volts)

C u rren t (A mp )

Fig. 4.13 Hot carrier read-disturb caused ∆Vt in a fresh cell and in a 10k P/E cycled cell. The disturb time is 10⁴s.

Fig. 4.14 Comparision of gate disturb caused ∆Vt (Vg=3V, Vd=Vs=0V) and room temperature Vt drift (Vg=Vd=Vs=0V)

1.0 1.5 2.0 2.5 0.0

0.2 0.4 0.6 0.8 1.0

Vg=3V fresh 10k P/E

Read Bitline Voltage(Volts)

∆ V

t

(V ol ts )

10

¹

10

²

10

³

10

⁴

0.0

0.1 0.2 0.3

RT drift

10

^-2

10

^-1

10

⁰

gate-disturb

Retention time (sec.)

∆ Vt (Volts) t

^0.3

log(t)

Fig. 4.15 Program-state charge loss in a fresh and in a 100k P/E cycled cells.

T=25C and 85C.

Fig. 4.16 Program-state charge loss at different applied gate bias. T=25C

10⁰ 10¹ 10² 10³ 10⁴ -1.5

-1.0 -0.5

0.0 Vg=

0

-1 -2 -3 -5

Retention time (sec)

∆ Vt (Vo lts )

10² 10³ 10⁴ 10⁵

3.0 3.5 4.0 4.5

5.0 ^fresh

100k P/E

filled: T=25C open: T=85C

Retention time (sec.)

Vt (Volts)

Fig. 4.17 Illustration of nitride trapped electron emission and oxide trap assisted tunneling.

Fig. 4.18 Measured nitride charge de-trapping current (IN) in a large area device at V^g=-6V. The device was subjected to FN stress at V^g=-20V for 2000s.

10

⁰

10

¹

10

²

10

^-13

10

^-12

10

^-11

1x10

^-10

V

_g

=-6V

Retention time(sec)

G at e c u rren t (A mp )

t

^-1

Fig. 4.19 Program-state Vt loss versus applied gate bias (top axis). The bottom axis corresponds to the square root of the nitride electric field. Vo is the flat-band voltage in high-Vt state.

( V

^1/2

)

-1 -2 -3 -5

0

V _g

∆ Vt ( V olts )

( V

₀

-V

_g

)

1.5 1.8 2.1 2.4 2.7 0.0

-0.5 -1.0 -1.5 -2.0

E

∆V

_t

∝

Chapter 5

Numerical Simulation for Program-State Charge Retention in SONOS Flash Memory Cell

5.1 Introduction

Recently, considerable research efforts have been made to study the charge retention loss mechanisms in SONOS devices. Lundkvist et al. showed that trapped charge direct tunneling leads to charge loss at room temperature [5.1] and later they accounted for the increased decay rate of charge loss at elevated temperatures with a thermal-enhanced charge emission model [5.2][5.3]. Lehovec et al. delivered a simple analytical retention model through the Frenkel-Poole (FP) release of electrons from mono-energetic nitride traps [5.4]. Williams et al. regarded charge loss as direct tunneling of the charges out of the nitride together with nitride charge migration by a series of emission-capture events [5.5]. Recently, White et al. have combined trap-to-band tunneling and thermal excitation to reproduce measured device retention data [5.6][5.7]. Although a variety of models have been proposed, they have some deficiencies in common. For example, all the models are applicable only to ultra-thin bottom oxides (1.5nm~2.5nm). However, to improve data retention and to minimize gate disturb, a thicker bottom oxide is usually employed in today’s SONOS cells [5.8][5.9]. With a larger oxide thickness, oxide traps created by program/erase (P/E) stress becomes important and should be taken into account in a charge loss model. Second, several groups fitted their experimental results with unphysical attempt-to-escape factors [5.4][5.5][5.10]. The values ranging from 10⁶ s^-1 to 5×10⁸ s^-1

are extremely low and should be modified by Shockley-Read theory [5.11][5.12].

In this chapter, we develop a numerical approach to solve a set of rate equations governing the electron FP emission and re-trapping in the nitride and charge leakage through the bottom oxide [5.13]-[5.17]. Comprehensive charge loss mechanisms based on direct tunneling for trapped electrons and positive charge (oxide hole trap) assisted tunneling (PCAT) [5.13] for conduction band electrons in nitride are formulated. The effects of bottom oxide thickness and stress created oxide traps on charge retention are measured and simulated. The dominant leakage mechanisms for different bottom oxide thickness are identified.

5.2 Retention Loss Simulation Model

The samples used in this work are n-channel SONOS cells consisting of a top oxide of TTO=9nm, a silicon nitride of TN=6nm. The bottom oxide thickness (TBO) ranges from 1.8nm to 5nm. The measurement data for the Tbo=1.8nm device are quoted from [5.18] and other oxide thickness results are measured in this work. FN tunneling is employed for programming and erase. This uniform FN injection excludes the possibility of stored charge lateral migration in the nitride.

5.2.1 Nitride Charge Dynamics and Loss Mechanisms

Charge transitions between the conduction band and trap states in the nitride and stored charge leakage paths are illustrated in the energy band diagram in Fig. 5.1.

The change of conduction band and trapped electron densities in the nitride is described by the following two coupled rate equations [5.14]-[5.16]:

t) distance to the SiN/bottom oxide interface (y), trap energy φN, and retention time t, respectively. The density of electrons in the nitride conduction band is denoted by nc(cm^-3), which is assumed to be uniform in x because the nitride layer is sufficiently thin. Re, Rc, Rt, RPCAT, and RDT are the rate coefficients for FP electron emission from nitride traps (path a in Fig. 5.1), free electrons capture into nitride traps (path b), trapped electron direct tunneling to the substrate (path c), conduction band electron escape through PCAT (path d) and via direct tunneling (path e), respectively. The FP excitation of electrons from nitride traps to the conduction band is [5.4]

The pre-factor νe is often referred to as the attempt-to-escape ＂ frequency for emission and can be expressed as Eq. (5-3a) where Ncn is the effective density of states in the nitride conduction band, υth is the thermal velocity and σN is the nitride trap capture cross section. β is the FP constant and En is the average electric field in the nitride. τe(φ) is the electron emission time from the trap energy of φN. The free electron capture rate coefficient is

)

where Nt is the nitride trap density per unit trap energy. (Nt−nt) is the amount of available traps for free electron re-capture. The direct tunneling rate for nitride- trapped electron is

where mox* and mN* are electron tunneling mass in the oxide and in the nitride.

Other variables have their usually definitions.

As for conduction band electron leakage paths, positive oxide charge assisted tunneling [5.13] and direct tunneling through the bottom oxide are considered.

Charge leakage via top oxide is not considered for a relatively large top oxide thickness. The built-in electric field in the ONO stack is neglected for simplification.

Electron tunneling from nitride traps to surface traps in Si band gap is also neglected.

To simplify the evaluation of PCAT, a concept of the most favorable trapped charge position is employed [5.19][5.20]. With an oxide charge site at this favorable position, the tunneling probability from the conduction band to the trap site is the same as that from the trap site to the substrate conduction band. Such feature of the most efficient tunneling trap location leads to the following equation

PCAT ox

th ox

PCAT N P

R = ⋅υ ⋅σ ⋅ _{(unit: s}^-1) (5-6)

1 PCAT

PCAT =R ⁻

τ _{(unit: s)} (5-6a)

where Nox is the stress-induced oxide hole trap (positively charged) density. PPCAT is the tunneling probability from the nitride conduction band to the substrate. τPCAT is the electron tunneling time via PCAT. The way to calculate the tunneling probability PPCAT is the same as in [5.13]. A one-dimensional Coulombic potential caused by a positive trapped charge is included in the electron tunneling barrier for the WKB approximation, i.e.,

h ox

coul 4 y y

) q y

( = πε −

Φ (5-7)

where εox is permittivity of oxide and yh denotes the location of a trapped positive charge from SiN/bottom oxide interface. Besides, the direct tunneling rate can be

where εox is permittivity of oxide and yh denotes the location of a trapped positive charge from SiN/bottom oxide interface. Besides, the direct tunneling rate can be

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