4-1 Conclusion
In this thesis, the effects of PECVD SiN process and the channel strain induced by the SiN-capping layer on the device characteristics and hot-electron degradation were investigated. Several important phenomena were observed and summarized as follows.
Firstly, the channel strain induced by the tensile SiN capping layer over the gate greatly boosts the drive current of short-channel NMOS devices. For example, as high as 15.4 % enhancement is achieved for the SiN-capped NMOS devices with a flow rate ratio of N2/SiH4=20 at a channel length of 0.4 μm. This is ascribed to the large difference in the expansion coefficient between SiN film and Si-substrate. Since n-channel devices with a compressive SiN capping layer show lower Gm than the control samples, it can be confirmed that either current enhancement or current degradation can be observed by varying the strain polarity. In addition, we also find that without the associated thermal budget, the deposition of the PECVD SiN capping layer can not alleviate the reverse short-channel effect of the devices, and the poly-depletion effect will not be enhanced. Finally, we find that the dielectric constant for the SiN film grown with a flow rate ratio N2/SiH4=20 is not different from the
other two splits with different flow rate ratio.
Secondly, hot-electron degradation is negatively affected when the SiN layer is deposited over the gate. However, we find that the negative impact in reliability can be alleviated by properly tuning the flow rate of SiH4 and N2. The hydrogen atoms tend to bond with nitrogen for nitrogen-rich film with increasing N2 flow rate, resulting in less diffusion of hydrogen species from the SiN to the oxide/channel interface.
In conclusion, we find that for the SiN-capped NMOS devices, the electrical performance and reliability both improve with increasing N2 flow rate. In other words, SiN-capped devices with optimized SiN deposition condition can maintain enhanced mobility while showing alleviated hot-carrier degradation. Optimization of both SiN deposition process and the film properties is therefore essential for the implementation of uniaxial strain in NMOS devices.
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Fig. 1.1 Schematic illustration for 3D process-induce strain component[25]
Fig. 1.2 Simple schematic of conduction and valence band bending with strain.[21]
Fig. 1.3 Schematic diagram of the energy sub-bands with unstrained and bi-axial strain in an MOS inversion layer.[26]