The charge transient behavior in a SONOS type flash memory has been characterized. By a multiple trapping model and two sets cross-coupled SRH rate equations, the charge loss path and the associated components are identified successfully. The Frenkel-Poole emission as well as free carriers retrapping depicts the conduction inside SiN film. And the leakage current is attributed to the loss from the nitride conduction band and trap states.
Anticipating the use of numerical analysis, the discretized meshes are required.
Utilizing a backward Euler implicit method with Newton’s iteration, the non-linear, stiff equations are solved numerically. This method can enable us to obtain the information at each moment.
As the bottom oxide thickness increases, the leakage current is limited for a long time. This phenomenon is referred to “current blocking effect”. The blocking corner time decreases after the cells suffer high field stress. This corner time can be treated as an index of bottom oxide quality. The shorter corner time corresponds to the poorer oxide quality. In addition, at a high temperature environment, the voltage decay will be enhanced due to thermionic field emission. According to simulated trapped charge distribution, the “empty-filled” boundary moves deeper with increasing temperature.
It implies that more deep trapped carriers are excited and then accelerating the charge loss.
Reference
[1] F. R. Libsch and M. H. White,” Charge Transport and Storage of Low Programming Voltage SONOS/MNOS Memory Devices,” Solid-State Electronics Vol. 33, pp. 105-126, 1990.
[2] Eiichi Suzuki, Hisato Hiraishi, Kenichi Ishil and Yutaka Hayashi, “A Low-voltage alterable EEPROM with Mental – oxide – nitride – oxide – Semiconductor (MONOS) Structures,” IEEE Trans. Electron Devices, pp.122-128, 1983
[3] M. K. Cho and D. M. Kim, “High Performence SONOS Memory Cells Free of Drain Turn-On and Over Erase: Compatibility Issue with Current Flash Technology,” IEEE Elect. Dev. Lett., Vol.21, pp. 399-401, 2000.
[4] M. White, “On the Go with SONOS,” IEEE Circuit and Device Magazine, pp.22-31, 2000.
[5] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A Novel Localized Trapping, 2–Bit Nonvolatile Memory Cell”, IEEE Elect. Dev.
Lett., Vol. 21, pp. 543-545, 2000.
[6] B. Eitan, P. Pavan, and I. Bloom, “NROMTM – A New Technology for SONOS Non-Volatile Memory Products” Solid-State Electronics Vol. 46, pp. 1757-1763, 2002.
[7] B. Eitan, “Non-Volatile Semiconductor Cell Utilizing Asymmetrical Charge Trapping”, U. S. Patent 5 768192, June 16, 1998.
[8] L. Lundkvist, C. Svensson, and B. Hansson,” Discharge of MNOS Structures at Elevated Temperatures,” Solid-State Electronics, Vol. 19, p.221, 1976.
[10] K. Lehovec and A. Fedotowsky, “Charge Retention of MNOS Devices Limited by Frenkel-Poole Detrapping”, Appl. Phys. Lett., Vol. 32, p.335, 1978.
[11] M. H. White and J. R. Cricchi “Characterization of thin-oxide MNOS memory transistors” IEEE Trans. Electron Devices, pp.1280-1288, 1972.
[12] Tahui Wang, W. J. Tsai, S. H. Gu, C. T. Chan, C. C. Yeh, N. K. Zous, T C. Lu, Sam Pan, and Chih-Yuan .Lu, “Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells (Invited Paper),”
IEDM Tech. Dig., pp. 169-172, 2003.
[13] Yu Wang and M. H. White, “An Analytical retention Model for SONOS Nonvolatile Memory Devices in the Excess Electron State,” Solid-State Electronics, Vol. 49, p.97, 2005.
[14] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, Tahui Wang, Sam Pan, Chih-Yuan Lu, and S. H. Gu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell” IEDM Tech. Dig., pp. 719-722, 2001.
[15] Gowrishankar L. Chindalore, C. T. Swift, and David Burnett, “A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories,” IEEE, Elect. Dev. Lett., Vol.24, p.257-259, 2003.
[16] Peter C. Y. Chen, “Threshold-Alterable Si-Gate MOS Devices,” IEEE Trans.
Electron Devices, pp.584-586, 1977.
[17] W. J. Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, Tahui Wang, Sam Pan, and Chih-Yuan Lu, “Cause of Data Retention Loss in s Nitride-Based Localized Trapping Storage Flash Memory Cell”, Proc. Int.
Reliability Phys. Symp., pp. 34-38, 2002.
[18] Ross A. Williams and Moiz M. E. Beguwala, ”The Effect of Electrical Conduction of Si3N4 on the Discharge of MNOS Memory Transistors,” IEEE Trans. Electron Devices, Vol. 25, pp.1019-1023, 1978.
[19] T. H. Kim, J. S. Sim, J. D.Lee, H. C. Shim, and B. G. Park, ”Charge Decay Characteristics of Silicon-Oxide-Nitride-Oxide-Silicon Structure at Elevated Temperatures and Extraction of the Nitride Trap Density Distribution,” Appl.
Phys. Lett., Vol. 85, p.26, 2004.
[20] P. C. Arnett, “ Transient Conduction in Insulators at High Fields,” J. Appl. Phys., Vol. 46, pp. 5236-5243, 1975.
[21] W. Shockley and W. T. Read,” Statistics of the Recombinations of Hole and Electrons,” Phys. Rev. Vol. 87, p. 835, 1952.
[22] Sze, Physics of Semiconductor Devices 2nd Edition, Johb Wiley & Sons Publishers.
[23] C. Sevensson, “Trap-assted Charge Injection in MNOS Structures,” J. Appl.
Phys., Vol. 44, pp. 4657-4663, 1973.
128, p. 596, 1962.
[25] P. J. McWhorter, S. L. Miller, and T. A. Dellin, “Modeling the Memory Retention Characteristics of Silicon-Nitride-Oxide-Silicon Nonvolatile Transistors in a Varying Thermal Environment,” J. Appl. Phys., Vol. 68, pp.
1902-1909, 1990.
[26] Luca Larcher, Paolo Pavan, and Boaz Eitan, “On the Physical Mechanism of the NROM Memory Erase,” IEEE Trans. Electron Devices, pp.1593-1599,2004.
[27] Ross A. Williams and Moiz M. E. Beguwala,” The Effect of Electrical Conduction of Si3N4 on the Discharge of MNOS Memory Transistors,” IEEE Trans. Electron Devices, Vol. 25, pp.1019-1023, 1978.
[28] K. A. Nasyro, V. A. Gritsenko, M. K. Kim, H. S. Chae, S. D. Chae, W. I. Ryu, J.
H. Sok, J. W. Lee, and B. M. Kim, “ Charge Transport Mechanism in Metal-Nitride-Oxide-Silicon Structures,” IEEE. Elect. Dev. Lett., Vol. 23, pp.336-338, 2002
[29] Gerald W. Recktenwald, Finite-Difference Approximation to the Heat Equation.
[30] M. Borissov, N. Kirov, J. M. Marshall, and A. Vavrek, New Physical Problem in Electronic Materials, p.55, 21-29 September, 1990.
[31] M. French, H. Sathianathan, and M. White, “A SONOS Nonvolatile Memory Cell for Semiconductor Disk Application,” 5th Nonvolatile Memory Technology Review, Linthicum Heights, Md., p. 70, June 22-24, 1993.
[32] Y Yang, M. H. White, “Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures. Solid-State Electronics Vol. 44, pp. 948-958, 2000.