CHAPTER 1 INTRODUCTION
1.2. T HESIS M OTIVATION
There are some advantages compare the ADPLL based with the analog based frequency synthesizer design. Traditional analog loop filter costs a lot of chip areas, since it uses resistance and capacitor. Digital loop filters gives benefits such as programmable parameters, robustness against noise and less power consumption. Digital design also can prevent to DC offset and drift phenomena. The digital design has another advantage that is the Electronic
Design Automation (EDA) tools. With the EDA tools help, designers can do Place and Route (P&R) easily. However, it is not the same situation for the most critical components such as DCO. The designers need to set proper constraints to the EDA tools; otherwise the EDA tools will not synthesis the desired circuits. For example, a delay chain composed of cascade routing by manual. This art gets the advantages both of analog and digital design.
Clock generator is the most important component of frequency synthesizer. In the analog designs, voltage controlled oscillator (VCO) are usually used to providing low phase noise frequency. This advantage comes with many disadvantages such as power consumption, area cost. Those issues make VCO is not suitable for mobile application. In this work, the proposed DCO is high-resolution and wide-bandwidth; moreover, it is a low power and small area design. Those good properties make the DCO to fit low power and mobile application.
1.3. Thesis Organization
The organization of this thesis is as follows:
In chapter 2, it is a brief to the applications of the Frequency synthesizer. And introduce the advantage of the Frequency synthesizer based on ADPLL.
In chapter 3, the proposed ADPLL is introduced. A detailed description of the idea and simulation are given. Including how we used standard cell to complete coarse tune and fine tune cell in DCO.
In chapter 4, we illustrated the hardware implementation and layout. A detailed description of the DCO implementation has illustrated.
In chapter 5, some concluding remarks will be derived from this research. Finally, we describe several design issues that needed to be further explored in the near future.
Chapter 2
Overview of Frequency Synthesizer
There are many applications need clock synchronization or frequency multiplication.
Several methods could meet the functional required but how to balance the cost and performance should never be ignored. In this chapter, gives a discussion about the advantages and disadvantages between those different approaches.
The organization of this chapter is as follows. Section 2.1 gives the overview of the frequency synthesizer. The architecture and algorithm of different digital PLL are discussed in section 2.2. Section 2.3 illustrates frequency synthesizer based on ADPLL.
2.1. Overview of Frequency Synthesizer
Frequency synthesizer (Fig. 2-1) accepts some frequency reference input signal (FREF) of a very stable frequency and then generates output frequency by the frequency
command word (FCW).
fout fref
(Fig. 2-1)
The relation between output frequency and FCW has represented in the equation.
(Eq.2-1)
There are many applications such as date recover, wireless communication, and microprocessor need frequency synthesizers. Base on different purposes and demands, Frequency synthesizer have different implementations. From the view of techniques, there are three major types of frequency synthesis techniques [8]. 1. Direct analog mix/filter/divide. 2.
Direct digital. 3. Indirect or phase-locked loop. Following section is the discussion of these three types.
2.1.1. Direct Analog Synthesis
Direct Analog Synthesis to produce the desired frequency by using frequency multipliers, dividers, filter and other mathematical manipulation. The quality of the output frequency correlates directly with the quality of the input. The advantages of this process type are the phase noise typically excellent, because the direct process and switching speed can be very fast. A broadband synthesis that used direct analog synthesis requires many references frequency, which makes it expensive. The disadvantages are high cost and high power consumption.
2.1.2. Direct Digital Synthesis
Fig. 2-2 shows the direct digital frequency synthesis (DDFS) system. A DDFS system used logic and memory to construct the desired output signal digitally, and a data conversion device to convert it from the digital to the analog domain. Although it can provide precise amplitude, frequency and phase, the power consumption could be excessive at high clock frequencies. Besides, the DAC and LPF are not pure digital designs. They contain analog components.
(Fig. 2-2)
2.1.3. Indirect Synthesis Using Phase Locking
Indirect synthesis using a PLL compares the output phase of an oscillator, such as a VCO, with a phase of a reference signal FREF. As the output drifts, detected errors produce correction commands to the oscillator, which responds in a negative-feedback controller. In general, the indirect synthesizer uses a PLL and a programmable fractional-N divider, which multiplies the stable reference frequency. In the loop, a loop filter is present so as to suppress spurs produced in the phase detector so that they do not cause unacceptable frequency modulation in the VCO. However, the filter causes degradation in transient response, which limits the switching time. Therefore, the requirements for frequency switching time and suppression of spurs are in conflict.
2.2. Overview of Phase-Locked Loop
A typical Phase-locked loop (PLL) consists of phase/frequency detector (PFD), loop
filter, voltage-controlled oscillator (VCO) and frequency divider, as shown in Fig. 2-3. PFD detects the phase/frequency error between the REF CLK and DIV CLK, and sends to the Loop filter. Usually, PFD gives UP/DOWN signal into a charge pump for translate error signal from current to voltage. Loop filter provides a smooth control voltage to VCO.
Therefore, VCO can provide desired output clock and feedback to frequency divider to form a negative feedback loop. The PLL has several analog devices such as charge pump, loop filter and VCO. Oscillator is one of the most important parts in PLL. There has been a significant research effort in VCO for WLAN application [2]. VCO can provide almost perfect sinusoidal signal. However, several fundamental issues such as control linearity, frequency resolution, power consumption and cost area need to be considered.
(Fig. 2-3)
Fig.2-4-1 shows the relation between control-voltage and VCO output frequency. In IEEE-802.11a [9], it uses Unlicensed National Information Infrastructure (U-NII) from 5150 to 5825MHz. It means that if the control-voltage is 1.8V, it must provide voltage resolution down to 135mV for 5MHz resolution. Besides, VCO is usually composed of inductor and capacitor for oscillator circuit. Fig.2-4-2 [2] shows the spiral structure of inductor. The inductors occupy most of the chip area. And it is usually layout by fully customer.
Fully-customer layout technique is very critical part for performance.
(Fig.2-4-1) (Fig.2-4-2)
2.3. Frequency Synthesizer based on All-Digital Phase-locked Loop
Basically, ADPLL based Frequency synthesizer is the same as the induction in Section 2.1.3. It takes out the analog components such as loop filter and VCO. The architecture shows in Fig. 2-5. The divider in frequency synthesizer is usually programmable. It divided the DCO output clock by “N” before into PFD. So, divided clock synchronize with reference clock thus DCO clock will be N times of reference clock. This mechanism makes synthesizer can synthesis different clock. However, it also comes with issues such as long locking cycle and jitter.
(Fig.2-5)
Chapter 3
The Proposed All-Digital Phase-Locked Loop
In this chapter, a detail description for the proposed frequency synthesizer based on ADPLL is given.
3.1. All-Digital Phase-Locked Loop Architecture Overview
The ADPLL is shown in Fig. 3-1. It has four major function blocks, such as PFD, Loop Filter, digital-control-oscillator (DCO) and loop divider. PFD detects the difference between extern reference clock and divided clock. Its output signal indicates the divided clock slower or faster than reference clock. There are three main considerations in designing PFD, Glitch, Dead Zone and Operation Frequency. Loop filter used to eliminate glitch, jitter and smooth the control signal. DCO gives output clock by the control signal.
(Fig. 3-1)
ADPLL is the core of this proposed Frequency Synthesizer. In this paper, an ADPLL is proposed to against control linearity, frequency, power consumption and area. A low complexity of ADPLL is proposed to reduce gate count and power consumption. Standard cell is used to implement the DCO and achieve wide-bandwidth and high frequency resolution. We utilize the digital circuit design techniques to gain the analog circuit design benefit. The ADPLL can be divided into three basic functions, such as frequency tracking, frequency evaluation and clock generation. The proposed ADPLL block diagram is shown in Fig.3-2. Frequency detector, Phase detector and TDC are used for tracking frequency error.
ALU is used to calculate the DCO command word from frequency error. DCO and frequency
divider are used for clock generation.
(Fig. 3-2)
3.1.1. The tracking algorithm
In this section, the proposed frequency/phase tracking algorithm is described. The goal of the tracking algorithm is to make different source clock “synchronized”. At beginning, we take an arbiter time to compare two clocks reference clock and internal divided clock, named REF and DIV clock respectively. Obviously, there are three schemes between the REF and DIV clock. First, the difference between two clocks (frequency error) is small enough. This scheme is called “Frequency locked” as Fig.3-3-1. Second, the internal DCO clock is faster than reference clock. This scheme called “Frequency lead” as Fig.3-3-2, whereas called
“Frequency lag” as Fig.3-3-3.
(Fig.3-3-1) (Fig.3-3-2) (Fig.3-3-3)
As introduction in chapter 2, Frequency synthesizer is designed to synthesis the required frequency from reference frequency. ADPLL needs stay in locked state. If not, Controller issues the control signal to slower or faster DCO output frequency. Thus, the controller has to determine which scheme that ADPLL stays now. This proposed tracking algorithm use a frequency counter to detect frequency error instead of using PFD directly. In order to detect the scheme, a number “N” has been given in the frequency counter. The frequency counter starts to count the DCO clock from positive edge of reference clock and stop at next positive edge. This approach can prevent from doing clock retiming in ADPLL and then the ADPLL will be low complexity. First, if the counter counts number “N-counter” smaller than the number “N-set”. It means that DCO clock is slower than reference clock. For example, the target frequency is six times of reference clock. In other words, there are six DCO clock
cycles in one reference clock cycle. Thus, if the frequency counter number is smaller than six, it means one reference clock cycle don’t have six DCO clock cycles. So, the DCO clock is slower than the required. Fig.3-4-1 shows this scheme. The top of green line indicates the counter is active.
(Fig.3-4-1)
Fig.3-4-2 shows the second scheme. If the number “N-counter” of the counter is bigger than “N-set”, it means that DCO clock is faster than reference clock. In this example, the target frequency is six times of reference clock. It means in one reference clock have more than six DCO clock. So, the DCO clock is faster than required.
(Fig.3-4-2)
Fig.3-4-3 shows the last scheme, the frequency error is smaller than frequency counter detection range. So the frequency counter count number “N-counter” exactly same as the number “N-set”. It represents the frequency is locked. In those schemes, delta1 and delta2 is the phase error. TDC is used to detect the small phase error.
(Fig.3-4-3)
3.2. Basic concept of DCO Implementations
In this section, we will introduce basic concept of the proposed DCO. The proposed DCO are based on DTC, ring oscillator, DCV [6] techniques.
3.2.1. Digital-to-Time converter
Digital-to-Time converter is used for extending DCO operation frequency range. Fig.3-5 shows the basic idea. It uses internal counter to count the extend clock cycle. The input control word C1 determines how many internal cycles will add to input clock cycle. For example, the one internal cycle is “S ns” that C1=20. It will provide 20*s ns delay to original input clock. In general, the DTC is one of the delay elements in the DCO.
(Fig.3-5)
3.2.2. Ring Oscillator
A basic Ring Oscillator is a delay chain that contains many inverters. Fig.3-6 shows the diagram. Each inverter cell has gate delay, various number of inverter can provide different delay clock. Equation (Eq. 3-1) expressed the delay of each inverter cell. Where is load capacitance, is the output voltage swing, and is the driving current to the load. From (1) we can express the Ring Oscillator Frequency in (Eq. 3-2). Changing number of inverter stages or the load capacitance or driving current to the load, either can change the clock period. [5]
(Fig. 3-6)
3.2.3. Digitally controlled Varactor (DCV)
The minimum resolution of inverter delay chain is limited by the gate delay. According to a well know concept , attach a delta capacitance on delay chain will change the delay time [6]. In this work, using and-or-inverter standard cell forms the digitally
controlled varactor as shown in Fig. 3-7. The digitally controlled varactor is not limited by the gate delay, so the resolution can be enhance.
∆ C
Cg(Fig. 3-7)
3.3. Standard Cell-based Digital-Control-Oscillator (DCO)
Since DCO is the heart of the ADPLL, it domains the performance of the ADPLL like jitter. We propose a high resolution Standard Cell-based Digital-Control-Oscillator to again jitter. The architecture has three major function blocks such as Digital to Time converter, coarse tune cell and Fine tune cell. Fig.3-8 shows the function blocks.
(Fig. 3-8)
In this work, there are 27 control bits for frequency adjustment. Each cell control bits illustration as below. DTC has 9 bits (C1[8:0]) for extending operation frequency range.
Coarse tune cell has 5 bits (C0[4:0]) for select different delay line. First fine tune cell has 3 bits (F1[2:0]) that would be binary decoded to 7 control stages, each stage provided 4.4ps.
Second fine tune cell has 3 bits (F2[2:0]) that would be binary decoded to 7 control stages.
Each stage provided 835fs. The third and the fourth fine-tune cell are not the same as the first and the second fine-tune cell since these didn’t pass clock, these affect the clock period by using DCV [6]. Third fine tune cell has 4 bits (F3[3:0]) decoded to 15 control stage, each stage provided 67.8fs. The fourth fine-tune cell is the last fine-tune cell that influences LSB resolution. This work achieves the minimum resolution to 10fs
Table 3.1
3.3.1. Digital to Time Converter DTC
DTC gives a wide-bandwidth operation function in DCO. It contains counter multiplex and an oscillator ring for internal clock generation. The basic idea is to extend an extract period by the counter. Fig.3-9 shows the architecture.
INC
“Out_reg” changes the signal level. Then output signal goes to next stage of DCO. The control setting determines the working period of the counter. If the setting C1[8:0] is “511”
that has the longest counter working period so the maximum extended clock period is gotten.
If the setting C1[8:0] is “0” the “Equal” is always high. The minimum clock period is gotten.
The DTC internal clock period is 906ps. The maximum and minimum clock period is 930ns and 2.95ns separately. While C1[8:0] increase, the DTC increases 1.8ns by step. The frequency range is from 1MHz to 338.8MHz. The DTC has designed to the operation frequency range. Using fine tune cell can get high solution. In this work, 10fs resolution has been proposed. Besides, DTC can increase operation without increasing chip area. That is not practical to use DRV cell only for wide-bandwidth, because it needs a lot of chip area.
3.3.2. Coarse-tune cell
After DTC stage is coarse-tune cell. In this coarse-tune cell consists of many inverters and NANDs. Furthermore, the delay chain can be separated into different segments. The basic idea of coarse-tune cell is to use multiplex for selecting different delay chain.
MUXMUX MUX
MUXMUX
MUXMUX
(Fig.3-10)
This Coarse-tune cell has 5 bits controlled word that 5 bits is decoded to 2^5 =32. Thus, this coarse-tune cell has 32 different selections. Fig.3-12 shows the delay path and multiplex select array. These multiplexers could be separated into five groups that are mapped to 5 control bits. Every multiplex has the same principle that input delay path “DelayA” is longer than input delay path “DelayB”. When the multiplex select signal is “high”, the output is selected from input “DelayA”. Therefore, the control word C0[4:0]=[11111] has the longest delay path. When C0[4:0] =[00000], the selected path is minimum, the delay time is intrinsic delay pass through 5 multiplexers. Because we used binary decode, the control words C0[4], C0[3]… C0[0] have different weight. Each control bit is just mapped to each multiplex group.
The LSB C0[0] controls the first multiplex group. In this group each multiplex input path
“DelayA” is added two more delay stages then input path “DelayB”. In this group, the delay path “DelayB” is selected while multiplex select signal is high. In other words, control bit C0[0] is high will select longer delay path, hence longer delay time been provided. The next multiplex group is the same as above. Multiplex select signal is high will provide longer delay time. There is another advantage used NAND cell in delay path, if the delay path had not been selected then the signal behind won’t transition. It means save power consumption.
3.3.3. Fine-tune cell
Fine-tune cell is designed to provide high resolution. In order to get high frequency resolution without too many cell. Fine-tune cell separate to four stage that first (Fine1), second (Fine2), third (Fine3) and fourth (Fine4). Each stage has different resolution. First fine-tune cell and Second fine-tune cell are cascade. Fine3 and Fine4 is joint the clock path but clock didn’t pass through directly. This can decrease total gate delay, prevent the clock path pass through too much gate. The minimum resolution is 10fs provided from fourth fine-tune cell. Beside, for linearity operation each stage’s tuning range will overlap to next stage. First fine-tune cell LSB is overlapped to second fine-tune cell MSB and so on.
Fig.3-11 shows the inter-connection between fine-tune cell. Fig.3-12 present the fine-tune cell as addition capacitors.
(Fig.3-11)
∆ C
Cg
∆ C ∆ C ∆ C
(Fig.3-12)
First fine-tune cell used OAI standard cell, there are 7 stages in Fine1. The control word from F1[6:0] =[000_0000] to F1[6:0]=[000_0001] turn on one control stage, the delay time add one stage delay 4.4ps. F1[6:0]=[000_0000] to F1[6:0]=[111_1111] tun on seven control
stages, so the delay time increases : .
Fine2 used OAI and also has 7 stages. The control word F2[6:0]=[000_0000] to F2[6:0]=[000_0001] turn on one control stage, the delay time increases 835 Femto-second(fs).
Also F2[6:0]=[000_0000] to F2[6:0]=[111_1111] turn on 7 stages, the delay time will add : . Fine2 maximum delay time 5845fs is longer than Fine1 minimum delay time 4400fs.
Fine3 has 15 stages and its control word logic is opposite to other fine-tune cell. While F3[14:0]=[00…0000] to F3[14:0]=[00…0001], the delay time is decreased 67.8fs. However, it won’t affect the control linearity. Fine3 maximum delay time is
also can cover the Fine2 minimum delay time. Fine4 cell used AOI cell to achieve 10f s resolution. F4[6:0]=[000_0000] to F4[6:0]=[000_0001], the delay time is add 10fs. The maximum delay is
Chapter 4
Simulation and Layout
In this chapter, we illustrate the hardware implementation and simulation. The steps of the semi-fully layout are introduced in appendix A.
4.1. SPICE simulation
As illustration above, the minimum DCO resolution is provided by fine-tune cell. We used SPICE simulation to find out every standard cell’s delay time. Fig. 4-1 shows the schematic of and-or-inverter (AOI) cell.
(Fig. 4-1)
There are four input pins A, B, C1 and C2 in AOI cell. The purpose of SPICE simulation is to find the resolution by the setting of AOI input pins. As VLSI technology, we knows that measured pin A capacitance at pin’s level (B,C1,C2)=[0 0 1] is different with (B,C1,C2)=[0 0 0]. Assumption the difference of capacitance is from Eq. 3-1 will get the
. Thus, pin A as load and pin C2 as control pin. Fig. 4-2 shows the simulation wave form.
(Fig. 4-2)
That is one of the simulation conditions for pin A as load and pin C2 as control. There are total 48 simulation conditions in one standard cell, and we take all of the AOI and OAI
That is one of the simulation conditions for pin A as load and pin C2 as control. There are total 48 simulation conditions in one standard cell, and we take all of the AOI and OAI