F INE - TUNE CELL

Fine-tune cell is designed to provide high resolution. In order to get high frequency resolution without too many cell. Fine-tune cell separate to four stage that first (Fine1), second (Fine2), third (Fine3) and fourth (Fine4). Each stage has different resolution. First fine-tune cell and Second fine-tune cell are cascade. Fine3 and Fine4 is joint the clock path but clock didn’t pass through directly. This can decrease total gate delay, prevent the clock path pass through too much gate. The minimum resolution is 10fs provided from fourth fine-tune cell. Beside, for linearity operation each stage’s tuning range will overlap to next stage. First fine-tune cell LSB is overlapped to second fine-tune cell MSB and so on.

Fig.3-11 shows the inter-connection between fine-tune cell. Fig.3-12 present the fine-tune cell as addition capacitors.

(Fig.3-11)

∆ C

Cg

∆ C ∆ C ∆ C

(Fig.3-12)

First fine-tune cell used OAI standard cell, there are 7 stages in Fine1. The control word from F1[6:0] =[000_0000] to F1[6:0]=[000_0001] turn on one control stage, the delay time add one stage delay 4.4ps. F1[6:0]=[000_0000] to F1[6:0]=[111_1111] tun on seven control

stages, so the delay time increases : .

Fine2 used OAI and also has 7 stages. The control word F2[6:0]=[000_0000] to F2[6:0]=[000_0001] turn on one control stage, the delay time increases 835 Femto-second(fs).

Also F2[6:0]=[000_0000] to F2[6:0]=[111_1111] turn on 7 stages, the delay time will add : . Fine2 maximum delay time 5845fs is longer than Fine1 minimum delay time 4400fs.

Fine3 has 15 stages and its control word logic is opposite to other fine-tune cell. While F3[14:0]=[00…0000] to F3[14:0]=[00…0001], the delay time is decreased 67.8fs. However, it won’t affect the control linearity. Fine3 maximum delay time is

also can cover the Fine2 minimum delay time. Fine4 cell used AOI cell to achieve 10f s resolution. F4[6:0]=[000_0000] to F4[6:0]=[000_0001], the delay time is add 10fs. The maximum delay is

Chapter 4

Simulation and Layout

In this chapter, we illustrate the hardware implementation and simulation. The steps of the semi-fully layout are introduced in appendix A.

4.1. SPICE simulation

As illustration above, the minimum DCO resolution is provided by fine-tune cell. We used SPICE simulation to find out every standard cell’s delay time. Fig. 4-1 shows the schematic of and-or-inverter (AOI) cell.

(Fig. 4-1)

There are four input pins A, B, C1 and C2 in AOI cell. The purpose of SPICE simulation is to find the resolution by the setting of AOI input pins. As VLSI technology, we knows that measured pin A capacitance at pin’s level (B,C1,C2)=[0 0 1] is different with (B,C1,C2)=[0 0 0]. Assumption the difference of capacitance is from Eq. 3-1 will get the

. Thus, pin A as load and pin C2 as control pin. Fig. 4-2 shows the simulation wave form.

(Fig. 4-2)

That is one of the simulation conditions for pin A as load and pin C2 as control. There are total 48 simulation conditions in one standard cell, and we take all of the AOI and OAI cells in CIC 90nm cell library. The 48 simulation conditions come from selected one control pins and one load pin in 4 pins. And other two pins could be [0 0] [0 1] … [1 1] total 8 condition. The simple derivation as follow: .

Next, analyze all the simulation results then pick up which conditions can meet request.

Due to the huge data, using analyze tool is necessary. First, the simulation is to select the delay time will response as control signal, as we discussion above. Fig. 4-3-1 and Fig 4-3-2 show the relation between control signal and cycle-to-cycle jitter. Both plot come from AOI standard cell named AOI112LTX2, but different pins arrange. In Fig. 4-3-1, pins arrangement is (A,B,C1,C2)=[1CL0]. In Fig. 4-3-2, pins arrangement is (A,B,C1,C2)=[1CL0].This is an opposite result; The cycle-to-cycle jitter in Fig. 4-2-1 is variance all the simulate time, changing the control signal didn’t affect the delay time. The cycle-to-cycle jitter in Fig. 4-2-2 is related to control signal. It is a stable result that we can pick up for candidate.

(Fig. 4-3-1) (Fig. 4-3-2)

After finish this step around all of the standard cells, all the result has sorted by rise and fall time as show in Fig. 4-4. The sorting table helps us to select which cell and pins arrangement

can meet our request. The rise and fall time balance is necessary. Finally, we can get what pins arrangement of standard cells as we need.

(Fig. 4-4)

4.2. Layout.

In this work, there are two layout art, one is tradition layout using EDA tools for auto place and route the other is our proposed semi-fully customer layout.

Fig. 4-4 shows the most important component, Fine-tune cell. The routing layer didn’t change that can prevent extra stray capacitance. This fine-tune cell consist of four fine-tune cell. The inter connection illustrated in Fig. 3-11. The place locating is well arranged for decrease routing difficulty.

(Fig. 4-5)

Fig. 4-5 shows the coarse tune cell. It is a delay and multiplex array. Because it is an array structure, we need to consider the path distance of the same coarse stage.

(Fig. 4-6)

Fig. 4-6 shows the whole layout. It uses EDA tool to do P&R, but contains the manual layout. The critical component layout by manual can gain the performance. The other part used EDA tools can save the time. It is similar mixed signal design flow, but in this work the fully-customer layout is unnecessary.

Table 4-1 shows the DCO performance. The chip area is only 687um x 687um. The power consumption is only 664.1uW in worse case. The whole chip layout shows in Fig. 4-7.

We also used nano-sim to do post-layout simulation. The demonstration result shows in Fig.

4-8.

(Fig. 4-7)

Table 4-1

Item Specification (unit) Supply voltage 1.0 V(tc)

0.9 V(wc)

Bandwidth 187KHz~345MHz (wc) 351KHz~598MHz (tc) Resolution 10fs

POWER Dissipation

664.1uW (wc)

Chip Size 687um*687um

(Fig. 4-8)

Chapter 5

Conclusion and Future Work

5.1 Conclusion

In order to realize ADPLL based Frequency synthizer. The semi-fully customer layout art has proposed. It gives a new design flow in SoC design. With this art, a high-resolution of DCO can be implemented. In this work, we used standard cells which provided by CIC 90nm process to archive high resolution. The LSB resolution is 10 fs as the HSPICE simulation results. The proposed DCO frequency range is from 187 KHz~345MHz that extended by the DTC. We also give a low complexity tracking algorithm which locking time is 30 cycles in typical case.

5.2 Future Work

We have several works proposed to extend this design in the future. The proposed work is as following. bouncing noise is much more than 10 fs.

3. The tracking algorithm can be replaced for faster locking time. This algorithm is design for low complexity. The main purpose is to make sure the DCO can be controlled. This work focus on wide-bandwidth and high-resolution. However, the tracking algorithm still has 30 cycles locking time in typical case.

4. To complete the measure is our next work. Building the testing PCB board and test fixtures are also big challenge. The measure uncertainty needs to be considered.

Bibliography

[1] Terng-Yin Hsu, chung-Cheng Wang, and Chen-Yi Lee, “Design and analysis of a Portable High-Speed Clock Generator,” IEEE Transactions on Circuit and Systems II:

Analog and Digital signal Processing, vol. 48, pp. 367-375, Apr. 2001.

[2] Yijoo Shin*, Taewon Kim, Sangwoo Kim, Sungkwon Jang, and Bokki Kim Department of Electronic Engineering, Kwangwoon University ‘A Low Phase Noise Fully Integrated CMOS LC VCO Using a Large Gate Length pMOS Current Source and Bias Filtering Technique for 5-GHz WLAN”.

[3] Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang, Yi-Chuan Liu, and Chen-Yi Lee “Design of a Wide-Band Frequency Synthesizer Based on TDC and DVC Techniques”.

[4] Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee “An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery Circuit”.

[5] Tomar, R. K. Pokharel, O. Nizhnik, H. Kanaya, and K. Yoshida “Design of 1.1 GHz Highly Linear Digitally-Controlled Ring Oscillator with Wide Tuning Range “.

[6] Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee “A Portable Digitally Controlled Oscillator Using Novel Varactors”.

[7] Chao Xu, Winslow Sargeant, Kenneth Laker, Jan Van der Spiegel “FULLY INTEGRATED CMOS PHASE-LOCKED LOOP WITH 30MHZ TO 2GHZ LOCKING RANGE AND f35PS JITTER”.

[8] Robert Bogdan Staszewaski, Poras T. Balsara “All-Digital Frequency Synthesizer in Deep-submicron CMOS.

[9] Wireless Lan Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE Std 802.11a, 1999.

Appendix A - Laker Tour

1. Type “laker” in terminal to start Laker.

2. Create a new

library and specify the library name.

3. Specify the technology file from library.

4. Create a new cell for layout

5. Start edit layout

6. After finish your design layout. Export it to gds format.

Appendix B - Abstract Tour

1. Type “abstract” in terminal to start abstract

2. Create a

new library

3. After create the new library, import LEF files from Cell Library.

4. There are two LEF files have to import. Those two files are provided from Cell Library.

In this example, one is “header9m126_V55.lef” the other is

“fsd0t_a_genracic_core.9m126.lef”

After import LEF files, there should be not any error message in log windows. And it means a user’s define library template has been created successfully.

5. Import gds file that you layout and export from Laker or other layout tools.

6. Specify layer map table

Next several steps are translate gds to LEF.

7. First, extract pin

In Boundary tab, please key in the layer name which is used in Laker for boundary.

There are some warning messages, those can be ignored. One of the important thing is check out if all the pins been created. In this example is “IN, OUT and RESET”.

8. Second, Extract.

Just press Run.

Normally, the Extract column in Cell window will show green tick.

9. Third step, Abstract

In this step, Site name must select to “core”.

Finally, the column abstract also become green tick.

Normally, there is no any error message in log windows otherwise go back to check where is the problem.

10. If those step have been done. Abstract can export LEF file we need.

Check log window if any error message.

11. There are some step need manual. Open the lef file that just export. Delete all the text line before “”

Close and save the new LEF file.

These are all the steps that used abstract translate GDS file to LEF file.