ed counterparts, digitally controlled ring oscil
3
All Digital Ring Oscillators
In contrast to their voltage controll
lators can be built of digital standard cells. Frequency control is obtained by changing the delay in the inverter loop. The operation principle is depicted in Figure 3.2.
Figure 3.2 All digital ring oscillator.
r consists of the propagation delays, rough the positive and negative edge in the ring. If the delay
The output period of the ring oscillato
th dringis assumed
of the ring oscillator is symmetric for both transitions, the frequency
1 ring 2
ring
f = d
This relationship is illustrated in Figure 3.3. The slop of the curve increases towards small ring delays. Even for very large rings with an oscillation frequency of 25 MHz, the slope at 25 MHz is approximately 1.25 kHz/ps or 50 ppm/ps. Applied to
a ring oscillator, this would require a delay resolution in the ring of 0.02 ps at 25MHz.
Digital delay generation with such a high accuracy is not realistic. In Chapter 4, a method for improving the frequency resolution of all digital ring oscillators is proposed.
Figure 3.3 Ring oscillator frequency vs. ring delay.
3.4 Analysis of the DCO Category
The heart of the ADPLL is a digitally controlled oscillator (DCO). Like most voltage-controlled oscillators, the DCO consists of a frequency-control mechanism within an oscillator block. Generally speaking, an odd number of inverters connected ome a ring oscillator. The clock period of the ring oscillator is two time of the inverter ferent clock period. Besides, a variable number of inverters implement a
the ring oscillator. One is the propagation delay time of an inverter and another is the any designs of the DCOs that have been presented.
in a loop chain bec
times the circular loop delay time. Different propagation delay produces dif
variable delay. Therefore, there are two parameters to determine the clock period of
number of the inverters. In terms of tuning these two parameters, there are m
Standard cell based DCO Design
Figure 3.4 shows a typical ring-oscillator which is very popular architecture in
most ADPLL designs. The main advantage is that the oscillator can be implemented by standard-cell library.
Figure 3.4 A typical ring-oscillator.
The modified architecture is shown in Figure 3.5 [18]. The enable signal powers the ring-oscillator. The path selection consists of tri-state inverters. The path selections from p1 to p4 are used to select different delay time of ring-oscillator to change output frequency. The problem of the architecture is a large parasitic capacitance at node 1 in Figure 3.5, and the DCO resolution is poor due to no fine tune cell being applied.
Figure 3.5 Modified architecture in [18].
An improved DCO architecture is showed in Figure 3.6 [14]. It is separated into two stages: a coarse-tuning stage and a fine-tuning stage. To avoid large loading capacitance appearing in the path selection output, the path selector is partitioned into two stages. In the first stage, sixteen coarse-tuning delay blocks select a partial output.
The second stage path selector will select the final output.
Figure 3.6 An improved DCO architecture in [14].
A cell-based digital controlled oscillator is shown in Figure 3..7[19]. It is a multiple path selection DCO with a delay matrix. When searching frequency, the path selection works as coarse search and the delay matrix works as fine search. The delay matrix consists of several parallel tri-state inverters. Its disadvantage is the large parasitic capacitance in the output node of the path selection.
Figure 3.7 Structure of the cell-based DCO in [19].
Another cell-based digital controlled oscillator is shown in Figure 3.8[20]. The oscillator being implemented is a seven-stage ring oscillator with one inverter replaced by a NAND gate for shutting down the ring oscillator during idle mode. To change the frequency of the ring oscillator, a set of 21 tri-state inverters are connected parallel to each inverter. When the tri-state inverters are enabled, additional current is added to drive each inverter stage. Although the DCO has the advantages of being made from all-standard cells, it has disadvantages such as relatively high power consumption and low maximum frequency from high capacitive load in the ring oscillator.
Figure 3.8 DCO using parallel tri-state inverters to adjust frequency in [20].
Delay cell DCO design
A DCO structure is showed in Figure 3.9(a) [12]. The ADPLL controls the DCO frequency through the DCO control word. Arithmetically incrementing or decrementing the DCO control word modulates the DCO frequency and phase. The magnitude of the incremental changes to the DCO control word defines the gain, which, in turn, dictates the relative change in DCO frequency（△F/△DCO control word）. As Figure 3.9(a) shows, the requisite odd number of inverting stages in the DCO is obtained by using one enabling NAND gate and eight controllable cells.
Figure 3.9(b) illustrates the basic premise of a constituent DCO cell. The sizing ratio ntrol devices is 2X to achieve binary weighted control. Hence, the DCO cell disadvantage is large area overhead.
of the co
can control the propagation delay time with n-bit control word. The the
Figure 3.9(a) 8-cell DCO with control bit [12].
Figure 3.9(b) Constituent DCO cell [12].
Another DCO structure is showed in Figure 3.10[16]. The DCO consists of four
he DCO cells work as the fine tune. The area of the DCO in Fi
paths and four DCO cells. The DCO cell is shown in Figure 3.9(b). The path selection works as the coarse search. T
gure 3.10 is smaller than the area of the DCO in Figure 3.9(a).
Figure 3.10 Structure of DCO in [16].
An improved DCO architecture is showed in Figure 3.11(a) [21].The DCO consists of coarse cell, fine cell, unit gain circuit and voltage divider. The DCO control word is the 8 binary weighted control signals. The weighted control signals DCO[4]~DCO[7] control the coarse cell and the others control the fine cell. The switch of the coarse cell is turned on by the Voltage_A and the switch of the fine cell is turned on by the Vdd voltage or Gnd voltage. By the two stage method, it can save
e area and power consumption. The coarse cell of the DCO was shown in the Figure _A becomes Vdd voltage or Gnd voltage.
th
3.11(b) . The fine cell is the same with coarse cell but the Voltage
Figure 3.11(a) An improved DCO architecture in [21].
Figure 3.11(a) The coarse cell of the DCO in [21].
3
Existent clock generation methods have been explained and the performance has been compared to the requirements mentioned above. Table 3.1 lists the characteristics of conventional clock generation circuits. In the next chapter, a new clock generation methods are proposed.
Table 3.1 Characteristics of various clock generation circuits.
Clock