The proposed ZCD is illustrated in Fig. 23(a) to control the switching frequency in the SCG circuit. The transistors M1-M3 and M4-M6 construct the level shifters to shift the signals VX and Vout to the VX1 and Vout1, respectively, to meet the input common-mode range of the comparator. In the first interval of each switching period, the INP is logic high to keep the Pg
high and reset the D-flip-flop to pull the ZC low. In the second interval of each switching period, the INP is triggered to logic low to turn on the power PMOSFET if the signal ZC is still low. Once the reverse inductor current occurs, VX is smaller than Vout corresponding to VX1 is smaller than Vout1. Simultaneously, the output of the comparator is triggered from low to high to set the signal ZC high to indicate the zero current condition. The signal Pg is changed from low to high to turn off the power PMOSFET and avoid the occurrence of the reverse inductor current.
37
(a)
(b)
Fig. 23. (a) The proposed ZCD circuit. (b) The timing diagram.
38
Chapter 5
Whole chip experimental Results
The proposed boost convert with the CSC technique was fabricated by TSMC 0.25 μm CMOS process. The threshold voltages of nMOSFET and pMOSFET are 0.477 V and -0.596 V, respectively. The off-chip inductor and output capacitor are 1 μH and 6.8 μF, respectively.
The output voltage Vo is 4.5V. The specification is listed in Table IV. The chip micrograph is shown in Fig. 24 and the chip area is about 1564 μm × 1813 μm including the test pads.
Test buffer
Fig. 25 shows the output waveforms at different load current condition when the converter operates at the CCM mode and DCM mode. Fig. 25(a) and (b) show that the proposed CSC technique adjusts the switching frequency of the boost converter dynamically according to the load current condition. Fig. 25(c) shows the switching frequency maintain 1.7MHz to enhance
39
system performance when inductor current enter into CCM mode. The relationship between load current, switching frequency and output ripple is listed in Table V. It demonstrates that the switching frequency with different load is almost the same at CCM mode. On the other hand, the switching frequency reduces with the load current decrease at DCM mode.
Fig. 26 demonstrates the waveform at the transition point. It is seamless between PFM and PWM mode, and the overshoot which ordinary pfm mode will occur is also reduced
The waveforms of the output voltage and the inductor current during load transient response are shown in Fig. 27. The settling times are about 26µs and 27µs for Vin = 2.7V and the change in load current from 200mA to 400mA and from 400mA to 200mA, respectively. It demonstrates the CCM mode operation.
Fig. 28 shows the simulation efficiency of proposed structure. The switching frequency of the boost converter can be effectively reduced at light load. As a result, the efficiency can be kept larger than 90% at load current= 10mA. It demonstrates that the efficiency can be kept high due to the implementation the technique.
Table IV.THEDESIGNSPECIFICATION
SPECIFICATIONS
loading current 400mA
Inductor ( L ) 1μH
Output capacitor ( CO ) 6.8μF
40
Equilibrium series resistance of the
output capacitor (RESR) 50mΩ
Operation temperature 0~100℃
PFM range 0mA - 150mA
(a)
41
(b)
I
LV
outf
sw=1.67MHz
∆V
out=46mV
∆I
L=660mA
(c)
Fig. 1. Waveforms in conventional boost converter with hysteresis control when load current changes from 70mA to 270mA within 2μs.
42
Fig. 252. Transition state waveform.
43
(a)
V
OUTI
L80mV
27usec
200mA 400mA
(b)
Fig. 26. Waveforms in the proposed boost converter with the CSC technique (a) when load current changes from 200mA to 400mA within 2μs and (b) when load current changes from 400mA to 200mA within 2μs.
Table V. COMPARED WAVEFORMS
IL fs Vout ripple
4mA 55kHz 34mV
6mA 71kHz 31mV
8mA 97kHz 30mV
10mA 114kHz 31mV
20mA 234kHz 30mV
44
40mA 460kHz 31mV
60mA 714kHz 32mV
80mA 909kHz 31mV
100mA 1.16KHz 34mV
200mA 1.66MHz 37mV
300mA 1.67MHz 46mV
400mA 1.7MHz 50mV
Fig. 27. Power conversion efficiency.
45
Chapter 6 Conclusion
The proposed CSC technique in boost converters can speed up transient response due to the current-mode hysteresis control and improve efficiency over a wide load range. The CSC technique behaves high accuracy similar to the current-mode control without the need of slope compensation for simplicity. The load-dependent switching frequency at light loads results in high power conversion efficiency. Experimental results show that the output voltage ripple can be kept smaller than 50mV over a wide load current range from 0mA to 400mA with power conversion efficiency higher than 90% at load current of 10mA.
6.1 Future Work
The CSC technique also minimizes the external components and thus it has the advantage of small footprint. But the CSC has the same disadvantage of the complex design the EMI filters because of the frequency variation along with the input supply and output voltage. Therefore, the improvement of EMI issue is important in the future.
46
Reference
[1] D. Maksimovic, “Power management model and implementation of power management ICs for next generation wireless applications,” Tutorial presented at the International Conference on Circuits and System (ISCAS), 2002.
[2] ‘‘Technical Review of Low Dropout Voltage Regulator Operation and Performance,”
Texas Instruments Incorporated, Dallas, TX, Aug. 1999.
[3] P. Favrat, P. Deval and M. J. Declercq, ‘‘A high-efficiency CMOS voltage double,”
IEEE Journal of Solid-State Circuits, vol. 33, pp. 410-416, March 1998.
[4] James S. Zeng, Lajos Burgyan, and Rendon A. Hollowa, ‘‘Highly efficient step-down/step-up and step-up/step-down charge pump,” United States Patent, Patent Number 6,657,875, July 16, 2002.
[5] Robert W. Erickson and Dragan Maksimovic, Fundamentals of Power Electronics, 2nd ed., Norwell, MA: Kluwer Academic Publishers, 2001.
[6] G. Jurasek, G. Levin, P. Sisson, and S. Repplinger, “High Efficiency Automotive Power Supply with Hysteretic Current Mode Controller,” in Proceedings of IEEE Applied Power Electronics Conference and Exposition, vol. 2, pp. 861, March 1996.
[7] Wei Tang, Fred C. Lee, “Small-Signal Modeling of Average Current-Mode Control,”
IEEE Trans. Power Electron., vol. 8, pp. 112-119, Apr. 1993.
[8] R. B. Ridley, “A new, continuous-time model for current-mode control,” IEEE Trans.
Power Electron., vol. 6, pp. 271-280, April 1991.
[9] J. H. Park and B. H. Cho, ”Small Signal Modeling of Hysteretic Current Mode Control Using the PWM Switch Model,” IEEE COMPEL, pp. 225-230, July 2006.
[10] K.D.T. Ngo, S. K. Mishra, and M. Walters, “Synthetic ripple modulator for synchronous buck converter,” IEEE PE Letter, vol. 3, pp.148-151, Dec. 2005.
47
[11] B. Razavi, Design of Analog CMOS Integrated Circuits. Boston, MA：McGraw-Hill, 2001.
[12] Hong-Wei Huang, Wei-Lun Hsieh, and Ke-Horng Chen, “Programmable voltage-to-current converter with linear voltage control resistor,” IEEE International Symposium on Circuits and Systems,2008.