Thermal noise (Switch circuits)

OSR

P_jitt = ⁱⁿ2 ⁱ 3.2）

We consider th

) A f 2

( π 2 σjit²

⋅ ⋅

⋅ （

e worst case in this work. That and are replaced by and

1 in Fig. 3.1, ecause we have modeled them as input-referred noise in the integrator input.

fin A_in f_B

Vref respectively.

Before discussing power consumption modeling, we summarize the nonideality modeling as follows. The leakage noise due to finite OTA gain can be considered as an additional quantization noise, so the total quantization noise will be higher than theoretical quantization noise, appearing at D2 in Fig. 4.9. All other nonidealities are modeled at D

b

− −

ΣΔ

Fig. 3.1 Main nonidealities sources in the modulator

3.2 Thermal noise (Switch circuits)

There are three thermal noise sources in the ΣΔ modulator, in MOS switches, OTAs and reference voltage. We will analyze them separately as follows. For a fully differential implementation, the in band switch thermal noise during the sampling phase results in output noise power [36]

_⎟⎟

⎜⎜ ⎠

⋅⎝

=

S

1 OS C

P_sw （3.3）

where

⎞

⎛ 4kT 1

R

k is Boltzman constant and T is the absolute temperature. Additional thermal noise is introduced by the switches during the integration phase, resulting in the output noise

power [34]

Since the thermal noise voltages introduced during these two phases are uncorr

⎜⎜ ⎞

⋅⎛

≅ 1 4kT

P （3.4）

elated, the total output switches thermal noise power from the switched capacitor integrator is

_⎟⎟

alf of is from the input branch, and the other half is from the DAC branch.

3.3

modulator with finite OTA gain , the modified quantization noise is expressed as [36]:

Psw

H

Finite OTA Gain Error

Finite OTA Gain is an important error when we analyze a real integrator. Typical value of OTA gain is about 50 ~ 80 dB in modern CMOS technology. For a general single-loop nth

order ΣΔ A₀ where P_Q is the original quantization noise, and

P +

=

Δ is the quantizer step size. The P_AV in（3.6）is due to finite OTA gain, and can be considered as an addi e quantization noise power. It can be verified using （3.6）that, for a single-loop topology, A = 50 dB is s

tiv

uff the sense that a higher would not significantly reduce

icient

.) (mod .

to avoid SNR degrades, in A ₀ P_Q

3.4 Multi-bit DAC noise

There are several advantages in using a multi-bit structure. One is that when the quantization step Δ decreases, quantization and settling noise reduce. Another is that a multi-bit structure improves stability and provides a higher overload level and more aggressive noise shaping function. However, due to CMOS process variations, there can be mismatches in the 2 unit capacitors ^B C of a B-bit DAC shown in Fig. 4.4. Assume that _u each unit capacitor distribution is Gaussian [37] around a nominal value. Let the normalized capacitance be

where e capacitance of the th unit capacitor. Define the deviation of as , where

Then voltage error caused by unit capacitor mismatches is given by [34]

（3.9）

repre de

s an additive Gaussian noise in the modulator feedback path, the variance of which is

where x(k sents the number of 1’s in the feedback thermometer co at the time step k. The e_dac(k) can be treated a white, the average DAC noise power at the modulator output becomes

2 2

ref 2 1 V

cap B

Pdac = ⋅ ⋅ ⋅σ （3.11）

Apparently the dominating factor is B, since P increases exponentially with respect to B. In order to reduce DAC error due to unit capacitor mismatch, several techniques have been proposed. The most efficient among these is the Data Weighted Averaging (DWA) [33], and it is shown in [38] that the DWA effect is a first-order noise shaping of the DAC noise. If the

OSR

DWA is employed, the average DAC nois

dac

e power at the modulator output is modified to be

3 2 2

2 ref 2 V ) (DWA

P_dac ≅ ⋅ ^B⋅σ ⋅ π （3.12）

Equations（3.11）

3 OSR

cap ⋅

and（3.12）will be used to estimate the DAC noise power in the ptimization process.

3.5 Settling noise

ge. So we only consider about settling noise in this p

which takes into account the time-domain distribution of SC integrator input Vs(n) described o

The settling error will produce settling noise and settling distortion, but settling distortion produced in large nonlinearity, the input signal settling in partial slewing about 50%. As mentioned above, the settling noise will vary lar

aper.

In this section, the settling noise model [39] is a mathematical model what has no need to run behavior simulation. Settling noise is produced by non-idealities in OTA what causes nonlinear transfer characteristics. This nonlinearity is approximated by a nonlinear fitting

in Fig. 4. The variance of Vs(n) in second-orderΣΔis 2^B[39], but it is not exact enough to use. Because in different parametersV_ref 0.5 FS

ref VS =1.4⋅V σ

⋅

= (Full Scale)、A_in、B and different stage of

ΣΔ

, the variance will be change. In part I. there needs to find a variance equation from the parameters mentioned above.

3.5

A typical time domain histogram distribution of vs(n) is shown in Fig. 3.2.

.1 Variance equation of V

S

-0.80 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

Fig. 3.2 Histogram distribution of Vs(n).

The result is close to a Gaussian distribution. Therefore, we assume V_S is Gaussian distributed with a ze e simulations suggest that the relation between

B LSB

VS ∝V =

σ FS 2 (Quantizer step size), and we suppose

ref We can use behavior simulation to find matrix function in (3.14) and using least-square solution to approximate P_α(B)andP_β(B)in each B.

)

are not the same. It has to calculate coefficients of

s than 6 in optimization module, the

and are E 3 .

Assume that the quantizer bit number is les

⎥

TABLE 3.1 Coefficient of polynomial

er of integration phase

errors are well known [40, 41]. The settling error during the sam ing

3.5.2 Settling noise pow

The settling error only consider of the error in integration phase, because

2⋅τ₁

2 1 <<τ

τ . Then

that occurs in linear settling will large than

minimum ε₂ ε₁.

Fig. 3.3 Three types of settling conditions in integration phase

The settling error ε₂ during the integration phase can be divided into three cases:

Linear settling: The parameter SR is the slew rate of OT is a constant produced by ch t, and

being the equivalent gain bandwidth in the integration phase.

There are three settling conditions depending on the absolu

2

te value of VS. The full slewing case is not considered here because it is not significant. From (3.17) and (3.18) it can be verified that VS at end of each integration interval can be written as

⎪⎩

From (16), the settling error of integration phase can be expressed as:

⎪⎩

To analyze the effect of the nonlinear error (3.21), it is approximated by the polynomial.

(3.22)

Then, least square method is applied and a cost function is defined to be

[ ]

_{S S}

W

)

is a Gaussian weighting function. With the method above, the coefficients in (3.23) for C to be minimum can be found to be

usingV_s

( )

f . The power spectral density of vs(n) is expressed as Then the expected value of the height of PSD of settling noise of integration phase can be defined as

{ ^{h ( f )} }

₁

^E { } ^h

_{e1 3}

^E { } ^h

_{e3 5}

^E { } ^h

_e5

E = α + α + α

(3.28)

3.5.3 Dependence with settling noise and quantization noise

The mathematical settling noise model produce by quantization noise model, so it might be calculated the quantization noise reduplicative. In (3.28), we can know that the settling noise is a linear combination of vectors 、 and . The settling noise and quantization noise signal will mixed together in (3.29), so power spectral density of each of them in (3.31)

is including 、 、

Assume that and isn’t equal to zero, the total noise power in (3.30) of settling noise and quantization noise is the sum of noise in baseband.

(jw)

The quantization noise is , so the settling noise power is not only the settling noise in baseband, it must addition the dependent parts

( )

^{j df}

(

^jω

S_SQ

P

_set

)

QS

in baseband in (3.31).

( ) ^{f S} ( ) ^{f S} ( ) ^{f df}

S

_{QS SQ}

f

0 S

B

+ +

= ∫

(3.31) The dependent partS ( )f is equal to ^SSQ( )^f complex conjugate in (3.32).

( ) ^f ( ^S

SQ

( ) ^f ) ^{* h}

e

^{( ) ( ) f ( h f ) *}

S

_QS

= = ⋅

(3.32) When quantization noise and settling noise are independent, the settling noise isS_S( )f . The other noise (Finite OTA leakage noise) 、 (Switch thermal noise) 、 ( Multi-bit DAC noise) and (Jitter noise) are white gaussian noise. We assume that the noises power are independence of each other, because each of than produced by difference source and did not influenced with other noises. So the noises power 、P 、P and could be added.

PAV P_sw

Pdac P_jitter

AV sw dac jitt

P P

4.

Models of Sigma-Delta Modulator Power Consumption

In order to estimate the power dissipation of ΣΔ modulator, we drive the power dissipation equation of the circuit. Our goal is effective to estimate the absolute value of the power because the relative power estimate model [42] in (4.1) was a disadvantage when designer realize circuit. Typically, ΣΔ ADC power consumption is categorized into static and dynamic parts.

Ceq

GBW

~

P ⋅ (4.1) The static power is created by static current and dynamic power is created by carrier charge and discharge of capacitors. Why we add the dynamic part, but the power model in (4.1) only consider with the static part. Because when the quantizer bit number increase, the static power will decrease and the dynamic power will increase in TABLE 4.1. So the dynamic power can’t always be neglected.

B

B 1 2

GBW (MHz) 65 31

SR (V/us) 272.271 129.852

C (pF) S 2 2

Static power (mW) 19.84 9.83 Dynamic power (mW) 2.14 3.31

Psw (dB) -110.414 -110.414

Pset ^(dB) -97.8094 -97.809

TABLE 4.1 power dissipation between Static part and Dynamic part in different bit

4.1 Static Power Consumption

The static power dissipation in a ^ΣΔ modulator is mainly from OTA and comparator. In this section, the supply current of OTA and comparator is a constant value. But it has no use in our

optimization model. How to link up the relationship between power model and system parameters is important.

4.1.1 OTA power model

Building the power consumption model of OAT is very a complex topic, because the integrator depends on five system parameters( 、 、 、 and ). The power consumption in (4.2) is easily to understand, but the parameter in (4.2) must be transformed into system parameter.

k_∑Δ A₀ C_S GBW SR

DD BASE OTA Δ

DD OTA Δ

OTA k I V k K I V

POW = _∑ ⋅ ⋅ = _∑ ⋅ ⋅ ⋅ (4.2) In (4.2), is the total number of current branches of OTA and is the OTA base current. The parameter depends on the architecture of OTA. When DC gain increase, the OTA must cascade more stage in Fig. 4.1 and will increased with DC gain in (4.3), because the eased with total stage number

KOTA I_BASE

. KOTA

will incr

A0

KOTA

A0 N_stage

Fig. 4.1 Structure of OTA

( )

(

^{1 N}stage ^{1 '}

)

OTA OTA

OTA N K

K = ⋅ + − ⋅ (4.3) The parameter in Fig. 4.1 is the ratio value of current branches and is the ratio between bias circuit and current mirror of OTA., suppose the currents are equal in stages and is less than or equal to 2, will be decided by system

OTA' K

K

NOTA

stage

N

~

2 _OTA' K_OTA'

parameter SR and GBW in (4.4).

If all transistor width will increase when the base current increases, we suppose that the trans-conductance parameter then trans-conductance of each stage is loop equivalent capacitive load in (4.8).

IBASE C_eq C_eq

The parameters ζ₀ and ζ₁ will changed when using different amplifier in first stage or first two stages. The parameter values of ^ξ0 and ^ξ1 by some amplifiers in TABLE 4.2.

ξ0 ξ₁

Folded-Cascode amplifier 0 2

Telescope amplifier 1 1

Two-Stage amplifier 0 1

TABLE 4.2 Value of ζ₀ and ζ₁ in different amplifier

In Fig. 4.2 shows the power dissipation of the actual OTA and OTA power model with consider parasitic capacitors and without consider parasitic capacitors, the parasitic capacitors in (4.8) is . In fact the parasitic capacitors could not be estimated before the OTA designed, we can only suppose the value of before designed. The actual OTA GBW is influenced by parasitic capacitors, so the GBW can’t rise unlimited. The actual OTAGBW must limits by dominant pole. Fig. 4.2 shows that the differences of power between actual OTA and OTA power model with consider parasitic capacitors are not large at low frequencies.

' N_{OTA L}

L C

C = ⋅

L' C

Fig. 4.2 Simulation of OTA power model

4.1.2 Comparator power model

The comparator power model shown in (4.9) is only depends on bit number, the supply current of comparator can not be calculated by system parameters. So it should be design a comparator before optimization simulation.

Icomp

DD comp

comp I V

POW =2^B⋅ ⋅ (4.9) In (4.9), comparator power in quantizer is only a function with system parameter , the parameter must decide by designer.

B

Icomp

The first integrator is the most important in terms of noise. Hence, all succeeding integrators are normally scaled down progressively to reduce the power consumption and die area. Consider that the sum of the relative scaling factors used in all the integrators of the modulator is . Then the static power consumption equals , where is proportional to the order of the

ΣΔ k_ΣΔ kΣΔ⋅POW_OTA kΣΔ

n ΣΔ modulator. From (4.2) and (4.10), the total static power consumption is:

comp OTA

static

POW POW

POW = +

(

comp

)

DD

B BASE OTA

ΣΔ

K I 2 I V

k ⋅ ⋅ + ⋅ ⋅

=

(4.10)

Since the static power consumption relates tok_ΣΔ、

B

、 、 、

、

AV C _eq SR and they are important system parameters t determined in the design flow.

GBW

4.2 Dynamic Power Consumption

In this section, we discuss dynamic power consumption. Dynamic power includes switch power DAC power and digital power. All of them depend on dynamic signal

and capacitor of each other.

OSR f

2 f_s = ⋅ _B⋅

4.2.1 Switch power model

The CMOS switch is shown in Fig. 4.3, assume that the number of CMOS transmission gate in Sigma-Delta Modulator is . The in (4.11) is the total power dissipation of switch circuits.

Switch

N PWO_Sw

2 DD s Switch Switch

SW N C f V

POW = ⋅ ⋅ ⋅ (4.11)

Fig. 4.3 CMOS transmission gate

When the switches turn on or turn off, it must charge and discharge carriers to the gate of CMOS switch. Those carriers loss accumulate a huge power dissipation of sigma-delta. So it must be estimated in our power model. It is easily to calculate capacitor of each switch gate in (4.12).

Switch

C

PMOS NMOS

Switch C C

C = +

( ^{W W} ) ^C

_OX

L ⋅ + ⋅

=

_{min P N} (4.12)

But our power must link the relationship system parameters and power dissipation, unfortunately is not the system parameter, it has no use in optimization model. But it can be transform to system parameter in (4.13) (4.14) (4.15).

Switch

C

Switch

R

⎟⎠ of CMOS transmission gate is the parallel resistance with and .

RP

Form (4.11) the total capacitor 1 ⎟⋅C_NMOS

⎠

proportional to the switch-on resistance [43] in (4.16).

Switch

Parameter is the number of total switches, so we define the relative switch power as

4.2.2 DAC power model

DAC power is the total carrier loss in feedback loops, the unit feedback capacitor will

be charged in sampling phase and those carriers on will be discharged in integration phase.

Cu

Cu

Fig. 4.4 Sampling phase Fig. 4.5 Integration phase

We estimate the power consumption of multi-bit DAC in the multi-bit sigma-delta converter. The multi-bit DAC is shown in Fig. 4.4 and Fig. 4.5. It is composed of switches and unit feedback capacitors. At first, we consider charge and discharge for a unit feedback capacitor in sampling phase and integration phase. Assume that the periods of charge and discharge both are

T2, the average current of unit feedback capacitor and power consumption of a unit capacitor in (4.18)(4.19).

C = in (4.20). The parameter N_DAC in signal ended sigma-delta modulator

is , but our model is fully differential sigma-delta modulator, the value of must

be double . The DAC Power is not depends on , because

in (4.19).

Digital power in (4.21) is including clock generator circuit power, dynamic element matching circuit power and the logic circuit power in quantizer. In this paper, we use CMOS logic to design the logic circuit. Parameter is total number of logic gate when the quantizer is only 1 bit and the parasitic capacitor is the average capacitor of total logic gates. In this section the parasitic capacitors could not be transfer to system parameters. So the digital circuit must design before optimization simulation.

Ngate

C_gate

Considering a CMOS inverter with the load capacitor are shown in Fig. 4.6, the capacitor ly the channel capacitor in MOSFET. The length to width ratio of and is

Fig. 4.6 CMOS logic inverter

Giving a periodic square-waveΦ to inverter input node. When changed from high level voltage to low level voltage at

Φ 0

t= , the charge and discharge. The total carrier in (4.23)

CPMOS C_NMOS

L

QH_→

(

PMOS NMOS

)

DD L

H V C C

Q _→ = ⋅ + (4.23)

In reverse case Φ changed from low level voltage to high level voltage att=T2_{, the} discharge and charge. The power dissipation in (4.24)

CPMOS C_NMOS Q_L→H

(

PMOS NMOS

)

DD H

L V C C

Q _→ = ⋅ + (4.24)

The average current in 1 clock cycle of this inverter could be calculated in (4.25), we can find the power dissipation of this inverter in (4.26).

Iavg

(

_{H L L H}

)

avg Q Q

T

I = 1⋅ _→ + _→

(

_{PMOS NMOS}

DD C C

T V

2⋅ ⋅ +

=

)

(4.25)

(

_{PMOS NMOS}

)

_{S DD}²

DD avg

INV I V 2 C C f V

P = ⋅ = ⋅ + ⋅ ⋅ (4.26)

From (4.26), the load capacitorC_gate =2⋅

(

C_PMOS+C_NMOS

)

Cgate

, assumed that is the

average of each logic gate capacitor and of all logic gates are the same, the digital circuit power could be calculated in (4.21)

Cgate

OSR f

2 V C N

POW_digital =2^B⋅ _gate⋅ _gate⋅ _DD²⋅ ⋅ _B⋅ (4.21)

In TABLE 4.3 is the relationship between total power models and system parameters, when the power depend on less parameter like and . So those power models

both needed to design circuit to get the parameters 、 and before optimization.

POWcomp POW_digital

Ngate C_gate I_comp

POWOTA POW_comp POW_SW POW_DAC POW_digital

OSR - -

f B - -

C S - - -

Switch

R - - - -

B - -

GBW - - - -

SR - - - -

A 0 - - - -

Δ

k∑ - -

FS - - - -

TABLE 4.3 Relationship between power models and system parameters

5.

Design Optimization of Sigma-Delta ADCs Design

Fig. 5.1 Flow of the proposed optimization for the ΣΔ modulator Model-based design

In section VI, we propose a design optimization flow to help designers reach an optimal design quickly as Fig. 5.1. The input signal bandwidth (Hz) and the output signal SNDR (dB) are treated as design specifications. We modify the figure-of-merit (FOM) [44] function by multiplying a variable K to the SNDR term of FOM and inverse it, to become our Cost Function. In Fig. 1 the Cost Function is expressed by

1

log 10

−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ ⎟⎟⎠

⎜⎜ ⎞

⎝ + ⎛

⋅

=

total B

dB POWER

SNDR f K

CF (5.1)

SNDR is defined as (5.1). Where and are sum of all major noises and distortions in SDM listed in TABLE I.

noise

total _ total _distortion

P P

PQ Quantization noise

PAV Finite OTA leakage noise

Pjitt Jitter noise

Pset Settling noise

Psw Switch thermal noise

POTA OTA thermal noise

Pdac Multi-bit DAC noise

NFDCG

HD3 third harmonic distortion of Nonlinear Finite-DC-Gain

NFDCG

HD5 fifth harmonic distortion of Nonlinear Finite-DC-Gain

HD2DAC second harmonic distortion of of Nonlinear Capacitance

HD3DAC third harmonic distortion of of Nonlinear Capacitance

HD4DAC fourth harmonic distortion of of Nonlinear Capacitance

TABLE 5.2 The representation of each noise in our models

The constant K serves as the relative weighting between SNDR and . Typically, if we prefer high resolution designs, we set K higher and SNDR plays a more important role than . On the other hand, if we prefer low power designs, we can set K lower.

parameters of

total

POWER

total

POWER

σcap, V_ref and some circuit device dimensions parameter (ex: μ_n, , etc ) depend on the technology, so they are set before the design optimization.

Cox

6.

Conclusions and Future Works

In order to increase the speed and low power of circuit design for ADCs, this paper offers an efficient optimization method. The power estimation is presented for sigma-delta converter with a certain accuracy and bandwidth specification. The power consumptions model offers designer to find the dominant power dissipation part and how to reduce it.. Our proposed method has acceptable accuracy and nice speed, and the flexibility can be enhanced by building more nonlinearity models for different circuit structures.

ΣΔ

Further, in order to estimation the noises power, it must consider the noise power dependency issue. In this paper only consider the dependency problem between setting noise and quantization noise. The power has a slight disadvantage that the digital power and comparator power must design before optimization.

References

[1] Shahriar Rab, “A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS,” IEEE J. Solid-State Circuit, vol. 32, NO. 6,Jun. 1997

[2] Mohamed Dessouky and Andreas Kaiser, “Very low-voltage digital-audio ΔΣ modulator with 88-dBdynamic range using local switch bootstrapping,” IEEE J. Solid-State Circuit, vol. 36, NO. 3, Ma.

2001

[3] Noura Ben Ameur, “Design of Efficient Digital Interpolation Filters and Sigma-Delta Modulator for Audio DAC,” International Conference on Design & Technology of Integrated Systems in Nanoscale Era. 2008 [4] Min Gyu Kim, “A 0.9 V 92 dB Double-Sampled Switched-RCDelta-Sigma Audio ADC,” IEEE J.

Solid-State Circuit, vol. 43, NO. 5, May. 2008

[5] Hsin-Liang Chen, Yi-Sheng Lee, and Jen-Shiun Chiang, “Low Power Sigma Delta Modulator with Dynamic Biasing for Audio Applications,” IEEE J. Solid-State Circuit, vol. 43, NO. 5,May. 2007

[6] Mohammad Ranjbar G.Roientan Lahiji Omid Oliaei. “A Low Power Third Order Delta-Sigma Modulator For Digital Audio Applications,” IEEE J. Solid-State Circuit, ISCAS 2006

[6] Mohammad Ranjbar G.Roientan Lahiji Omid Oliaei. “A Low Power Third Order Delta-Sigma Modulator For Digital Audio Applications,” IEEE J. Solid-State Circuit, ISCAS 2006

在文檔中 功率消耗模型及模組設計最佳化運用在積分三角類比數位轉換器 (頁 36-0)