Chapter 1 Introduction
1.3 Thesis Organization
In this thesis, NW-TFTs originally proposed by Advanced Device Technology Laboratory (ADTL), NCTU were adopted [33]. Both SPC and MILC techniques were utilized
to crystallize the a-Si channels. Without using expensive lithography equipments, TFTs with nano-scale channels can be prepared. Besides, this approach is compatible with modern semiconductor processing.
The overview of LTPS-TFTs and NWs is described in Chapter 1. In Chapter 2, we briefly explain the device structure and the process flow. In Chapter 3, we discuss the effect of an additional deep ion implantation (I/I) on the off-state leakage of the SPC NW-TFTs. In Chapter 4, the MILC NW-TFTs with different MILC open window arrangements and annealing temperatures were investigated. Finally, we summarize the conclusions and the suggested future work in Chapter 5.
Chapter 2
Device Fabrication and Measurement
2.1 Device Structure and Process Flow
6-inch (100)-Si wafers capped with 100 nm wet oxide were used as the starting substrates, followed by the definition of a 100 nm in-situ-doped n+ poly-Si as gate electrode.
After RCA clean, 38 nm TEOS and 100 nm a-Si were grown by LPCVD system sequentially.
To reduce the S/D resistance, all wafers received a P31+ implant with a dose of 1x1015 cm-2 and a low implant energy of 15 keV. Wafers were then divided into two splits according to the crystallization method.
(1) SPC NW-TFTs
One of the splits was fabricated by SPC. Based on I/I condition, wafers were also classified into two splits. One split of wafers further received an additional P31+ implant with a dose of 3x1013 cm-2 at 40 keV, while the other split was skipped from receiving this extra implant. The purpose of the deep I/I is to increase the dopant concentration in the drain region near the gate oxide. Subsequently, S/D regions were defined by photolithography, and then etched by reactive ion etching (RIE), during which the NW channels abutting the sidewall of the gate were formed simultaneously. Wafers were then covered with a 300 nm low temperature oxide (LTO) as passivation layer. To transform the a-Si channels into polycrystalline state, SPC was performed in a N2 ambient at 600 for 24 hr. After standard ℃ metallization, wafers were sintered in forming gas at 400 for 30 min. Fig. 2℃ -1 illustrates the device structure of the NW-TFT (a) without and (b) with deep I/I, with labels of the
projected range of the implant (the dashed line) in the S/D regions as determined by the implant energy.
(2) MILC NW-TFTs
The other split was fabricated by MILC. Briefly, after S/D implantation, NW channels were defined by RIE etching. Wafers were then covered with a 100 nm LTO as Ni barrier layer. MILC open windows were defined by photolithography, and then etched by 50:1 HF for 4 min. Subsequently, 5 nm Ni was sputtered onto the wafers by physical vapor deposition (PVD) system. To transform the a-Si channels into polycrystalline state, MILC was performed in a N2 ambient at 525 ℃ or 550 for 21 hr. The unreacted Ni was removed by H℃ 2SO4/H2O2
solution at 120 for 10 min, followed by 200 nm LTO as passivation layer. An additi℃ onal annealing step in a N2 ambient at 600 for 6 hr ℃ was adopted to ensure the activation of the dopants in the S/D regions. After standard metallization, wafers were sintered in forming gas at 400 for 30 min. Fig. 2℃ -2 illustrates the (a) bird’s view and (b) top view of the NW-TFT with asymmetric MILC open window at the source terminal. Note that a parameter called offset, OS, is defined as the shortest horizontal distance between the MILC open window and the channel. In this study, OS was split into 0.5, 1.5, 2.5, 4 and 5.5 μm.
In this experiment, the NW channels, like the spacers in the MOSFETs, are formed by RIE system. The feature size is determined by several factors, such as gate height, a-Si thickness and over-etching time. Two important parameters called channel width and thickness are 50 nm and 55 nm, respectively, as the transmission electron microscopy (TEM) image shown in Fig. 2-3.
2.2 Measurement Setup and Electrical Characterization
HP 4156A Semiconductor Parameter Analyzer was employed to perform the electrical characterizations of the NW-TFTs. During all measurements, the temperature was controlled
at a stable value by temperature-regulated hot chuck.
From the measured ID-VG curve at VD = 0.5 V, the parameters of the NW-TFTs including threshold voltage (Vth), subthreshold swing (SS), field-effect mobility (μFE) can be extracted according to their definition.
Here, the threshold voltage (Vth), calculated by the constant current method, is defined as the gate voltage (VG) needed to achieve a drain current (ID) of (W/L)×100 nA, i.e.
where W and L are the channel width and length, respectively.
The subthreshold swing (SS) can be calculated from the subthreshold current in the weak inversion region by
Finally, the field-effect mobility (μFE) is determined by
D
where gm is the maximum transconductance and Cox is the gate oxide capacitance per unit area.
Chapter 3
NW-TFTs Fabricated by SPC
3.1 Fundamental Characteristics of SPC NW-TFTs
The operational principles of the novel NW-TFTs are similar to those of the conventional TFTs. The n+ ploy-Si side-gate is used to modulate the channel potential, thus controlling the switching behavior of the device. The transfer and output characteristics of SPC NW-TFTs are shown in Figs. 3-1(a) and (b), respectively. Fig. 3-1(a) reveals that good device performance with high on/off current ratio (6.23×105) and reasonable subthreshold swing (0.83 V/dec) is achieved. Since the cross-sectional area of the NW channel is quite small, low leakage current was originally expected. However, the off-state current is anomalous high and depends on both the gate and drain bias. The leakage mechanism will be carefully examined and analyzed in the following sections. In Fig. 3-1(b), a kink effect is observed. Under high electric field region, the grain barrier heights for both sides of the grain boundary become asymmetric and the grain barrier height near the source side will be lower than that near the drain side. There will be extra carriers injecting from the source through the side with lower grain barrier into the channel. This phenomenon is so called the drain-induced grain barrier lowering (DIGBL) effect [34] [35]. Furthermore, the impact ionization mechanism initiated by the DIGBL current may cause an anomalous current increase in the saturation region.
3.2 Leakage Mechanisms
In poly-Si channels, the band diagram modulated by the drain and gate bias would affect
the off-state characteristics of the devices. Fig. 3-2 illustrates two possible regions for leakage generation in our novel NW-TFTs. One occurs in the drain/channel junction, and the other occurs in the gate-to-drain overlap region. Detail mechanisms would be briefly discussed as followed.
3.2.1 Drain/Channel Junction
This mechanism occurs laterally from the channel to the drain via trap-assisted conduction and is strongly dependent on the magnitude of the drain bias. According to the electrical field strength at drain/channel junction, there are generally three cases as illustrated in Figs. 3-3(a), (b) and (c):
(a) Under low electric field regime: Electrons are thermally excited from valence band into midgap states located at the grain boundaries (GBs), and then the trapped electrons are emitted to the conduction band in the same way, i.e., the so called “pure thermal emission” or “thermal generation”.
(b) Under medium electric field regime: Since the increasing drain bias pulls the energy band at the drain terminal down, the thermally excited electrons from the valence band to trap states can tunnel to the conduction band through the reduced barrier width. This is known as the thermionic field emission.
(c) Under high electric field regime: While the band-bending is pulled more severely, the electrons can easily tunnel from the valence band to the conduction band with the aid of the trap states. This is called field emission or tunneling.
In poly-Si channel, the presence of the trap states in the band gap plays an important role on the leakage current. The thermal emission current is proportional to the intrinsic carrier concentration of silicon (ni), which is proportional to exp[-Eg/2kT] (where Eg is the energy band gap of silicon, k is the Boltzmann constant, and T is the temperature in Kelvin) [36]. For
this reason, the activation energy of the pure thermal emission current should be approximately equal to Eg/2. In addition, the pure thermal generation current is nearly independent of gate voltage. On the other hand, the activation energy should be approximately equal to Eg, if the channel is made up of ideal single crystal Si with no GBs [37].
3.2.2 Gate-to-Drain Overlap Region
This mechanism exists in the gate-to-drain overlap region and depends on both the magnitude of the gate and drain bias. According to the electrical field strength inside the drain terminal, there are generally three conduction cases as illustrated in Figs. 3-4(a), (b) and (c).
In fact, this mechanism is similar to that described in Section 3.2.1.
For a fixed drain bias, as the gate is more negatively biased (or alternatively, for a fixed gate bias, the drain is more positively biased), i.e., increasing the voltage difference between the gate and drain (|VGD|), a depletion region would be formed in the n-type drain overlapping the gate. Under high electric field regime (Fig. 3-4(c)), the quasi-Fermi level at the channel/oxide interface shifts nearer to the valance band edge. This results in the generation of electron-hole pairs via the tunneling of the valance band electrons into the conduction band, i.e., band-to-band tunneling. Here, it is important to emphasize that this mechanism entirely takes place in the Si drain region instead of tunneling through the gate oxide. This is known as the gate-induced drain leakage (GIDL) [38].
The electric field distribution inside the drain terminal that directly account for the GIDL mechanism can be modulated by two major processing parameters. One is the dielectric thickness between the gate and drain. Since the dielectric has the ability to sustain voltage drop, lower electric field strength would be achieved by increasing its thickness. The other is the drain doping concentration. This is because the doping level determines the position of the Fermi level and influences the depletion width. Besides, the gate-to-drain overlap area and
defects density are two important factors that need to be taken into consideration.
3.3 Effects of Deep Ion Implantation
In our previous work, we have identified that GIDL is the most dominant leakage mechanism in our novel NW-TFTs due to their unique layout feature [39][40]. It was found that this leakage current could be restrained by inserting a Si3N4 hard mask (HM) between the gate and drain to reduce the electric field strength in the drain region [41]. In this study, we show that by carefully adjusting the implant energy, the undesirable GIDL mechanism in NW-TFTs could also be effectively suppressed.
Fig. 3-5 compares the off-state currents between devices (a) without and (b) with deep I/I, with various gate widths (GW), a structural parameter defined in Fig. 2-2(b). Fig. 3-6(a) shows the leakage currents of NW-TFTs, extracted from Fig. 3-5, without and with deep I/I as a function of GW at |VGD| = 8V. Furthermore, in Fig. 3-6(b), a parameter called off-state current ratio (OSCR),
which is the off-state current normalized to that with GW = 0.8 μm, is also shown as a function of GW. It is found that the off-state characteristics of NW-TFTs with deep I/I are nearly independent of the gate width. In our previous work, we have shown that the GIDL leakages are mainly constricted in the gate-to-drain overlap region with an area roughly proportional to the GW. The results shown in Figs. 3-5 and 3-6 indicate that the GIDL effect is greatly suppressed in devices with deep I/I. This is attributed to the increase of the dopant concentration in the drain region near the gate oxide, leading to the reduction in the depletion width and electric field strength.
Figures 3-7(a)~(f) show the dependence of the leakage current on the drain voltage for
devices without and with deep I/I at VG = 0, -1, -2, -3, -4 and -5 V, respectively. It reveals that the output characteristics are essentially the same for both splits under low VG, due to the low electric field strength. On the other hand, as a highly negative gate bias is applied, the GIDL mechanism becomes significant and the effect of the deep I/I becomes evident, as obviously shown in Fig. 3-7(f).
Based on the results presented above, Figs. 3-8(a) and (b) schematically depict the major leakage current paths in the drain side of the NW-TFTs (a) without and (b) with deep I/I, respectively. As shown in Fig. 3-8(a), Path A illustrates the occurrence of leakage current owing to the band-to-band or trap-assisted tunneling (GIDL) mechanism. These paths are easily turned on due to the very low dopant concentration in regions near the oxide interface, and can be shut off with the implementation of deep I/I in the drain side. When this is done, the leakage paths are then confined in a narrow region near the gate sidewall (Path B), as shown in Fig. 3-8(b). As a result, the off-state leakage becomes independent of the gate width, consistent with the experimental data observed in this work.
3.4 Activation Energy Extraction
In order to gain a deeper insight into the leakage mechanism, the off-state activation energy is obtained according to the governing equation of off-state current, activation energy and temperature [42], defined as
kT) exp( E I
Ioff = o − a (3-2)
where Io is the constant independent of temperature, Ea is the drain current activation energy, k is the Boltzman constant and T is the absolute temperature. The equation can also be expressed as
The off-state transfer characteristics of NW-TFTs (a) without and (b) with deep I/I measured at 25, 50, 75, 100, 125 ℃ are exhibited in Fig. 3-9. Next, we use equation (3-3) to plot the Arrhenius plots of off-state currents for NW-TFTs without and with deep I/I at various gate biases, which are shown in Figs. 3-10(a) and (b), respectively. From the date lines in Fig. 3-10, the activation energies (Ea) can be extracted from their slope, and are summarized in Fig. 3-11 for comparison. It indicates that the activation energy gradually decreases with a more negative gate bias due to GIDL mechanism. Moreover, it’s worth noting that the activation energy of NW-TFTs without deep I/I shows a stronger dependence on the gate voltage, in contrast to that with deep I/I. It’s because the electric field strength and depletion width are reduced by implanting an additional deep I/I, hence the undesirable GIDL mechanism can be suppressed effectively in NW-TFTs.
3.5 Electric Field Strength Simulation
ISE-TCAD, a powerful simulation tool for semiconductor process and device, was employed to simulate the electric field strength in the gate-to-drain overlap region at different dopant concentration in the drain terminal. We set the thickness of the drain and gate oxide to be 100 nm and 38 nm, respectively, the same as the experimentally measured thickness. For simplification, the dopant concentration was considered to be a uniform distribution. The gate and drain were then biased at -5 V and 3 V, respectively, i.e., in the off-state operation. After mesh and run step, the simulation results could be obtained.
Since we adopt n+ poly-Si as the gate material, the voltage difference |VGD| should be ideally shared by the drain and gate oxide besides the gate. In Fig. 3-12, the dependence of the electric field distribution in the drain and gate oxide on the dopant concentration is shown.
Specifically, the electric field strength inside the drain terminal is the most interesting parameter for understanding GIDL mechanism. For GIDL to take place, the drain doping level
should be modulated to about 1018 cm-3. If the doping level is much lower than this, the depletion width and tunneling barrier are too wide, eliminating the probability of band-to-band tunneling. On the other hand, if the dopant concentration is very high, |VGD| drops most of its voltage in the gate oxide instead of drain, as shown in Fig. 3-13. Owing to the suppression of the band-bending in the drain region, the GIDL occurrence can also be excluded. Finally, with the help of simulation, we succeed in explaining why GIDL can be suppressed in the novel SPC NW-TFTs by introducing an additional deep I/I.
Chapter 4
NW-TFTs Fabricated by MILC
4.1 Basic Characteristics of MILC NW-TFTs
Based on either one-sided or two-sided open window for MILC, the NW-TFTs were classified as metal-induced unilateral crystallization (MIUC) or metal-induced bilateral crystallization (MIBC). Furthermore, the measurement setup can also be divided into two splits called “Forward” and “Reverse” modes based on the reversal of the S/D. Hence, as shown in Fig. 4-1, there are four different kinds of MILC open window arrangements, including (a) MIUC (Forward), (b) MIUC (Reverse), (c) MIBC (Forward) and (d) MIBC (Reverse). In fact, MIBC (Forward) and MIBC (Reverse) should show nominally identical performance.
The transfer characteristics of MIUC (Forward) and MIUC (Reverse) NW-TFT are shown in Figs. 4-2(a) and (b), respectively. In Fig. 4-2(a), the device performance is dramatically enhanced as compared with SPC NW-TFTs described in Section 3.1. Higher on/off current ratio (5.17×106) and better subthreshold swing (0.27 V/dec) are obtained. We believe it is due to the improvement of the crystallinity in the channel. Since the migration of the NiSi2 precipitates is confined by the oxide around the NW channel, the crystallinity of the channel can be seen as a quasi-single-crystalline Si. Furthermore, the needle-like grain with crystallization direction along the NW channel is formed, so the number of barrier at the GBs where conduction electrons must overcome is reduced. As a result, the extracted field-effect mobility of MIUC (Forward) device is 60.25 cm2/V-s, which is much higher than 5.82
cm2/V-s of the SPC counterpart. In Fig. 4-2(b), anomalously high leakage current is observed in contrast to Fig. 4-2(a). The detail analysis will be described in the next section.
The GB trapping model proposed by J. Levinson et al. was used to determine the trap density [43]. When the current is governed by thermionic emission around GBs in poly-Si, the drain current in the linear region is given by
V )
where μo is the pre-exponential factor, q is the electric charge, Nt is the carrier trap-state density per unit area, t is the channel thickness and εs is the semiconductor permittivity. In Fig.
4-3, the plot of ln(ID/VG) versus (1/VG) for SPC and MIUC (Forward) NW-TFTs is shown.
According to equation (4-1), we can extract Nt from the slope of the data line. The result reveals that the Nt of MILC device is about one order smaller than that of SPC device.
Therefore, MILC process can dramatically improve the crystallinity of the poly-Si NW channel and enhance the device performance. Finally, major device parameters are extracted and summarized in Table 4-1.
4.2 Effects of MILC Open Window Arrangement
Since MILC open window contains high undesirable Ni contamination, its location would greatly influence the off-state characteristics of the devices. From the configurations illustrated in Fig. 4-1, the effect of the seeding window arrangement on the leakage current can be carefully addressed.
In Fig. 4-4, the off-state leakage current as a function of the offset length for devices fabricated by MIUC (Forward) and MIUC (Reverse) is shown. It reveals that the leakage current of MIUC (Reverse) NW-TFTs is about two orders larger than that of MIUC (Forward) NW-TFTs. It’s mainly due to the fact that the MIC region is just situated on the gate-to-drain
overlap region. The Ni-related species accumulated at the inter- and intra-grains may provide more deep states in the band gap of the Si, causing severe trap-assisted tunneling leakage mechanism. On the other hand, note that the leakage current of MIUC (Forward) and MIUC (Reverse) NW-TFTs is independent of and dependent on the offset length, respectively. From the SEM image shown in Fig. 4-5, a continuous boundary at MIC/MILC interface can be observed clearly after Secco etch [44]. If MILC open window is located at the source terminal, the highly defective MIC/MILC interface is located far away from the drain terminal. The trap states in the drain/channel junction are considered to be identical, so the leakage current is
overlap region. The Ni-related species accumulated at the inter- and intra-grains may provide more deep states in the band gap of the Si, causing severe trap-assisted tunneling leakage mechanism. On the other hand, note that the leakage current of MIUC (Forward) and MIUC (Reverse) NW-TFTs is independent of and dependent on the offset length, respectively. From the SEM image shown in Fig. 4-5, a continuous boundary at MIC/MILC interface can be observed clearly after Secco etch [44]. If MILC open window is located at the source terminal, the highly defective MIC/MILC interface is located far away from the drain terminal. The trap states in the drain/channel junction are considered to be identical, so the leakage current is