Leakage Mechanisms

NW-TFTs Fabricated by SPC

3.1 Fundamental Characteristics of SPC NW-TFTs

The operational principles of the novel NW-TFTs are similar to those of the conventional TFTs. The n⁺ ploy-Si side-gate is used to modulate the channel potential, thus controlling the switching behavior of the device. The transfer and output characteristics of SPC NW-TFTs are shown in Figs. 3-1(a) and (b), respectively. Fig. 3-1(a) reveals that good device performance with high on/off current ratio (6.23×10⁵) and reasonable subthreshold swing (0.83 V/dec) is achieved. Since the cross-sectional area of the NW channel is quite small, low leakage current was originally expected. However, the off-state current is anomalous high and depends on both the gate and drain bias. The leakage mechanism will be carefully examined and analyzed in the following sections. In Fig. 3-1(b), a kink effect is observed. Under high electric field region, the grain barrier heights for both sides of the grain boundary become asymmetric and the grain barrier height near the source side will be lower than that near the drain side. There will be extra carriers injecting from the source through the side with lower grain barrier into the channel. This phenomenon is so called the drain-induced grain barrier lowering (DIGBL) effect [34] [35]. Furthermore, the impact ionization mechanism initiated by the DIGBL current may cause an anomalous current increase in the saturation region.

3.2 Leakage Mechanisms

In poly-Si channels, the band diagram modulated by the drain and gate bias would affect

the off-state characteristics of the devices. Fig. 3-2 illustrates two possible regions for leakage generation in our novel NW-TFTs. One occurs in the drain/channel junction, and the other occurs in the gate-to-drain overlap region. Detail mechanisms would be briefly discussed as followed.

3.2.1 Drain/Channel Junction

This mechanism occurs laterally from the channel to the drain via trap-assisted conduction and is strongly dependent on the magnitude of the drain bias. According to the electrical field strength at drain/channel junction, there are generally three cases as illustrated in Figs. 3-3(a), (b) and (c):

(a) Under low electric field regime: Electrons are thermally excited from valence band into midgap states located at the grain boundaries (GBs), and then the trapped electrons are emitted to the conduction band in the same way, i.e., the so called “pure thermal emission” or “thermal generation”.

(b) Under medium electric field regime: Since the increasing drain bias pulls the energy band at the drain terminal down, the thermally excited electrons from the valence band to trap states can tunnel to the conduction band through the reduced barrier width. This is known as the thermionic field emission.

(c) Under high electric field regime: While the band-bending is pulled more severely, the electrons can easily tunnel from the valence band to the conduction band with the aid of the trap states. This is called field emission or tunneling.

In poly-Si channel, the presence of the trap states in the band gap plays an important role on the leakage current. The thermal emission current is proportional to the intrinsic carrier concentration of silicon (ni), which is proportional to exp[-Eg/2kT] (where Eg is the energy band gap of silicon, k is the Boltzmann constant, and T is the temperature in Kelvin) [36]. For

this reason, the activation energy of the pure thermal emission current should be approximately equal to Eg/2. In addition, the pure thermal generation current is nearly independent of gate voltage. On the other hand, the activation energy should be approximately equal to Eg, if the channel is made up of ideal single crystal Si with no GBs [37].

3.2.2 Gate-to-Drain Overlap Region

This mechanism exists in the gate-to-drain overlap region and depends on both the magnitude of the gate and drain bias. According to the electrical field strength inside the drain terminal, there are generally three conduction cases as illustrated in Figs. 3-4(a), (b) and (c).

In fact, this mechanism is similar to that described in Section 3.2.1.

For a fixed drain bias, as the gate is more negatively biased (or alternatively, for a fixed gate bias, the drain is more positively biased), i.e., increasing the voltage difference between the gate and drain (|VGD|), a depletion region would be formed in the n-type drain overlapping the gate. Under high electric field regime (Fig. 3-4(c)), the quasi-Fermi level at the channel/oxide interface shifts nearer to the valance band edge. This results in the generation of electron-hole pairs via the tunneling of the valance band electrons into the conduction band, i.e., band-to-band tunneling. Here, it is important to emphasize that this mechanism entirely takes place in the Si drain region instead of tunneling through the gate oxide. This is known as the gate-induced drain leakage (GIDL) [38].

The electric field distribution inside the drain terminal that directly account for the GIDL mechanism can be modulated by two major processing parameters. One is the dielectric thickness between the gate and drain. Since the dielectric has the ability to sustain voltage drop, lower electric field strength would be achieved by increasing its thickness. The other is the drain doping concentration. This is because the doping level determines the position of the Fermi level and influences the depletion width. Besides, the gate-to-drain overlap area and

defects density are two important factors that need to be taken into consideration.