Thesis Organization…

In this study, properties of silicon oxide deposited by SAPPT and E-gun system on silicon substrate are discussed. In addition, a suitable condition for silicon oxide deposited by SAPPT was selected from different temperature biases using MIS and MIM test structures.

In chapter 1, we describe application and Motivation of Organic Thin Film Transistor. Than acquaint with issues for fabrication OTFT structures, and technique of APPT.

In chapter 2, we adopt a new process, APPT, which can be operated under low temperature and atmospheric ambient. And APPT will make use of dielectric layer SiO₂ for our experiment. We use to two different systems deposited silicon oxide as insulator dielectric layer which to test insulator quality of handicapper convenient for metal insulator semiconductor ( MIS ), metal insulator metal ( MIM ) and amorphous silicon metal insulator metal ( a-Si MIM ) structures.

In chapter 3, we use different structures to experiment with silicon oxide dielectric layer quality and leakage current.

In chapter 4, we will describe the conclusions and the future works.

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R e f : W i l l i a m A . M a c D o n a l d “ A d v a n c e d F l e x i b l e P o l y m e r S u b s t r a t e s ” p . 1 6 5

F i g u r e 1 - 1 : C o m p a r e w i t h temperature f o r a v a r i e t y o f f l e x i b l e e l e c t r o n i c s u b s t r a t e s .

R e f : M R S 2 0 0 2 F l e x I C s

Ta b l e 1 - 1 : C o m p a r e w i t h characterization f o r a v a r i e t y o f f l e x i b l e e l e c t r o n i c s u b s t r a t e s .

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Figure 1-2: Construction of o r g a n i c t h i n - f i l m t r a n s i s t o r

Ta b l e 1 - 2 : Characterization of materials for OTFT.

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Figure 1-3: Classification of semiconductor materials

Figure 1-4: Molecular structure of pentacene.

Figure 1-5: Molecular structures of P3HT and BBL.

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R e f : Synthetic Metals 143 (2004) 21–23

Figure 1-6: Influence of mobility for OTFT passivation.

R e f : Current Applied Physics 5 (2005) 348–350

Figure 1-7: The electrical characteristics of OTFT encapsulated by the PVA coating method.

R e f : Current Applied Physics 5 (2005) 348–350 Figure 1-8: The electrical characteristics of OTFT encapsulated by polyacrylate-based

adhesive multilayer composed method.

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Ref: Organic electronics 8 (2007) 450-454.

Table 1-3: Characterization of contact angle for organic and inorganic materials

Figure 1-9: Schematic of the organic thin film transistors (OTFTs) with (a) Top gate/Bottom contact structure (b) Top gate/Top contact structure (c) Top contact/Bottom gate structure (d) Bottom contact/Bottom gate structure (e) Double gate structures.

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Table 1-4: Characterization of dielectric materials and process methods for OTFT

Figure 1-10: APPT system of ITRI

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Chapter 2 Experiment

2.1 Silicon oxide deposited with E-gun and SAPPT equipments on the metal insulator semiconductor ( MIS ) structure

In this scenario, we use to two different systems deposited silicon oxide as insulator dielectric layer which to test insulator quality of handicapper convenient for metal insulator semiconductor ( MIS ) structure.

First, the n⁺-Si wafer was used as the substrate, and was rinsed in the deionization water ( DI water ), and was then dipped in dilute HF solution ( HF:DI water = 1:100 ) that to remove the native oxide, the wafer was accomplished the RCA Clean procedure after, deposition of silicon oxide were electron-beam ( e-gun ) technique and atmospheric-pressure plasma technology ( APPT ), respectively.

In atmospheric-pressure plasma technology aspect, Heats up the Tetraethoxy silane ( TEOS ) to 180℃ was injected by nitrogen ( 50％ ) and oxygen ( 50％ ) as carrier gases which was the deposition source of silicon oxide. The plasma power was established around 50 W with an appropriate scanning rate ( sccm /cycle ) to deposit silicon oxide on the top of n⁺-Si substrate at room temperature under an atmospheric- pressure. The thickness of silicon oxide was increased with the scanning times ( cycle/area ) , and we adopted 80 times and flow 1 sccm parameters to compare with different silicon oxide dielectrics.

In electron-beam technique aspect, the silicon substrate was deposited 60 nm thick remained at room temperature ( 25℃ ) that the deposition rate and vacuum pressure were 0.05 nm/sec and 4×10^-6 Torr, respectively. Finally, all top contact electrodes were deposited 300 nm thick aluminum layer defined with shadow mask by thermal coater system. The active region pad of all capacitors was diameter 200 µm and all bottom contact electrode were deposited 300 nm thick aluminum layer before the bottom n⁺-Si substrate swabs the sponge of dilute HF solution.

2.2 Silicon oxide deposited with effect of substrate temperature by

SAPPT on the metal insulator metal ( MIM ) structure

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In this scenario, we purpose to deposit silicon oxide dielectric on the bottom contact electrode metal by atmospheric-pressure plasma technology. But silicon oxide was not deposited on the metal at room temperature. Consequently, we try to find solution to heat up to the n⁺-Si substrate that was able to deposit on the metal.

First, the n⁺-Si wafer was used as the substrate, and was rinsed in the deionization water ( DI water ), and was then dipped in dilute HF solution ( HF:DI water = 1:100 ) that to remove the native oxide, the wafer was accomplished the RCA Clean procedure after, deposition of silicon dioxide was thermal kiln grown 500 nm thick on the top of n⁺-Si substrate for isolation purpose. And deposited 300 nm aluminum as the bottom electrode. Heats up the Tetraethoxy silane ( TEOS ) to 180℃ was injected by nitrogen ( 50％ ) and oxygen ( 50％ ) as carrier gases which was the deposition source of silicon oxide. The plasma power was established around 50 W with an appropriate scanning rate ( sccm /cycle ) to deposit silicon oxide on the top of n⁺-Si substrate at room temperature under an atmospheric-pressure. The thickness of silicon oxide was increased with the scanning times ( cycle/area ) , silicon oxide was deposited on the aluminum thin film by atmospheric-pressure plasma technology ( APPT ) with varied substrate temperature (was treated at 100℃ , 150℃, and 200℃ respectively). Than we adopted 60 times and flow 1 sccm parameters to compare with different silicon oxide dielectrics.

Finally, all top contact electrode were deposited 300 nm thick aluminum layer defined with shadow mask by thermal coater system. The active region pad of all capacitors was diameter 200 µm .

2.3 Deposition of silicon oxide dielectric under room temperature on amorphous silicon metal insulator metal ( a-Si MIM ) structure

In this scenario, we purpose to deposit silicon oxide dielectric on the bottom contact electrode metal by atmospheric-pressure plasma technology. But silicon oxide was not deposited on the metal at room temperature. Consequently, we try to find solution to deposit amorphous silicon on the bottom electrode metal by electron-beam technique that was able to deposit on the metal at room temperature.

First, the n⁺-Si wafer was used as the substrate, and was rinsed in the deionization water ( DI water ), and was then dipped in dilute HF solution ( HF:DI water = 1:100 )

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that to remove the native oxide, the wafer was accomplished the RCA Clean procedure after, deposition of silicon dioxide was thermal kiln grown 500 nm thick on the top of n⁺-Si substrate for isolation purpose. And deposited 300 nm aluminum as the bottom electrode.

Then, we deposited amorphous silicon thickness of 2 nm by electron-beam technique that in order to easeful grow silicon oxide by atmospheric-pressure plasma technology at room temperature.

Heats up the Tetraethoxy silane ( TEOS ) to 180℃ wae injected by nitrogen ( 50

％ ) and oxygen ( 50％ ) as carrier gases which was the deposition source of silicon oxide. The plasma power was established around 50 W with an appropriate scanning rate ( sccm /cycle ) to deposit silicon oxide on the top of n⁺-Si substrate at room temperature under an atmospheric-pressure. The thickness of silicon oxide was increased with the scanning times ( cycle/area ) , silicon oxide was deposited on the aluminum thin film by atmospheric-pressure plasma technology ( APPT ) with varied scanning times ( at 60, 80, 100, and 120 times respectively). Than we adopted flow 1 sccm parameter to compare with different silicon oxide dielectrics.

Finally, all top contact electrode were deposited 300 nm thick aluminum layer defined with shadow mask by thermal coater system. The active region pad of all capacitors was diameter 200 µm .

2.4 Fabricated processes of organic thin film transistor ( OTFT )

In this scenario, we adopted flow 1 sccm and 60 times parameters to deposit insulator as gate dielectric layer on the organic thin film transistor structure by atmospheric-pressure plasma technology ( APPT ).

First, the n⁺-Si wafer was used as the substrate, and was rinsed in the deionization water ( DI water ), and was then dipped in dilute HF solution ( HF:DI water = 1:100 ) that to remove the native oxide, the wafer was accomplished the RCA Clean procedure after, deposition of silicon dioxide was thermal kiln grown 500 nm thick on the top of n⁺-Si substrate for isolation purpose. The bottom contact structure was adopted to fabricate organic thin film transistor. That the structure of organic thin-film transistor.

And deposited 50 nm thick aluminum layer as the gate electrode by lift-off method. The aluminum layer was deposited by thermal coater and silicon oxide deposited by

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atmospheric-pressure plasma technology ( APPT ) at 150℃ under an atmospheric pressure with scanning 60 times was used as gate insulator. Source/ Drain electrodes with 50 nm thick nickel layer were deposited by electron-beam technique. The active layer used in this study was pentacene (obtained from Aldrich Co., Ltd.) which was evaporated by thermal coater. During deposition of pentacene active layer, the substrate was heated to 70℃ at power 17 W in a pressure chamber of around 1x10^-6 Torr.

2.5 Characteristic measurement of devices

Capacitance-Voltage (C-V) characteristic diagrams were analyzed at 1MHz by HP 4284A precision LCR meter parameter and the characteristic curves of Current-Voltage (I-V) were measured with semiconductor parameter analyzer by HP 4156. All measurements were carried out at room temperature in an air atmosphere.

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Figure 2-1: Fabrication flow of metal insulator semiconductor ( MIS ).

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Figure 2-2: Fabrication flow of metal insulator metal ( MIM ).

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Figure 2-3: Fabrication flow of amorphous silicon metal insulator metal ( a-Si MIM ).

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Figure 2-4: Fabrication flow of organic thin film transistor ( OTFT ).

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Chapter 3

Results and Discussion

3.1 Silicon oxide dielectric layer quality analysis and appraisal 3.1.1 MIS

We use to two different systems deposited silicon oxide as insulator dielectric layer which to test insulator quality of handicapper convenient for metal insulator semiconductor ( MIS ) structure. Sample A and sample B was APPT and E-Gun deposition respectively.

The C-V characterization of sample A and sample B was shown in Figure 3-1.

EOT (Equivalent Oxide Thickness) calculated from capacitance of Figure 3-1(a) for sample A and sample B was about 8.277 nm and 10.919 nm respectively. The expression of EOT is very popular for the high dielectric constant gate insulator of CMOS device [16]. Because there are many kinds of insulator materials with different dielectric constants, EOT could be considered as a standard for a comparison of the gate insulator controllability to channel accumulation. The calculation of EOT is presented at equation ( 3-1 ). The circular area of top electrode in this study was diameter 200 µm .

( 3-1 )

The relationship between I-V of sample A and sample B were showed in Figure 3-1(b). The leakage current of sample B is higher than sample A at 1.5V bias voltage.

However, because we want to know the effect of silicon oxide deposited by e-gun and SAPPT at different physical thickness, we try to make the comparison under the same electric field obtained from the voltage divided by the EOT (EEOT= Bias Voltage / EOT).

When two OTFT devices are biased at the same E_EOT, which means the same

charges were accumulated at both device’s channels. In this case, when the E_EOT was 1.5 MV/cm, leakage current of sample B is higher than sample A. Show figure 3-1 (c ).

.

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3.1.2 MIM

We purpose to deposit silicon oxide dielectric on the bottom contact electrode metal by atmospheric-pressure plasma technology. But silicon oxide was not deposited on the metal at room temperature. Consequently, we try to find solution to heat up to the n⁺-Si substrate that was able to deposit on the metal. Silicon oxide of sample D ~ F was deposited by SAPPT on the bottom electrode surface at different substrate temperature at 100℃, 150℃, and 200℃. The horizontal axis and vertical axis of Figure 3-2 represent the swept voltage set and the value of capacitance respectively. The values of EOT calculated from Figure 3-2 (a) of sample D, E, and F were about 20.198 nm, 23.836 nm, and 28.496 nm respectively, so we could find that the deposition rate was increased with the substrate temperature. However, the capacitance value of sample C couldn’t be measured due to the high leakage current. The I-V characterization of sample C shows almost short circuit current, which implies the deposition rate was almost zero when we deposited silicon oxide on the surface of aluminum at room temperature. This situation is very different to that by deposited on silicon substrate at room temperature. These results revealed that the surface material is a main factor for SAPPT method to deposit silicon oxide at room temperature. The leakage current density versus electric field was shown in Figure 3-3. The leakage current of sample E and sample E-Gun is about 9×10^-8 A/cm²and 2×10^-7 A/cm²at 0.5 MV/cm respectively.

The quality of silicon oxide deposited by SAPPT at 150℃ is better than that deposited by e-gun.

3.1.3 a-Si MIM

We purpose to deposit silicon oxide dielectric on the bottom contact electrode metal by atmospheric-pressure plasma technology. But silicon oxide was not deposited on the metal at room temperature. Consequently, we try to find solution to deposit amorphous silicon on the bottom electrode metal by electron-beam technique that was able to deposit on the metal at room temperature. Silicon oxide was deposited on the aluminum thin film by atmospheric-pressure plasma technology ( APPT ) with varied scanning times at 60, 80, 100, and 120 times respectively. Than we adopted flow 1 sccm parameter to compare with different silicon oxide dielectrics.

The horizontal axis and vertical axis of Figure3-4 represent the swept voltage set and the value of capacitance respectively. The values of EOT calculated from Figure3-4

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(a) of sample 60, 80, 100, and 120 times were about 18.072 nm, 19.715 nm, 24.643 nm and 27.108 nm respectively,

The leakage current density versus electric field was shown in Figure 3-5. The leakage current of sample E-Gun is about 2×10^-7 A/cm² at 0.5 MV/cm respectively. The quality of silicon oxide deposited by e-gun is better than that deposited by SAPPT.

3.2 Determination of Threshold voltage and Mobility

The linear regime field effect mobility can be obtained by the calculation described below. At low VD, ID increases linearly with VD (linear regime) and is approximately determined by the following equation:

where L is the channel length, W is the channel width, C_ox is the capacitance per unit area of the insulating layer, V_T is the threshold voltage, and µ is the field effect mobility, which can be calculated in the linear regime from the transconductance,

Gm = _nC_oxV_D value of the slope of this plot to Gm, then find Gmmax which can gain the value of threshold voltage (VT) and linear mobility. For the known values included Cox, VT, and W/L, the value of saturation mobility can be obtained from equation (3-4)

( )

²

3.3 OTFT electric characteristics analysis and discussion

At this part, SAPPT method was adopted to fabricate the gate insulator of OTFT with the parameters of sample E discussed. Process temperature and throughput are the two main considerations for this selection. First, most plastic substrates could not sustain temperature higher than 200℃. The process condition of sample E (150℃) provides a suitable thermal buffer for flexible electronic device fabrication. Secondly, the deposition rate is increased with the raised process temperature and the condition of sample E has a relatively higher deposition rate than sample D. The condition of sample

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E is still a low temperature process and can get a better deposition rate for throughput and still maintain good quality. The drain current (ID) versus drain-source voltage (VDS) at varied gate voltages (VGS) was shown in Figure 3-8(a). The output characteristic of ID

versus VGSwas shown in Figure 3-8(b). The carrier mobility was calculated at the saturation region with following equation:

( 3-5 )

Ci is the capacitance per unit area of gate insulator in equation. (3-5). It correspond to a device with channel width W = 200 µm and length L = 50 µm. The saturation mobility and the threshold voltage of the OTFT were about 0.066 cm²/V-sand - 2 V respectively.

The OTFT could be operated at the voltage below -5 V due to the EOT of about 14 nm.

However, the mobility of this device was lower than some other reports [17, 18]. We suggested that three possible reasons could explain this phenomenon. First, since we fabricated the OTFT device with bottom contact structure [2], the grain size of the active layer would be affected by the roughness of the electrodes of source and drain.

Secondly, the roughness of aluminum gate electrode was about 8.7 nm (the corresponding AFM analysis was shown in Figure 3-14(a)), the roughness of the silicon oxide deposited by SAPPT on the top of aluminum gate electrode was around 10.8 nm (see Figure 3-14(b)). Third, the contact angle of gate insulator with DI water was about 20 degree and figure 3-15 shows hydrophilic characteristic at the surface of the silicon oxide. Roughness and hydrophilic characteristic might be the main factors to influence the deposition of pentacene and then decrease the mobility of OTFT devices. [18-20].

3.4 Leakage current characteristic of OTFT discussion in various structures

We can see leakage current 3×10^-7 A at drain/source voltage and gate voltage was zero and -7 respectively. In figure 3-8(b). Consequently, we to discuss for leakage current in the different structure. View from figure 3-9 to figure 3-13.

First, we compare with define pentacene region and not define pentacene region in figure 3-9. Result in leakage current of not define pentacene region is higher than define pentacene region. Because of not define pentacene region have large field that account to more leakage current. And we adopt two materials to experiment, we obtain the same result. Hence, define pentacene region is important for OTFT divice that can be

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effective reduce leakage current.

We compare with have HMDS and not have HMDS in figure 3-11. Result in leakage current of have HMDS is higher than not have HMDS. Because of HMDS can be increase pentacene grain size and increase pentacene conductivity. Therefore, we found have HMDS not only the increase conductive merit but also increases leakage the current shortcoming. In figure 3-12 and figure 3-13, leakage current of not define pentacene region is higher than define pentacene region and leakage current of have pentacene is higher than not have pentacene.

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Figure 3-1: The electronic characterization of MIS.

0.5 1.0 1.5 2.0 2.5

Leakage Current Density ( A/cm2 )

Bias ( V )

Leakage Current Density ( A/cm2 )

V/EOT ( MV/cm )

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( a )

( b )

Figure 3-2: The electronic characterization of MIM for C-V and I-V.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

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( a )

( b )

Figure 3-3: The electronic characterization of MIM for I-V and I-E.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 -1.2x10^-7

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( a )

( b )

Figure 3-4: The electronic characterization of a-Si MIM for C-V and I-V.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

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( a )

( b )

Figure 3-5: The electronic characterization of a-Si MIM for I-V and I-E.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

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( a )

( b )

Figure 3-6: The electronic characterization of MIM, a-Si MIM and E-Gun for C-V and I-V.

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( a )

( b )

Figure 3-7: The electronic characterization of MIM, a-Si MIM and E-Gun for I-V and I-E.

0.00 0.06 0.12 0.18 0.24 0.30 0.36 0.42 0.48 0.54 0.60 -1.0x10^-7

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Figure 3-9: The electronic leakage current characterization of pentacene-HfO2 MIM for I-V.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 -20.0p

0.0 20.0p 40.0p 60.0p 80.0p 100.0p 120.0p 140.0p 160.0p 180.0p 200.0p 220.0p 240.0p 260.0p 280.0p 300.0p 320.0p

HfO

₂

No Define Define

Leakage Current ( A )

Bias ( V )

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Figure 3-10: The electronic leakage current characterization of pentacene-SiO2 MIM for I-V.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.0

1.0n 2.0n 3.0n 4.0n 5.0n 6.0n 7.0n 8.0n 9.0n 10.0n 11.0n 12.0n 13.0n

SiO

₂

No Define Define

LeaKage Current ( A )

Bias ( V )

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Figure 3-11: The electronic leakage current characterization of pentacene-SiO2 MIM for I-V.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.0

1.0n 2.0n 3.0n 4.0n 5.0n 6.0n 7.0n 8.0n 9.0n 10.0n 11.0n 12.0n 13.0n 14.0n

SiO

2

Have HMDS No HMDS

Leakage Current ( A )

Bias ( V )

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Figure 3-12: The electronic leakage current characterization of OTFT for HfO2.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0.0 20.0p 40.0p 60.0p 80.0p 100.0p 120.0p 140.0p 160.0p 180.0p 200.0p 220.0p 240.0p

HfO

2

No PR Define PR Define No Pentacene

Leakage Current ( A )

Bias ( V )

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Figure 3-13: The electronic leakage current characterization of OTFT for SiO2.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0.0 20.0p 40.0p 60.0p 80.0p 100.0p 120.0p 140.0p 160.0p 180.0p 200.0p 220.0p 240.0p

SiO

2

No PR Define PR Define No Pentacene

Leakage Current ( A )

Bias ( V )

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Figure 3-14:

( a ) shows the AFM image of aluminum gate insulator with roughness about 8.7 nm.

( b ) shows the AFM image silicon oxide deposited at 150℃ on the aluminum with the roughness around 10.8 nm.

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Figure 3-15:

(a) shows the contact angle image silicon oxide deposited at 150℃ on the aluminum with the angle around 20°.

(b) shows the contact angle image with HMDS the angle around 68.1°.

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Chapter 4 Conclusion

4.1 Conclusion

From the experiment 3.1.1 and 3.1.2, we can know that the deposition rate of silicon oxide deposited by SAPPT at room temperature depend on the surface material where to deposit on. The leakage current of silicon oxide deposited by SAPPT at 150℃ (sample E) was about 9×10^-8 A at 0.5 MV/cm which is around one order lower than that of the control sample G (E-gun deposition). Because sample E has better insulator property due to a higher deposition rate and suitable process temperature than other samples deposited by E-gun, its process condition was chosen to fabricate OTFT device. OTFT with the gate insulator deposited by scanning atmospheric-pressure technology was successfully demonstrated in experiment 3.1.3. The highest process temperature in the fabrication of OTFT device was 150℃. The operation voltage of this device is reduced to -5V due to the smaller EOT of 14 nm. Although the mobility of our device is lower than 0.1 cm²/V-s. The reasons for low mobility may be caused by the surface roughness of gate electrode and the hydrophilic surface in SAPPT process.

In summary, we already fabricated successfully OTFT with good dielectric property by using SAPPT method and demonstrated that SAPPT is a suitable method to fabricate good dielectric for the applications of plastic substrate due to the low temperature process under an atmospheric pressure.

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4.2 Future work

• Improves the organic thin film transistor performance on surface treatment by atmospheric pressure plasma technology.

• Change gate electrode metal from aluminum to nickel , tellingly reduce surface roughness enhance organic thin film transistor performance .

• Because Pentacene OTFT are sensitive to ambient conditions. Protection from the environment by encapsulation is critical to the stability of Pentacene OTFT.

Therefore, using a suitable material as passivation to protect Pentacene film from environmental effect is another important topic.

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Reference

1. M. Shtein, J. Mapel, J. B. Benziger, and S. R. Forrest, Appl. Phys. Lett., 81 (2002)

1. M. Shtein, J. Mapel, J. B. Benziger, and S. R. Forrest, Appl. Phys. Lett., 81 (2002)

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