Chapter 1 Introduction
1.2 Thesis Organization
This thesis is organized into six chapters.
Chapter 1 briefly describes the motivation of this thesis.
Chapter 2 begins with the fundamental concepts of analog-to-digital conversion and performance metrics used to characterize ADCs. Then, several Nyquist-rate ADC architectures are introduced. The evolutions and properties for different ADCs are described.
Chapter 3 concentrates on the detail operation principle and the calibration techniques of pipelined ADCs. Then, the most popular 1.5-bit/stage structure for pipelined ADC is presented, which is very suitable for high speed and low power design. For even more enhancing the performance, the proposed improved loading-free architecture is developed to speed up the ADC and opamp-sharing technique is used for better area and power efficiency. A summary is placed in the last to describe the whole pipelined ADCs with above two techniques.
Chapter 4 illustrates the designs and implementations of the circuit blocks used in the proposed pipelined ADCs. First, the analog blocks, such as MDAC and Sub-ADC, are described. The core components like opamp and comparator are discussed deeply.
Then, the digital blocks like digital error correction logic and clock generator are introduced. The transistor level simulation results of each circuit are also presented.
Finally, the layouts of the proposed pipelined ADCs are shown with their floor plans.
Chapter 5 presents the measurement environment, including the required instruments and component circuits on the DUT board. The measured results of the pipelined ADC with opamp-sharing technique described in Chapter 3 and Chapter 4 are shown and summarized.
Finally, Chapter 6 is the conclusions of this work. Some suggestions and improved recommendations are proposed for the future work.
Chapter 2
Overview of Analog-to-Digital Converters
2.1 Introduction
This chapter first introduces the concept of ideal analog-to-digital converters and the performance metrics which are useful to determine the quality of the ADCs. In the following section, some Nyquist-Rate ADC architectures are introduced and their characteristics are described. These architectures are developed for differential requirement such as speed, resolution, power consumption and area. The techniques used to cancel the various error sources for several architectures are also introduced.
2.2 Fundamental Aspects of A/D Converters
A analog-to-digital converter connects the continuous analog signal and the discrete digital word. In the beginning, the ideal behavior of the conversion is introduced. Following, the quantization noise caused by the quantization error is also discussed, since it is the dominate noise source of a analog-to-digital converter. In the final section, the performance metrics, which obviously indicate the quality of ADCs, are described.
2.2.1 Ideal A/D Converter
A ideal analog-to-digital converter tend to quantize the analog input signal into an N-bit digital word is shown in Figure 2.1, where B is the digital output word while out
V and in V are the analog input and reference signals, respectively. That is, the full ref range of analog input signal is divided into several uniform levels according to the number of quantization steps,
2N
Number of quantization steps = (2.1) and each level width is defined as
2 1 significant bit (MSB) and b as the least significant bit (LSB). 0
/
Figure 2.1 Ideal analog-to-digital converter.
For an A/D converter, the following equation relates these signals,
(
12 1 22 2 02 N)
ref N N in x
V b - - +b - - + ××× +b - =V + , where V 1 1
-2VLSB £Vx £2VLSB (2.3) Note that V also known as quantization error is the difference between the analog x input signal and the quantized output signal [4][5].
2.2.2 Quantization Noise
As mentioned above, quantization errors occur even in ideal A/D converter. We can make a linear model for the quantized output signal, Vstaircase, which is equal to the analog input signal, V , subtract the quantization noise signal, in V , as shown in Q Figure 2.2.
Figure 2.2 Linear model for the quantized output signal.
The quantization noise signal is defined as the difference between the actual analog input and the quantized output signal, and can be represented as
Q in- staircase
V =V V (2.4) Figure 2.3 (a) shows the transfer curve for an ideal 3-bit ADC and the corresponding quantization noise is shown in Figure 2.3 (b) [6]. Note that the quantization noise is limited to ±VLSB/ 2.
Figure 2.3 (a) Transfer curve for an ideal 3-bit ADC and
In a stochastic approach, we assume that the input signal is varying rapidly such that the quantization noise signal, V , is a random variable uniformly distributed between Q
LSB/ 2
±V . The probability density function for such an noise signal, f q , will be a Q
( )
constant value, as shown in Figure 2.4. Hence, the quantization noise power, P , is Q given by
Figure 2.4 Probability density function of quantization noise.
2.2.3 Performance Limitations
Before proceeding, it is required to know the performance metrics for determining the transfer response of the data converters. In this section, some commonly used terms characterizing the performance of data converters are introduced as below.
2.2.3.1 Resolution
The resolution of an ADC is defined to be the number of the distinct input segments corresponding to the different output word. It also indicates the minimal difference of the input signal that can be recognized by the ADC. An N-bit resolution ADC means that the converter can resolve 2N distinct input segments. We can find that high resolution ADCs can resolve smaller segments of the input signal than low
resolution ADCs. This quantity does not mean actually the accuracy of the converter, but instead it usually refers to the number of output bits.
2.2.3.2 Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio of the signal power to the output noise power. The SNR includes the quantization noise and other circuits noise excluding the harmonic components of the input signal. If it is assumed that the input signal is a sinusoidal waveform between 0 and V , then the RMS value of the sinusoidal wave ref
is equal to Vref / 2 2
( )
. If we only consider the quantization noise of the ADCs, theHowever, the SNR decreases from the best possible value for reduced the input signal levels [4].
2.2.3.3 Signal-to-Noise plus Distortion Ratio (SNDR)
The signal-to-noise plus distortion ratio (SNDR) is often used to measure the performance of an ADC. When a sinusoidal signal is applied to an ADC, the output spectrum generally contains a single tone at the fundamental frequency. Due to distortion, the output spectrum also contains several tones at the harmonic frequency, known as harmonic distortion. As a result, the SNDR of the ADC is defined as the ratio of the signal power at the fundamental frequency to the total power of non-ideal effects, including the harmonic distortion, quantization noise and other noise sources
2.2.3.4 Spurious Free Dynamic Range (SFDR)
The spurious free dynamic range is defined as the power ratio of the input signal to the largest distortion component. In a fully differential signal system, generally the largest distortion component is the 3rd harmonic term.
For more clearly figuring out the difference among SNR, SNDR and SFDR, a spectrum diagram is shown in Figure 2.5, where S is the fundamental frequency of the input signal, D are the distortion components and N is the noise floor.
Power Spectrum
f S
N
D
SFDR
fin 2fin 3fin
Figure 2.5 The spectrum diagram with signal, distortion and noise.
The SFDR is depicted in Figure 2.5, and the SNR and SNDR are depicted as below respectively.
S S
SNR SNDR
N N D
= =
+ (2.7)
2.2.3.5 Effective Number of Bits (ENOB)
Another specification often used to describe the ADC’s performance is the effective number of bits (ENOB). Different from resolution, ENOB indicates the ADC’s accuracy in a specific input frequency and sampling rate, and it can be expressed from SNDR as follow:
-1.76 6.02
ENOB= SNDR bits (2.8)
2.2.3.6 Offset and Gain Error
The transfer characteristic of an ADC is expected to be a straight line with uniform step width. However, the actual transfer step widths might not be uniform ideally. These non-ideal terms cause errors and non-linearity performance in ADCs.
Figure 2.6 (a) shows the offset error, which is defined as the horizontal deviation from the ideal position by a constant amount. The gain error (or scale factor error) describes the difference of slop between the ideal straight line and the actual transfer line, as shown in Figure 2.6 (b).
Input Output
actual ideal
( )a ( )b
Offset Error
Gain Error
actual ideal Output
Input
Figure 2.6 Illustrating (a) offset error and (b) gain error for a 3-bit A/D converter.
2.2.3.7 Differential Non-Linearity Error (DNL)
After both the offset and gain errors have been removed, each transfer step level might not be equal to 1 LSB (
2
ref N
=V ) ideally. The differential non-linearity error is
( )
, 11
step n
Width LSB
DNL n
LSB
= - (2.9)
An ADC is guaranteed not to have any missing codes if the minimum DNL error is larger than -1 LSB.
2.2.3.8 Integral Non-Linearity Error (INL)
The integral non-linearity error is defined as the deviation of the middle point of each transfer step form the ideal straight line. There are two ways to define the straight line. A common used definition is known as the endpoint straight line which is drawn through the end points of the first and last code transition. An alternative definition is to find the best-fit straight line such that the maximum INL is minimized [4]. The INL is also specified after both the offset and gain errors have been removed and can be expressed as
( )
( ), ( ),1
t n actual t n ideal
V V
INL n
LSB
= - (2.10)
Figure 2.7 shows the illustration of the DNL and INL.
Input Output
actual ideal
INL
1 LSB
1 DNL+ LSB
Figure 2.7 Illustrating the DNL and INL.
2.2.3.9 Sampling-Time Uncertainty (Aperture Jitter)
The sampling-time uncertainty is another significant issue that limits the performance of ADCs, which is also known as aperture jitter. Considering a sinusoidal wave input signal, V , with input frequency in f as below in
( )
sin 2( )
2
ref
in in
V t =V p f t (2.11)
Since the variance of V for a sinusoidal waveform is the largest at the zero crossing in point, we can find out the maximum slope by differentiating V with respect to time in and setting t=0, as shown below
max in
in ref
V f V
t p
D =
D (2.12) If Dt represents the sampling-time uncertainty, and if we want to keep DVin less than 1 LSB, we can find that
in in ref LSB
V p f V t V
D = D < (2.13)
In consequentially, we get the limit of the aperture jitter Dt of a N-bit ADC as follows
1 2
LSB
N
in ref in
t V
f V f
p p
D < = (2.14)
Figure 2.8 shows the concept of the aperture jitter [4].
2 Vref
2 Vref
-0
V
int
D t
V
inD
Sampling
Time
Figure 2.8 Aperture jitter.
2.2.3.10 Dynamic Range (DR)
The dynamic range is defined as the ratio between the maximum signal power for peak SNR and the minimum detectable signal power within a specified bandwidth.
With a sinusoidal input signal, we can measure the dynamic range by varying its amplitude to find the 0dB SNR and peak SNR positions, as shown in Figure 2.9. If the noise power is independent on the signal power, the dynamic range is equal to the SNR at full scale. However, generally the noise power increases as the signal power increases. Therefore, the actual peak SNR will be less than the dynamic range [3].
Dynamic Range
( )
SNR dB
( )
Vin dB
Peak SNR
0 dB
Figure 2.9 Dynamic range.
2.3 Review of Nyquist-Rate A/D Converter Architecture
Architectures for implementing analog-to-digital converters (ADCs) can be roughly divided into three categories (Table 2.1)—low-to-medium speed, medium speed, and high speed. These different architectures of ADCs are developed for different applications. Each of them has different trade-off among speed, resolution, power, and area. In the section, Nyquist-rate A/D converters are introduced. These ADCs generate a series of output codes in which each code has a one-to-one correspondence with a single input value. With high operation speed near the Nyquist rate, these ADCs are good for high speed application. Another kind of ADCs is known as oversampling A/D converters, which are not introduced in this section.
These ADCs operate much faster than the input signal’s Nyquist rate and increase the signal-to-noise ratio (SNR) by filtering out quantization noise. Generally, the oversampling ADCs are adopted for high resolution design.
Table 2.1 Different A/D converter architectures [4].
Low-to-Medium Speed, High Accuracy
Medium Speed, Medium Accuracy
High Speed, Low-to-Medium Accuracy Integrating
Oversampling
Successive approximation Algorithmic
Flash Two-step Interpolating
Folding Pipelined Time-interleaved
2.3.1 Flash (or Parallel) ADC
Flash ADCs, also known as Parallel ADCs, have the highest speed in overall ADC architectures. As seed in Figure 2.10, a flash ADC is composed with a resistor string、2N-1 comparators and a (2N-1)-to-N decoder. The resistor string contains 2N resistors and divides the reference voltage into 2N-1 segment values, and each of which is fed to a comparator’s negative input. The input voltage is compared with each segment value and results in a thermometer code at the output of the comparators.
The thermometer exhibits all ones at the bottom if Vinput is great then the voltage on
the resistor string, and zeros at the top if Vinput is less then the voltage on the resistor string. Finally, an (2N-1)-to-N decoder is used to convert the (2N-1)-bit thermometer code into an N-bit binary output code. It is obvious that all comparators operate in parallel, and then the decoder deals with the output codes of these comparators immediately. Therefore, flash ADCs can generate a digital output word in each clock phase. Besides, the conversion speed of the flash ADC is only dependent on the speed of the comparators and the digital decoder, so it is easy to achieve high speed. With extremely high throughput, the flash ADC is quite suitable for very high speed application. However, for high resolution flash ADCs, a larger number of comparators and small offset for these comparators are required. Design of a comparator with small offsets is difficult and expensive. Furthermore, a large number of comparators induces a large input capacitive loading limiting the conversion rate and consumes large power and area. For above reasons, high resolution ADCs are rarely implemented by flash architectures.
Vref Vinput
R R
R R R
N
to N D ec od er -
-N bit Binary Output
2 -1N comparators
Thermometer code
Figure 2.10 An N-bit Flash ADC.
2.3.2 Two-Step ADC
Accompanying the increase of resolution, the flash ADC becomes nearly impossible to be realized for too large power consumption and area. One way to solve this problem is to separate the converter into two complete flash ADCs, which is known as two-step ADC. A two-step ADC mainly consists of a MSB ADC and a LSB ADC, which are used to convert the former bits and the later bits separately. As shown in Figure 2.11, we assume the MSB ADC is an M-bit converter and the LSB ADC is an L-bit converter, so the Sub-DAC must be an M-bit converter and the total output resolution, N, is equal to the sum of M and L. First, the input signal is quantized by the MSB ADC, and then the Sub-DAC would convert the first M-bit output code back to analog signal. This analog signal would be subtracted from the input signal, and then the result would be multiplied by 2M. The output value of the amplifier is known as residue value. In the next phase, the residue value is fed to the
LSB ADC to determine the last L-bit output code, and then the total N-bit output code flash ADC, which only needs one clock cycle [7].
M bit
Figure 2.11 An N-bit Two-Step ADC.
2.3.3 Pipelined ADC
In two-step ADC, the ADC is divided into two steps, and it could be possible to separate the ADC into N steps, which is known as a pipelined ADC. As shown in Figure 2.12, a pipelined ADC consists of a S/H, several identical stages and a flash ADC in the final part. Each identical stage includes a Sub-ADC and a multiplying digital-to-analog converter (MDAC), which is composed of the S/H, the Sub-DAC, the subtractor and the gain amplifier.
/
Figure 2.12 An N-bit Pipelined ADC.
First, the input signal is sampled by the S/H and then the held value is fed to stage 1. The following identical stages sample the residue of the previous stage and process the signal likely a two-step ADC. The S/H in each stage allows stages to operate concurrently, so that each stage is free to process a new sample as soon as its residue is sampled by the next stage. Finally, the residue is fed to a flash ADC to determine the last bits. After an initial latency of N clock cycles, one conversion will be completed per clock cycle. Therefore, the pipelined ADC could still keep high throughput rate even though the number of stages increases. Because of the feature, pipelined ADCs can generally operate at much higher sampling rates.
With the inter-stage gain amplifiers, the requirement of the comparators for the following stages could be relaxed. Therefore, we could realize a high resolution pipelined ADC by only increasing the number of stages without raising the complexity of the comparators too much. However, the additional gain amplifiers would become the dominate sources of power dissipation. Therefore, pipelined ADCs
resolution applications, pipelined ADCs need fewer circuits compared to Flash and Two-Step ADCs, since the circuit complexity for pipelined ADCs approximately increase linearity but that is exponential growth in Flash and Two-Step ADCs.
Because of the ability of each stage to operate concurrently and the tolerance of the comparator offsets, pipelined ADCs are quite suitable for high speed and medium-to-high resolution application [8].
2.3.4 Cyclic ADC
A cyclic ADC is similar to a single stage of pipelined ADCs with the output fed back to the input, as shown in Figure 2.13. It has only one stage and this stage would be repeatedly used in one cycle. When an input is sampled by the cyclic ADC, it takes N cycles to complete the output word and the delay time is the same as the pipelined ADC. However, the new input would not be sampled for a cyclic ADC before the N-bit output word is completed, so the throughput rate of the cyclic ADC is only 1/N times compared with the pipelined ADC. However, since only one stage is required, the cyclic ADC is extremely suitable for low power and low area designs.
/ S H
-k bit Sub ADC
-k bit Sub DAC
+
_ + 2k
residue
V
k bits Input
Figure 2.13 A Cyclic ADC.
2.3.5 Successive Approximation ADC
Successive-approximation ADCs apply a binary search algorithm to determine the closest digital word to match the input signal. As shown in Figure 2.14, it is also known as successive-approximation register (SAR) ADC. In the first cycle, the MSB, b1, is determined and stored in the successive-approximation register (SAR), and then b1 is fed to the D/A converter to generate a new reference value, VD/A. In the second cycle, the original input signal is compared with the new VD/A to determine b2 and then the same operation is repeated again. After N period cycles, the complete N-bit output word is determined. Successive approximation ADCs are very analogous to Cyclic ADCs, but in each cycle the former varies the reference voltage and the later varies the input signal.
Figure 2.14 (a) Successive-approximation converter and (b) transfer curve of VD/A.
2.3.6 Time-Interleaved ADC the throughput rate of the time-interleaved ADC is four times the rate of each ADC in the four channels. By using many ADCs in parallel, time-interleaved ADCs achieve high conversion rate but consume large power and area. It is also essential that the channels are extremely well matched, as mismatches will introduce tones at fs /m
2.3.6 Time-Interleaved ADC the throughput rate of the time-interleaved ADC is four times the rate of each ADC in the four channels. By using many ADCs in parallel, time-interleaved ADCs achieve high conversion rate but consume large power and area. It is also essential that the channels are extremely well matched, as mismatches will introduce tones at fs /m