Chapter 1 Introduction
1.2 Thesis organizations
This thesis discusses about the circuit design and implementation of Band-notch Low-Noise Amplifier for UWB. In chapter 2, we will review diverse topologies of notch LNA, and present our design with simulated results in TSMC 0.18 μm CMOS process. Finally, an improved circuit will be discussed in chapter 3, and then make a conclusion in chapter 4.
MB-OFDM Data Rate Parameters Data Rate
(Mb/sec) Modulation Type Coding Rate
53.3 QPSK 1/3
Chapter 2
Tunable CMOS Band-notch LNA
Low-noise amplifier (LNA) is a critical device since it’s typically the first stage in receiver. The common goals in design are:
1. Low noise figure (NF) 2. Sufficient linearity
3. Input and output matching 4. Low power consumption.
5. Gain flatness 6. Stability
2.1 The general topologies of 1
ststage in LNA
In a communication system, in order to make LNA connect to an antenna, the first problem facing is wide-band input matching.
The general topologies of 1st stage in LNA are shown in Fig. 2.1
(a) Resistive termination (b) Shunt-series feedback
(c) 1/gmtermination (d) Inductive degeneration Fig. 2.1 The general topologies for 1st stage of LNA
1. Resistive termination
Adding a 50ohm resistor to the input node of a common source amplifier, as shown in Fig. 2.1 (a). Such topology is rarely used in the LNA design since the real resistor will contribute noise and cause an unacceptable high noise figure. But the noise contribution of the terminating resistors can be neglected when an antenna is mounted directly on the amplifier.
2. Shunt-series feedback
A LNA with the shunt-series feedback topology as Fig. 2.1(b), often have high power dissipation. The cause is the bias point of input fastened with the output voltage, and hence the biasing point of system can’t be set at the optimal bias point.
In addition, the shunt series feedback topology has a stability problem in high frequency. The root cause is related to source resistance Rs, it can’t be negative, or the system will oscillate. But the parasitic component of transistor can’t be neglected in high frequency so the feedback effect would make the stability of system drop to unstable region.
3. 1/g
mtermination
This topology seems like a good choice for wide bandwidth system because the transistor’s gm is merely affected in the frequency range of UWB system. In order to make 1/ gm equal to 50Ω, gm has to be fixed at 20mS. This means the transistor size must be fixed, and it will affect the noise figure of system. Rather than other topologies, the gain of such LNA is rarely small. Therefore, there will be more than one stage in back of this topology for enhancing the overall gain.
In common gate configuration, the noise figure and matching circuits totally depend on the transistor. The (2.1) shows the noise factor of the single transistor [1].
α
+γ
= 1
F
(2.1)where γ is the coefficient of channel thermal noise and α is
0
where gm is the trans-conductance and
g is the zero-bias drain conductance.
d0 For the long channel device, γ equals to 2/3 and α equals to 1. For the short channel device, the value of γ is greater than 2/3. Based on these data, the best noise figure of this topology tends to be more than 2.2dB.Consequently, this topology can afford quite wide bandwidth impedance matching but bring a large noise figure and is difficult to achieve high gain performance.
4. Inductive degeneration
From the small signal model shown as Fig. 2.2(b), the input impedance of this architecture can be calculated as
s
At the resonant frequency, the input impedance is purely real and proportional to Ls. Therefore, this system don’t have to add additional any resistive components and it can reach the input impedance matching by choosing appropriate value of the Ls. This leads to a very good noise figure and impedance matching for a narrow bandwidth system.
However, since this topology utilizes resonance at the desired frequency, it can be used only for narrow bandwidth signals and it is not suitable for wide bandwidth applications.
Transformer feedback
Transformer feedback is the commendable topology of input matching, and it has been reported in [2], as shown in Fig. 2.2. The causes are its noise contribution (refer to T1 in Fig. 2.2) in transformer winds is relatively small, and the response of an on-chip transformer can allow the realization of an absolutely stable band-pass feedback network. Moreover, such topology can replace the multi-inductor network to get broadband input matching, and hence the additional noise and more chip area due to multi-inductor will be prevented. By the way, the input impedance with feedback is determined by the effective turns ratio of T1 (
n/k
) and the trans-conductance (g
m) of Q1Fig. 2.2 Transformer feedback
According to (2.4), the 3dB bandwidth of transformer is limited by the magnetic coupling (k) between windings. Thus, we can get k
≧
0.6 is required for full bandwidth of UWB.l
The high-k transformer design is good for reducing the pass band attenuation.
The highest magnetic coupling can achieve in virtue of overlaying transformer windings. Such technology has another advance that the chip can hence be save more.[3]
Note that the bandwidth defined by (2.4) does not account for capacitive parasites which impair the higher-frequency response. The limitation of bandwidth caused by inter-winding capacitance will be mitigated by using the transformer in the inverting configuration where each winding has one terminal at AC ground.
The trans-conductance of Q1 defines the input stage loop gain and is selected in conjunction with the effective turns ratio (i.e., n/k ~ 5.25) of T1. The magnetizing inductance of T1 matches the input impedance to 50Ω and provides a noise figure less than 3dB at the lower edge of the amplifier pass-band.
2.2 Notch filter
The notch filter is a filter that passes all frequencies except those in a stop band centered on a center frequency. Here, Fig. 2.3 (a) and (b), show the general two LC tanks of notch filter. Fig. 2.3 (c) is part of the proposed topologies of notch filter in this thesis.
Fig. 2.3 (d), shows the notch filter of Fig. 2.3 (c) with the parasitic capacitor from transistor. Its impedance is given by (2.5), and the series resonance frequency is
1
Tunable notch filter
Fig. 2.4 shows the proposed notch filter composed of Fig.2.3 (b) and (c). Rather than narrowband rejection of WLAN signal, we aim at filtering out all WLAN signals (i.e. 5.1-5.9GHz), as show in Fig. 2.5
Fig. 2.4 Proposed notch filter
Fig. 2.5 Band notch response
The notch filter 1 in Fig. 2.3, is a simple parallel circuit and its resonant frequency is given by (2.6). At its resonant frequency, the input signal will be rejected so we’ll see a notch frequency f1,as marked in Fig. 2.5.
1 2
2 3
1 2
1
f
C L
f
=LC
= =π
π
(2.6)The notch filter 2 in Fig. 2.3, tends to be a simple series circuit at high frequency.
As the tank tends to be resonant at f2, its low impedance will short the signal to ground, thus there is a notch point in Fig. 2.6. Additionally, the notch filter 2 tends to be a parallel circuit at low frequency, which is set to equal to f1. In virtue of such topology, we can get the wide band rejection nature as shown in Fig. 2.3.5. Finally, we use varactor to fulfill tunable function, as show in Fig 2.8.
There is some confusion when it comes to the derivations of the resonant frequencies of the notch filter, hence the derivations of the relevant equations for the filter is also included later.
Fig. 2.6 The spectrum of band notch filter with ideal LC components
Fig. 2.7 Tunable notch filter
(a) Tuning voltage = 0V (b) Tuning voltage = 1V Fig. 2.8 The spectrum of tunable band notch filter
Related equation derivation:
1
2.3 UWB LNA Review
In this section, we’ll discuss some diverse topologies of UWB LNA. Then, the characteristic of our design will be indicated in next section.
Fig. 2.9
Fig. 2.9 shows a LNA structure in [5], fabricated in 0.13um2 CMOS process, using cascode configuration and without notch characteristic. Cascode configuration is a typical technology in high gain, and broadband amplifier design since it can reduce the effective input capacitor and increase the output loading. In addition, the cascode structure also has good properties of reverse isolation and such characteristic is useful for broadband matching. However, it’s not good to noise figure due to the noise contribution from trans-conductance of additional transistor.
Fig. 2.10
(a) (b) Fig. 2.11
Fig. 2.11 shows a notch LNA structure in [6], fabricated in 0.35um2 SiGe BiCMOS technology ,consisting of the cascode configuration, active notch filter, and emitter follower. The notch filter sketched in Fig. 2.11(b) is reported in [7]. It synthesizes impedance that combines a series resonance, at frequency
] )
||
( 2 /[
1
π L
3C
3 +C
4C
var , and with a parallel one , at frequency 1/(2π L
3C
4||C
var). When the frequency is at series resonant frequency, the input impedance of the notch filter will greatly deteriorate the voltage gain of the LNA, thus the rejection of WLAN signal is obtained, which can be manipulated by the varactor.(a) Spectrum (b) Tuning result Fig. 2.12
(a) (b)
(c) Fig 2.13
Fig. 2.13 shows another notch LNA structure in [4], fabricated in 0.13um2 CMOS process, using passive LC tanks to achieve the notch characteristic. Such LC tank, which will be elaborated later, has not only a series resonance but a parallel resonance. However, its gain flatness isn’t good enough, as shown in Fig 2.13 (c).
2.4 Circuit implement
There are four core topologies in this thesis as list below:
1. Transformer feedback for input matching
2. Tunable notch filter for wide band rejection with tuning function 3. Cascade topology for gain improvement
4. Source follower for output matching
Furthermore, the design in this thesis is based on a finished circuit “Notch LNA”
in our lab and then makes it tunable in virtue of the adding varactor.
The prototypes and layouts of both “Notch LNA” and “Tunable band notch
LNA” are shown in Fig. 2.14 and Fig. 2.15.
Fig 2.14 (a) The prototype of band notch LNA
``
Fig. 2.14(b) The layout of band notch LNA
Fig. 2.15(a) The prototype of tunable band notch LNA
Fig. 2.15(b) The layout of tunable band notch LNA
2.5 Simulation result
In this section, the measured results are shown below.
1. TT corner
Freq. range (GHz) 3~10
S11(dB) <-8 S22(dB) <-8 S21(dB) 12 S12(dB) <-50 NF(dB) 2.4~3.2 5GHz Notch(dB) -8
Power(mW) 15.8 P1dB(dBm) -24 IIP3(dBm) -3
Table 2.1 TT Corner post-simulation summary
Fig. 2.16 (a) S-parameter under TT corner
Fig. 2.16 (b) Noise Figure under TT corner
Fig. 2.16 (c) P1dB under TT corner
Fig. 2.16 (d) IP3 under TT corner
Fig. 2.16 (e) Stability under TT corner
2. SS corner
Freq. range (GHz) 3~10
S11(dB) <-8 S22(dB) <-9 S21(dB) 10 S12(dB) <-50 NF(dB) 2.7~3.5 5GHz Notch (dB) -8
Power(mw) 15.8 P1dB (dBm) -24
IIP3 (dBm) -0.5
Table 2.2 SS Corner post-simulation summary
Fig. 2.17 (a) S-parameter under SS corner
Fig. 2.17 (b) N.F under SS corner
Fig. 2.17 (c) P1dB under SS corner
Fig. 2.17 (d) IP3 under SS corner
Fig. 2.17 (e) stability under SS corner
3.FF corner
Freq range(GHz) 3~10
S11(dB) <-7 S22(dB) <-7 S21(dB) 13 S12(dB) <-50 NF(dB) 2.3~3.2 5GHz Notch(dB) -10
Power(mW) 15.8 P1dB(dBm) -24 IIP3(dB) -5
Table 2.3 FF Corner post-simulation summary
Fig. 2.18 (a) S-parameter under SS corner
Fig. 2.18 (b) N.F under SS corner
Fig. 2.18 (c) P1dB under SS corner
Fig. 2.18 (d) IIP3 under SS corner
Fig. 2.18 (e) Stability
Comparison of UWB LNA
Spec. This
Table 2.4 Comparison of Ultra Wide-band LNA
Chapter 3 Improvement
In previous design, the band notch LNA generates a flatness response in stop band to reject the WLAN signal of IEEE 802.11a in 5 to 6GHz. However, we found there was other WLAN applications exist in the band group2 as shown in Fig. 3.1, it is the HipLAN2 of ETSI.
Moreover, we also concern the interference from GSM signal since its power is relative strong to UWB. Hence, we make an improvement in previous design regarding these considerations and the circuit as show in Fig. 3.2.
Fig. 3.1 WLAN signals allocation
Stand Area Low Band (GHz) High Band(GHz)
IEEE 802.11a North America 5.15-5.35 5.725-5.825 ETSI HiperLAN2 Europe 5.15-5.35 5.47-5.725
MMAC HiSWANa Japan 4.9-5.0 5.15-5.25
Table 3.1
3.1 Circuit analysis
In this improvement, the core what we modify are adding one more notch filter (C13 L8) and tee type matching circuit. The additional notch filter is used to reject the GSM signal (1.8GHz to 1.9GHz), and the tee type matching circuit is added to help lowering S11 of the LNA.
Fig. 3.2 Improved circuit structure
3.2 Simulation result
Freq range(GHz) 3~10
S11(dB) < -10 S22(dB) <-10 S21(dB) 12 S12(dB) <-50 NF(dB) 3.3~3.9 5GHz Notch(dB) < -8
Power (mW) 31.5 P1dB (dBm) -24
IIP3(dB) -5
Table 3.2 SS Corner pre-simulation summary
Fig. 3.3 (a) S-parameter under SS corner
Fig. 3.3 (b) N.F under SS corner
Fig. 3.3 (c) N.F under SS corner
Fig. 3.3 (d) IP3 under SS corner
Fig. 3.3 (e) Stability under SS corner
Chapter 4 Conclusion and future work
4.1 Conclusion
This thesis presents two tunable band notch UWB LNA’s based on the finished circuit “Notch LNA”. One is to reject the WLAN (5.1-5.9GHz) interference and another one is with the additional rejection aimed at GSM signal (1.8G ~1.9GHz).
According to the simulated results, the feasibility of such band notch technique is confirmed.
In addition, we’ll also discuss another topology, such as Fig 4.1. The major difference is the placement of primary winding of transformer. According to its simulation result, we can know the noise figure and gain flatness will get better, but the return loss is hard to cover full band. The root causes are:
Fig. 4.1 Tunable notch filter with topology of inductive degeneration
1. Both of the inductance and size of primary winding are decrease. So the noise figure can get better.
2. The placement of transformer is similar to the topology shown in Fig 2.1(d), which is jut suitable for the device with narrow bandwidth but without mutual inductance.
Fig. 4.2 Return loss and gain flatness
Fig. 4.3 Noise figure
4.2 Future Work
In this thesis, we have finished the design of UWB LNA’s. However, in ultra wide-band receiver architecture, there are still many important blocks needed to be implemented, such as Mixer, Synthesizer, etc. Besides forgoing, the ESD protection must be designed within the thinner gate oxide process. Finally, the EM EDA tool must be used accurately and all parasitic effects including parasitic capacitance, resistance and inductance must be considered carefully.
Reference
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