Chapter 1 Introduction
1.3 Thesis Organization
The thesis will introduce you the overview Low-Voltage SRAM design in chapter 2.
I will discuss and analyze the low-voltage SRAM development. Afterwards, how to produce the power consumption and have to take notice of the current leakage from the transistor that also writes in chapter 2.
In chapter 3, I will tell you my 8T SRAM design structure in detail. I want to do the design better and use some circuit to improve the performance in the 512Kb memory chip. The 8T SRAM chip use the pipeline structure that wishes the performance can get better and working faster. Besides, we choose the H-tree clock distribution to
Fig1.1 (a) Conventional 8T SRAM cell (b) single-ended 8T SRAM cell [1.1]
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transmit the external clock that is able to make the pipeline working preferable. Then, the 8T SRAM made Data-Aware Write-Assist (DAWA) to enhance its write ability and reduce power. Then, we use a new scheme of voltage controller that control whether boosting world-line (WL) or not to write/read ability better. Doing DAWA operation, we can’t always turn on the DAWA for long time that the cell data is flipped probably. For this reason, we design the DAWA tracking circuit to control the DAWA switch.
Finally, chapter 4 is displaying the test flow how to test the design and showing the chip measure results. We will discuss the data by real measurement and analyze the design where should modify that let the chip performance better. Chapter 5 is making a conclusion of reference in the thesis.
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Chapter 2
Overview of Low-Voltage SRAM Design in Recent Years
2.1 Introduction
The chapter first would introduce the family of memory development and discuss their identity. To realize read-disturb, read static noise margin (RSNM), write static noise margin (WSNM) definitions, and so on. We just choose major memory to realize how they operation in present IC industry.
Next, I will tell you the conventional 6T SRAM, the conventional single-ended 8T SRAM, and the new 8T disturb-free single-ended 8T SRAM basic operation. Even though two single-ended 8T structures are different, but the RSNM and WSNM is the same. Besides, I show the simulations of the 6T/8T SRAM RSNM and WSNM. Since the thesis is talking about power, we discuss the power consumption where produce in the transistor in this chapter ultimately.
2.2 Memory Family
2.2.1 Flash
Flash has developed for 20 years since in 1986 product. The main structure are NOR and NAND flash memories. Its belong Non-Volatile Memory (NVM) and play an important role on disk cashes. It also viable subsystem on PC computing and uses other applications as 3G/UMNT mobile phones. The NOR composition main make use of cellular phones or embedded application and the NAND composition is for memory cards. The NOR flash for code and storage application and the NAND flash only for data storage. [2.1][2.2]
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We simply explain the flash operation. We see the Fig. 2.1, this is a Flash cell which has two gates surrounding by dielectrics. The couple capacitor is produce between control gate (CG) and floating gate (FG). In normal state (or positively charged), the data is logic “1”. And the negatively charged state stand for the data value is logic “0” as electrics store in the FG.
For writing operation, a NOR Flash is programming by channel hot electron (CHE) injection in the floating gate (FG) at the drain side; it is eared by the flower-nordheim (FN) electron tunneling oxide from the FG to the silicon surface.
(Fig. 2.2) [2.1].
Fig. 2.1 Schematic cross section of the Flash cell. [2.1]
Fig. 2.2 NOR Flash writing mechanism. [2.1]
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For reading operation, we can measure the FG MOS transistor voltage to decide the cell data whether is logic “1” or “0”. We see the Fig.2.3 [2.1] that realize the Flash cell store logic “1” that transconductance is the same with logic “0” in current-voltage characteristic curve. Only difference is the threshold voltage shift ∆VT
that is proportional to store the electron charge Q in fixed gate bias. While the current is very high we measure that means the stored data is logic “1” in fixed bias voltage.
In other case, as we measure the current is 0 that represent the Flash cell storage logic
“0”. [2.1]
2.2.2 DRAM
Dynamic Random Access Memory (DRAM) is very important memory for PC that main application is used to most of memory for disk in this day. DARM is the Volatile Memory (VM). If you do not support the fixed voltage for it, the DRAM cell storage data can’t remain original data in last time. The DRAM structure is combined into one transistor and one capacitor as Fig. 2.4. Due to the simple composition (1T+1C) that density is very well. With SRAM comparison, the cost is cheaper than SRAM, but accesses data slower and consumes more power.
Fig. 2.3 Floating-gate MOSFET reading operation [2.1]
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Next, the DRAM cell is introduced into its operation of reading and writing. In write mode, turns on the access transistor is controlled over word-line at first. If we want to transmit the logic “0” data in the DRAM cell, first step the bit-line (Fig. 2.4) discharge to GND. Then second step, original charges in the storage capacitor are produced the discharged path passing through the access transistor to bit-line. Else if we wish to write logic “1” into the DRAM cell, we assume the storage capacitor has no charge into in beginning. The bit-line charges to the support voltage (VDD) and turns on the access transistor naturally. Then it comes into a charge path from bit-line through the access transistor and finishes the working.
In read mode, of course the cell must turn on the access transistor. The bit-line voltage always is VDD that fixed supporting voltage in stand-by mode. When in read mode, the bit-line voltage changes from VDD to 1/2VDD. Besides, the cell storage logic “1” let the bit-line voltage larger than 1/2VDD. On the contrary, the cell stores logic “0” make the bit-line voltage less than 1/2VDD. This bit-line voltage wills read the result by sense amplifier with 1/2VDD as a diving line.
But cause of the DRAM structure has a capacitor that discharges to ground for period of time. This problem makes the write “1” data in cell for long time, the capacitor voltage change floating “1” to floating “0” and finally read the cell data
Fig. 2.4 DRAM structure
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result is wrong. To solve the problem, there is a mechanism for each fixed time will be recharged once.
2.2.3 FinFET SRAM
According to Moore’s law, today the process gets smaller and smaller but cause to the physical properties discover we will meet the bottleneck below 10nm process.
Therefore, some people use the same process however the system place the way of 3D that can improve the performance. Another way is changing the MOS structure, and afresh is issued with properties, and then does modify and modeling. The structure is FinFET that is a trending in the future!
Now we begin to introduce the FinFET composition. There are three FinFETs in Fig.
2.5 [2.3]. This composition unlike planar single- and double-gate devices in plane, the channel width is placed perpendicular to the semiconductor plane. It is not only increase the drive current due to raise per unit planar area by fin-height but also reduces the delay time cause to the equation: Cload/Idrive. [2.3]
Fig. 2.5 Multi-fin FinFET structure [2.3]
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In the Fig. 2.5, the silicon fin of thickness tsi is located on an SOI wafer. The tsi is the body-thickness of the resulting double-gate structure where both gates are tied together. Current flow is parallel to the wafer plane while channel width is perpendicular to the plane. The effective channel width is equal to 2h because the height of SOI thickness also is h. Higher widths are achieved by drawing multiple fins in parallel and wrapping the gate around them. The effective channel width for a multi-fin FinFET on a given planar area of silicon is determined by h and fin-pitch p.
The minimum h required to achieve equivalent planar are efficiency is thus p/2. In other words, increasing h beyond p/2 increases area efficiency. The upper bound on h is set by the maximum fin aspect ratio (amax=Hmax/ tsi) allowed by the process. [2.3]
The design considerations for the reliable operation of the 6T FinFET SRAM circuits are provided in this section. The standard tied-gate (TG) FinFET SRAM cell is shown at Fig. 2.6 that all six transistors are sized minimum in 32nm process and Fig.
2.7 is that layout. [2.4]
Fig. 2.6 TG-FinFET 6T SRAM cells schematic [2.4]
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The idle mode leakage power consumption is reduced with the Independent-Gate (IG) FinFET 6T SRAM that can enhance the data stability and the integration density as compare to the TG-FinFET SRAM circuits. The schematic is in the Fig. 2.8 and the layout is shown at Fig. 2.9 that the six transistors also use the minimum size.
Fig. 2.7 TG-FinFET 6T SRAM cells layout [2.4]
Fig. 2.8 IG-FinFET 6T SRAM cells schematic [2.4]
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2.3 SRAM
2.3.1 6T SRAM
The 6T SRAM is the most companies using to produce SRAM memory in recent years. The construction is shown in Fig. 2.10. It is composed of two back-to-back inverters and adds one NMOS in inverter input side respectively that accomplishes the 6T SRAM structure. We usually say MP1 and MP2 are pull-up gates; MN1 and MN2 are called pull-down gates; M1 and M2 are called pass-gates in the field. In standby, the 6T SRAM setting is bit-line (BL) and bit-line-bar (BLB) is charging to VDD, but the word-line (WL) is not turning on.
QB Q
WL
BLB BL
MP2 MP1
MN2 MN1
M1 M2
VDD
Fig. 2.9 IG-FinFET 6T SRAM cells layout [2.4]
Fig. 2.10 6T SRAM cell structure
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First, we start to introduce the read operation in 6T SRAM. Above the description, the standby mode, the BL and BLB will pre-charge to VDD at beginning. As reading the cell, the selected cell WL is going high (logic “1”) that turns on the M1 and M2.
Then, the BL and BLB voltage starts to float. If we assume the Q data is logic “1” and QB is logic “0”, cause to switch on M1 the BLB voltage is going to low gradually until the voltage to GND. The cell right side BL voltage is floating high according to the Q is logic “1”. We can see the Fig. 2.11 to realize the current flows in the 6T cell.
0 1 write logic “0”, so the Q point initial value is logic “1”. Turning on the WL and BL discharge to GND but BLB still keep on VDD. Q is going to write “1” operation and the other side, QB is going to do writing “0” working. In write mode, the BL and BLB are two opposite signals. To see Fig. 2.12 that displays the write operation and current flows. The red numbers are initial values in the figure and the data will be written to the 6T cell in period.
Fig. 2.11 6T SRAM read current flow
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0 1
WL =1
BLB = 1 BL=0
MP2 MP1
MN2 MN1
M1 M2
VDD
After understanding the read/write operation in 6T SRAM, we always want to read and write data easily but these two running conflict each other. If we consider read ability well, the pull-down NMOS must be stronger than the pass-gate NMOS. Else if we wish write ability good, the pass-gate NMOS have to stronger than pull-up PMOS.
Unfortunately, we also thick about the stability in standby mode and the pull-up PMOS do not be weaker overly than pull-down NMOS. In Fig. 2.13, there are three ratios β 1, β 2, andβ 3 in blue background that are represented the proportion of standby, read, and write ability. In simple terms,β 1 value cannot much smaller; β 2
value is more smaller more better; β 3 values is more larger more better.
Fig. 2.12 6T SRAM writing current flow
Fig. 2.13 6T SRAM transistor ratios
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2.3.2 Conventional 8T SRAM
Although 6T SRAM performance is very well and simplify the SRAM, but the trend for all 3C products with the external voltage requirements are low. The 6T SRAM external power cannot too low that the reason will explain in below selection.
For working in low VDD, we try to design another SRAM cell and the 8T SRAM is produced directly. In Fig. 2.14 is shown the conventional 8T SRAM. [2.5]
QB Q
This 8T cell (Fig. 2.14) adds two-transistor read stack in the conventional 6T cell.
The below transistor gate of the stacking-transistor is connected to the node of Q.
While write operation, we just turn on the WWL directly and RWL not turn on. Then the working way is the same by the conventional 6T SRAM cell. Afterwards, the read operation is turning on RWL and turning off WWL that the current only through two stack transistors if the Q value is logic “1”, then RBL is pulled down to logic “0”. If Q is logic “0” that RBL voltage is a floating “1”. In addition, the two cross-coupled inverters of 8T SRAM condition is alike standby state so that don’t have read-disturb problem.
The Fig. 2.15 [2.5] is the conventional single-ended 8T SRAM layout. The compact layout is the 6T cells at the left side that just take on the RWL and RBL at the right side, and then the layout is accomplished. The WWL is 6T cells’ WL. Similarly, the WBL and WBLB are 6T cells’ BL and BLB separately.
Fig. 2.14 Conventional 8T SRAM
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However, the thesis 8T SRAM cell schematic is not the above description. We use the different design way and have the same benefits, for example: Read Static Noise Margin (RSNM) is better than 6T SRAM and can work in low VDD. The 8T SRAM we use will introduce in chapter 3.
2.4 SRAM Static Noise Margin (SNM)
Static Noise Margin(SNM) means that the maximum DC noise voltage. In simple words to say that is a bit-cell can be tolerated by the moaximum noise value. If exceed the value, then the storage in the cell will be filed and be incorroected.
Measure the SNM is getting form Voltage Transfer Curve (VTC) that usually is called as “butterfly curve” and SRAM cell must have two inverters that place back-to-back.
We show Fig. 2.16 that is the VTC of inverter. Besides, we use the example for 6T cell explain SNM for below article.
Fig. 2.15 Conventional 8T SRAM layout [2.5]
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2.4.1 Hold Static Noise Margin (HSNM)
HSNM is means when the SRAM cell in the stand-by mode. The WL signal is logic
“0” and do not turn on the cell pass-gate. Next, BL and BL signals are pre-charged logic “1”. Cause of SNM have to use DC voltage to measure, we use the way [2.7] to test the value that shown in Fig. 2.17.
WL =0
BLB=1 BL=1
MP2 MP1
MN2 MN1
M1 M2
VDD
+
+ - VR
VL
Fig. 2.16 Voltage transfer curve of inverter [2.6]
Fig. 2.17 HSNM detected circuit
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The method of measuring HSNM is connected to two DC noise source with 6T cell in Fig. 2.17. We sweep the DC noise source form high voltage (ex: 1V) to low voltage (ex: 0V), then observing the result of VR and VL voltage. These results individually use the VDD and VR/VL to do two axes that accomplish the voltage transfer curves.
VTCs overlapping outcome that the shape like a butterfly, so the mapping also say
“butterfly curve” as shown in Fig. 2.18. There are two SNM in the figure, we choose the smaller SNM as the cell SNM.
2.4.2 Read Static Noise Margin (RSNM)
The method is the same as the above description that difference is initial condition.
We turn on the WL in read mode and per-charge BL and BLB to VDD are changeless in 6T cell that show in Fig. 2.19. Besides, the butterfly curve is shown in Fig. 2.20.
Expressly, the RSNM is worse than HSNM in 6T cell. The reason is that WL turns on the M1 and M2, so produced the current path pass through the pull-down NMOS:
MN1 and MN2. Pull-down NMOSs have an equivalent resistor due to the VR/VL
voltage cannot low to GND. This voltage difference from the minimum voltage to GND we are called read-disturb.
Fig. 2.18 The butterfly curve in hold mode VR (V)
18 but the 8T cell will solve the read-disturb problem due to the initial condition is the same in hold mode. The 8T cell in read mode just turns on the RWL and the inside WWL don’t turn on at Fig. 2.14. The 8T RSNM is shown in Fig. 2.21 and the thesis 8T cell also have the same conclusion.
Fig. 2.19 RSNM detected circuit
Fig. 2.20 The butterfly curve in read mode (6T) VR (V)
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2.4.3 Write Static Noise Margin (WSNM)
In write mode, we assume VR voltage is logic “0”, then VL is logic “1”. Let the WL voltage go high and switch on M1, M2. BL is logic “1” according to VR voltage, for the same reason that LBL is setting logic “0”. The writing operation is ready and use again DC source to input two inverters gate detecting VR/VL variation as shown in Fig.
2.22. As a result of the right-side inverter setting is the same with RSNM, so the one of Voltage Transfer Curve (VTC) is equal in Fig. 2.23.
WL =1
Fig. 2.18 The 8T cell butterfly curve in read mode Fig. 2.21 The 8T butterfly curve in read mode
Fig. 2.22 WSNM detected circuit
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2.5 SRAM Write Margin (WM)
Write ability to use other methods this way is to Write Margin (WM). How to survey the value in a cell? We read on. First, we let the BLs to high level (VDD), and sweep down BL form VDD to GND. When the cell storage value is flipped all at once, now the BL voltage is defined as WM. Or change another way to say, we test the BL voltage start from GND to rise gradually as we detect the cell write fail that the voltage is WM. We see the Fig. 2.24 [2.8] to realize the definition.
VR (V) VDD (V)
Fig. 2.23 The write-1 VTC
Fig. 2.24 Diagram of new write margin [2.8]
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2.6 SRAM Array Structure
Cause of the memory in 3D products is very important that has to save or read many data in the period time, so the designed memory system need to a lot of areas for memory cells. Nevertheless, there is the way to design the memory array structure already and follows it can make well easily. The memory array basic structure is in Fig. 2.25. We always put many memory cells together that is called SRAM array if the memory is by SRAM. The SRAM array left side places the row decoder that working is decoded one signal for address to select a cell word line. Then, the SRAM array below puts a column decoder that running one signal by address to choose a cell bit line. To select one word line and one bit line their across a cell is called storage cell that will is going to write or read operation. If the working is read that pass through the sense amplifiers and comes out after some gating computations.
To design a memory system we have many tests to test. Usually one circuit has one critical path to use tracing a lot of problems. Of course, SRAM organization also has a critical path as in Fig. 2.26. Most of critical paths are the longest of total system by designer. The reason is that the longer path will go through more gates in general. The
Fig. 2.25 Basic SRAM organization
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critical path starts from address and then sequence passes through address register, row decoder, column mux., sense amplifiers, comparator, and finally input/output register in Fig. 2.26. Most of delay is though the SRAM column, column mux., and
critical path starts from address and then sequence passes through address register, row decoder, column mux., sense amplifiers, comparator, and finally input/output register in Fig. 2.26. Most of delay is though the SRAM column, column mux., and