Thesis Organization

This thesis is divided into five chapters. In Chapter 2, the operation principle of the TFTs is introduced. The measurement and extraction of electrical parameters are also describes. The experiments and equipments for a-IGZO TFTs is described in Chapter 3. In Chapter 4, the electrical properties of a-IGZO films are presented. First, the effects of inlet gas flow ratio and annealing conditions are discussed. Second, the a-IGZO interface conditions and the effects of different source and drain materials on the electrical properties of a-IGZO TFTs are also presented. Finally, conclusions and future works are summarized in Chapter 5.

Chapter 2

Principles and Characterizations of TFTs ______________________________________

In this chapter, the principle of TFTs is first introduced. Second, the measurement and the electrical parameter extraction; including threshold voltage, subthreshold swing, filed-effect mobility and on/off current ratio are presented.

Finally, the surface morphology measurement using the atomic force microscope (AFM) and the contact angle measurement are described.

2.1 Operation Principle of TFTs

Conventional TFTs compose of a semiconductor layer, a gate insulator layer, and three electrode terminals including gate, source and drain. The bottom-gate-top-contact TFT structure is shown in Fig. 2-1.

Fig. 2-1 A bottom-gate-top-contact TFT structure.

Transistors can be classified into the depletion-mode and the enhancement-mode, based on whether drain current flows through TFT when no voltage is applied to gate electrode. For the depletion-mode TFT, when the device is on, drain current flows through the device when no gate voltage is applied. For the enhancement-mode TFT, when the device is off, only leakage current flows through the TFT without applying the gate voltage.

The energy band diagrams through the gate of an n-type enhancement-mode TFT is introduced to explain the three modes of TFT operation, as shown in Fig. 2-2.

(a) (b) (c)

Fig. 2-2 The semiconductor energy band diagram when (a) unbiased, (b) negative gate voltage bias, (c) positive gate voltage bias.

When no gate voltage is applied, the semiconductor is in an equilibrium state. When a negative gate bias is applied, delocalized electrons in the channel are repelled from the semiconductor/gate interface and create a depletion region of positive charge, as indicated by the positive curvature in the conduction band and valance band near the insulator shown in Fig. 2-2 (b).

When a positive gate bias is applied, delocalized electrons in the channel are attracted to the semiconductor/insulator interface, creating electron accumulation at the interface, as indicated by the negative curvature in the conduction band and valance band near the insulator in Fig. 2-2 (c). These accumulated electrons at the semiconductor/insulator interface provide a current conduction path and form the channel.

2.2. Electrical Measurement

The device electrical properties were measured by a Keithley 4200 IV analyzer in a light-isolated probe station at room temperature. In I_DS-V_GS measurement, the typical drain-to-source bias was swept from V_GS = -10 V to VGS = 30 V. In IDS-VDS measurement, the typical drain-to-source bias was swept from VDS = 0 V to VDS = 40 V.

2.3. Parameter Extraction Method

In this session, we describe the methods of typical parameters extraction such as threshold voltage (V_th), subthreshold swing (SS), On/Off current ratio (Ion/Ioff) and field effect mobility (µFE) from device characteristics.

2.3.1. Determination of the V

th

Threshold voltage (Vth) was defined from the gate to source voltage at which carrier conduction happens in TFT channel. Vth is related to the gate insulator thickness and the flat band voltage.

Plenty of methods are available to determine V_th which is one of the most

important parameters of semiconductor devices. This thesis adopts the constant drain current method, that is, the voltage at a specific drain current NID

is taken as Vth, that is, Vth = VG (NID) where Vth is threshold voltage and NID

stands for normalized drain current. Constant current method is adopted in most studies of TFTs. It provides a V_th close to that obtained by the complex linear extrapolation method. Generally, the threshold current NID = ID/(W/L) is specified at 1 nA in linear region and at 10 nA in saturation region; W and L represent for TFT channel length and width, respectively.

2.3.2. Determination of the Subthreshold Swing

Subthreshold swing (SS, V / dec.) is a typical parameter to describe the control ability of gate toward channel which is the speed of turning the device on and off. It is defined as the amount of gate voltage required to increase and decrease drain current by one order of magnitude. SS is related to the process, and is irrelevant to device dimensions. SS can be lessened by substrate bias since it is affected by the total trap density including interfacial trap density and bulk density. In this study, SS was defined as one-half of the gate voltage required to decrease the threshold current by two orders of magnitude (from 10^-8A to 10^-10A). The threshold current was specified to be the drain current when the gate voltage is equal to Vth.

2.3.3. Determination of the Field-Effect Mobility

Typically, the field-effect mobility (µFE) is determined from the transconductance (g_m) at low drain bias (V_D = 0.1 V). The TFT transfer I-V characteristics can be expressed as

2 ] the drain current can be approximated as:

D

2.3.4. Determination of On/Off Current Ratio

Drain on/off current ratio is another important factor of TFTs. High on/off current ratio represents not only the large turn-on current but also the small off current (leakage current). It affects AMLCD gray levels (the bright to dark state number) directly.

There are many methods to determine the on and off currents. The practical one is to define the maximum leakage current as off current when drain voltage is applied at 4.5 V.

2.4. Surface Morphology Measurement

The Digital Instruments Dimension 300 atomic force microscope (AFM) was used to characterize the surface morphology of the a-IGZO thin films.

Fig. 2-3 A schematic model of AFM.

The tapping-mode scanning prevents the probe from damaging the sample surface and can get more precise surface topographic information. In the tapping-mode, the probe oscillates up and down regularly. The cantilever vibrates at various frequencies depending on the magnitude of the van der Waals force between the cantilever tip and the sample surface. A laser beam reflected by the cantilever detects the tiny vibration of the cantilever, as shown in Fig. 2-3.

The feedback amplitude and the phase signals of the cantilever were recorded by the computer. The amplitude signals provide the morphology information and

the phase signals reveal the material information.

2.5. Contact Angle Measurement

The contact angle is defined by the edge of a liquid droplet on the surface of flat sample; it is formed between the liquid/solid interface and the liquid/vapor interface as illustrated in Fig. 2-4. The static measurement mode is illustrated with a small liquid droplet laying on a flat horizontal solid surface.

The static measurement mode is used to estimate wetting properties of a localized region on a solid phase.

Fig. 2-4 The contact angle formation of liquid on solid surface

The contact angle is specific for any given system and is determined by the interactions across the gas-solid-liquid interfaces. The indices s and l stand for

solid and liquid respectively. The symbols σ_s and σ_l denote the surface tension components of the two phases; the symbol γsl represents the interfacial tension between the two phases, and θ stands for the contact angle corresponding to the angle between vectors σ_l and γ_sl. The relationship between these parameters is the Young’s equation (σ_s = γ_sl + σ_l×cosθ).

Chapter 3

Experimental Methods _________________________________________

The experimental methods of the fabrication of the a-IGZO TFT are described. Besides, the principle of sputtering system including the RF sputtering and the DC sputtering, is described,

3.1. a-IGZO TFT Device Fabrication

(1) Substrate Cleaning

The detail sequence to clean the n⁺ heavily doped silicon (Si) is:

Step 1: Clean Si wafer by DI water for 3 mins

Step 2: Clean Si wafer by DHF solution for 10 seconds

Step 3: Use N2 purge to dry the Si wafer; place them into a glass container with a cover.

Step 4: Put the glass container into an oven at 100°C for 1 min

(2) Preparation of Gate Insulator Layer

A 300 nm thick silicon oxide (SiO2) for the gate dielectric was thermally grown in the horizontal furnace by using the low pressure chemical vapor deposition (LPCVD) method. A high quality insulator is required in order to suppress the gate leakage current.

(3) Device Processing Steps

A typical a-IGZO TFT processing flow chart is shown below.

Fig. 3-1 The flow chart of typical a-IGZO TFT device fabrication

Fig. 3-1 shows the preparation of the bottom gate a-IGZO TFT structure used in this study. A heavy doped (N⁺) prime Si wafer with 300 nm thermal oxide layer was selected as the gate electrode and insulator, respectively.

Following, the 40 nm thick source and drain electrodes were deposited through stencil mask openings. The deposition methods for different source and drain are shown in Table 3-1. Finally, a 50 nm thick a-IGZO (In:Ga:Zn = 1:1:1) thin-film was deposited by sputter at room temperature. The RF sputtering was

used for reducing the charges accumulated on the a-IGZO target. The deposition was done with a continuously gas flow of argon and oxygen without intentional substrate heating.

Table 3-1 The electrode fabrication methods.

Finally, the devices were thermally-annealed by a tube furnace in the nitrogen atmosphere at 350°C for defect elimination. In the nitrogen atmosphere at high temperature. Oxygen molecules with only partial bonding on the a-IGZO thin film surface will outgas, and the semiconductor characteristics can be improved.

The channel width (W) of the device were of 600 µm and the channel lengths (L) are 200, 400, 600, 800 or 1000 µm.

Electrical measurement of the a-IGZO TFT was carried out with a probe station system located in a light tight box. The electrical properties of TFTs were measured by a PC controlled Keithley 4200 semiconductor parameter analyzer. For measuring the TFT transfer characteristics, the drain-to-source voltage (VDS) was changed in between 1 and 11 V. The gate-to-source voltage

(V_GS) was varied from -10 V to 30 V. All measurements were done at room temperature in ambient air.

3.2. Sputtering

3.2.1. RF Sputtering

RF sputtering can be applied to the deposition of both insulating and conducting materials. Figure 3-2 shows a RF sputtering system, the substrate is located above the target so that the sputtered atoms can be deposited on to the substrate. A RF power supply generates plasma at the frequency of 13.56 MHz.

The plasma creates ions which are accelerated towards the target by a negative DC bias on the target. The ions bombard the target surface and dislodge the target atoms, which then deposit onto the substrate. The sputtering is performed in vacuum, typically between 1 mTorr and 50 mTorr. A lower chamber pressure increases the mean free path, which is the distance between collisions, so that the sputtered target atoms can reach the substrate without scattering away.

Fig. 3-2 Schematic RF sputtering system.

3.2.1. DC Sputtering

DC sputtering has the advantage of higher deposition rate and is less expensive than RF sputtering. A DC sputtering system is shown in Fig. 3-3, the substrate is located above the target and acts as the anode. DC sputtering is commonly applied to deposit conductive materials.

Fig. 3-3 Schematic DC sputtering system.

Chapter 4

Results and Discussion ______________________________________

4.1. The Effects of Oxygen Flow Rate and Post-Annealing on a-IGZO TFTs

4.1.1. Introduction

The carrier source of Si and metal oxide is shown in Fig. 4-1. For Si, the carriers are resulted from impurity doping as shown in Fig. 4-1 (a). Electrons dominate the carrier transport for phosphorous-doped Si. Carrier transport is dominated by holes for boron-doped Si. For metal oxide, the carrier concentration is related to the oxygen vacancy; one oxygen vacancy provides two electrons, as shown in Fig. 4-1 (b).

characteristics are strongly associated with the a-IGZO film. The reactions on film surface dominate the threshold voltage (V_th) shift. The oxygen absorption changes the carrier concentration. The oxygen absorption forms depletion layer, resulting in Vth shift.

The oxygen absorption accompanies partial charge transfer, Vth varies at different oxygen flow rate implies the change in carrier concentration during the absorption and desorption processes. When the oxygen flow rate increases, the channel carrier concentration decreases because of less oxygen vacancies in a-IGZO film. Therefore, higher voltage is needed to turn on the channel.

The electrical characteristics of IGZO film can be controlled by varying the deposition conditions (Ar flow rate and O2 flow rate). When the oxygen flow rate is low, IGZO film is not applicable for TFT channel layer because the film

conductivity is high. When oxygen flow rate is high (over 8 sccm), IGZO film becomes insulator. In intermediate oxygen flow rate (5~8) sccm, IGZO shows semiconductor characteristics and is suitable for channel layer. It is considered that the low oxygen flow rate increases the electrical conductivity of the deposited film.^1,5 In the case of Ar gas flow, even though it is not strongly related to electrical property of IGZO film, it is one of the key parameter to control the uniformity of TFT behavior. Fig. 4-2 shows that only in a proper range of P_O2 will the a-IGZO exhibit the semiconductor characteristics.⁴ In our experiments, several oxygen flow rates (0 sccm, 0.2 sccm, 0.4 sccm, 0.6 sccm, 0.8 sccm) were adopted so as to prepare the a-IGZO TFTs with various electrical characteristics.

Fig. 4-2 Electrical property of IGZO TFT as a function of oxygen and argon flow rate during deposition.⁶

4.1.2. Results and Discussion

4.1.2.1. Determination of the Deposition Rate

First, the deposition rate of IGZO was determined by measuring the film thickness with the AFM. The AFM results of a-IGZO film thickness are shown in Fig. 3-3. The deposition rate is about 5.933 nm/min for oxygen flow rate = 0 sccm device and 3.537 nm/min for oxygen flow rate = 0.6 sccm device.

(a)

(b)

Fig. 4-3 The AFM result of (a) 0 sccm O2 device deposited for 6.5 mins.

(b) 0.6 sccm O₂ device deposited for 8 mins

4.1.2.2. The Effects of Oxygen Flow Rate on a-IGZO TFTs

The a-IGZO TFTs were operated in enhancement mode. The SiO2 gate insulator is 100 nm thick and the post-annealing time is 1.5 hours. Good electrical characteristics like large on-state drain current, small threshold voltage, and low threshold voltage were obtained when the oxygen flow rate is 0 sccm, as shown in Fig.4-4.

-10 0 10 20 30

Fig. 4-4 The a-IGZO TFT output characteristics for different oxygen flow rates.

As a result, under the same post-annealing time, V_th is smaller for smaller oxygen flow rate. The decrease of Vth is due to the mobile carrier increase.

The mobile carrier increase in channel relates to the oxygen flow rate and affects the channel/dielectric interface by changing the density of interface states. In other words, less oxygen vacancies are filled when the oxygen flow rate is smaller. The oxygen vacancies provide electrons and increase the channel carrier concentration, leading to a smaller V_th.

4.1.2.3. The Effects of Post-Annealing on a-IGZO TFTs

TFT based on AOSs (e.g. IGO ZTO, ZIO) sputtered in pure Ar requires high annealing temperature (T > 300 ˚C) to exhibit satisfactory electrical characteristics; including better saturation current, smaller hysteresis, and Vth. The post-annealing effects on device with 300 nm SiO2 gate insulator is shown in Fig. 4-5. V_th shifts negatively after post-annealing because post-annealing leads to the lattice structure rearrangement, structural relaxation, and the improved a-IGZO bonding. Post-annealing improves the channel/dielectric interface; and the charge trapping defects are decreased.

The electrical output characteristics for devices post-annealed for 2 and 3 hours are compared in Fig. 4-6. Annealing causes modification of the semiconductor/insulator interface, local atomic rearrangement and improved bonding. Three-hour annealing is the appropriate for a-IGZO TFT with a 300 nm SiO2 gate insulator. Vth shifts negatively to be near 0 V after the thermal treatment.

-20 -10 0 10 20 30 40

Fig. 4-6 The output electrical characteristic comparison for a-IGZO TFTs post-annealed for 2 and 3 hours.

4-1-3. Conclusions

The oxygen flow rate was varied to examine oxygen absorption effect.

The Vth changes with the oxygen flow rate. The oxygen vacancies provide electrons and increase the channel carrier concentration, leading to a smaller V_th. Post-annealing improves the crystallinity in a-IGZO because of the semiconductor/insulator interface modification and local atomic rearrangement and the threshold voltage can be adjusted to be near 0 V.

It is found that IGZO thin film transistors are very sensitive to oxygen and can be used as oxygen or pressure sensors.⁹

4.2. The Interface Modification for a-IGZO TFTs

4.2.1. Introduction

Research for a-IGZO TFT was focused on the intrinsic limitations of semiconductor. A large Vth is still an issue for a-IGZO TFT. It is noteworthy that a high interface trap density at the semiconductor/dielectric interface increases the V_th. A large V_th leads to the “hard saturation” phenomena in the electrical output characteristics. Besides, a poor dielectric layer quality leads to the increase of gate leakage current.

In this session, the a-IGZO TFT with the dual-stack structure is introduced, as shown in Fig.4-7. A buffer layer and the gate dielectric insulator were stacked up. The buffer layer is an interface modification layer. The buffer layer materials used in this study were hafnium oxide (HfO₂), aluminum oxide (Al2O3), and hexamethyldisilazane (HMDS). Device with only the SiO2 gate insulator is for comparison.

Fig. 4-7 The dual stack a-IGZO TFT structure.

The HfO2 and Al2O3 buffer layers are both 10 nm thick, and are deposited by the e-gun evaporation on SiO2 for the a-IGZO/gate dielectric surface treatment, as shown in Fig. 4-7. The series capacitance of the SiO₂/buffer layer was dominated by the thicker 300nm SiO2 and the contribution of the thinner buffer layer was estimated to be of less than 10 %.

4.2.2. Result and Discussion

The buffered-TFT output characteristic comparison is shown in Fig. 4-8.

It is noticeable that ID of the HMDS-buffered a-IGZO TFT is increased.

-20 0 20 40 10^-13

10^-11 10^-9 10^-7 10^-5

I D

VG SiO2

Al₂O3 HfO2

HMDS

Fig. 4-8 I_D-V_G curve comparison of the buffered-a-IGZO TFTs.

The contact angle measurement result is shown in Fig. 4-9. The water drop on HMDS has the largest contact angle on the HMDS surface, indicating that a-IGZO has improved interfacial condition when it is stacked with a hydrophobic material.

(a) (b)

(c) (d)

Fig 4-9 Contact angle image for water drop on the (a) Al2O3, (b) HfO2, (c) HMDS, and (d) SiO2 surface.

Table 4-1 Contact angle of different buffer layer surface.

The performance comparison of a-IGZO TFT with the interface modification layer is shown in Table 4-2. The mobility of the HDMS-buffered TFT was enhanced to 13.67 cm²/Vs.

Table 4-2 The performance of the a-IGZO TFTs with the interface modification layer.

4.2.3. Conclusion

A dual stack TFT structure is introduced to examine the properties of the a-IGZO/gate insulator interface. The interface modification materials adopted in this session are HfO₂, Al₂O₃, and HMDS. As a result, HMDS improves the field-effect mobility of the a-IGZO TFT. All buffered-TFTs have higher mobility than TFT without the interface modification, indicating that the gate insulator/active layer interface is improved.

From the contact angle measurement; HMDS surface has the largest contact angle for the water drop, indicating that a-IGZO has improved interfacial condition when it is stacked with hydrophobic material HMDS.

The proposed dual layer structure has shown a great potential for the advanced AMLCD technology since the output electrical characteristics of a-IGZO TFTs are greatly related to the conditions of the a-IGZO semiconductor/gate insulator interface.

4.3. The Effects of Source and Drain Electrodes on a-IGZO TFTs

4.3.1. Introduction

The unmatched source/drain electrodes lead to the high series contact resistance, causing the current suppression phenomena. Furthermore, a high contact resistance induces the current crowding effect and increases the Vth. Thus, a high efficient contact is necessary to attain electrical properties.

For a-Si:H TFTs, the source to drain resistance is influenced by the contact resistance between n+ a-Si:H and the source/drain metal; by the bulk resistance

of the n+ a-Si:H film, by the interface effect between n+ a-Si:H and source/drain electrodes, and by the intrinsic a-Si:H layer sheet resistance.

Unlike a-Si:H TFTs, the proposed a-IGZO TFT does not have a highly doped ohmic layer, the source to drain resistance is affected by the interface properties between intrinsic a-IGZO and the source/drain metal. These

Unlike a-Si:H TFTs, the proposed a-IGZO TFT does not have a highly doped ohmic layer, the source to drain resistance is affected by the interface properties between intrinsic a-IGZO and the source/drain metal. These

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