Chapter 1 Introduction
1.3 Thesis Organization
In this thesis, the photo behaviors of low-temperature polycrystalline silicon thin film transistors (poly-Si TFT) under front and back light illumination were studied.
Furthermore, the models of electrical characteristics of poly-Si TFT under
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illumination were investigated and established in detail. In addition, the photo leakage behaviors after DC stress degradation are also examined. Meanwhile, several optical sensor applications were developed in this work.
This dissertation is divided into seven chapters. It can be summarized in Fig. 1-4.
The dissertation is organized in to the following chapters: In chapter 1, the general background and overview of low temperature polycrystalline silicon thin-film transistors are introduced. In chapter 2, the experimental, such as the fabrication and the measurement of the devices, is described. In chapter 3, photosensitivity analysis of low-temperature poly-Si thin film transistor based on Unit-Lux-Current is investigated. In chapter 4, dependence of photosensitive effect on the defects created by DC stress for LTPS TFTs is studied. In chapter 5, investigation of backlight sensing in Poly-Si TFTs is presented. In chapter 6, characterization of thin film transistor for optical sensor application is studied. Finally, the summarization of all experimental results in this dissertation and the suggestions for the future work are presented in chapter 7.
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Figure 1-1 (a) Model for the crystal structure of polysilicon films. (b) The
charge distribution within the crystallite and at the grain boundary. (c)
The energy band structure of the polysilicon crystallites.
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Figure 1-2 Three possible mechanisms of leakage current in poly-Si TFTs, including thermionic emission, thermionic field emission and pure tunneling.
1 2
3 2 1
3 Ec
Ev Et
Leakage Current Mechanism (1) Thermionic emission (2) Thermionic field emission (3) Pure tunneling
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Figure 1-3 The poly-Si density of states distribution.
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Figure 1-4 The figure illustrating the structure of this dissertation.
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Chapter 2
Experimental
2.1 Device Fabrication
The process flow of TFTs is described below. Top gate LTPS TFTs with width/length dimension of 20µm/5µm were fabricated using low temperature process.
Firstly, the buffer oxide and a-Si:H films with thickness of 50 nm were deposited on glass substrates with PECVD. The samples were then put in the oven for dehydrogenation. The XeCl excimer laser of wavelength 308 nm and energy density of 400 mJ/cm2 was applied. The laser scanned the a-Si:H film with the beam width of 4 mm and 98% overlap to recrystallize the a-Si:H film to poly-Si. After poly-Si active area definition, 100 nm SiO2 was deposited with PECVD as the gate insulator. Next, the metal gate was formed by sputter and then defined. For n-type devices, the lightly doped drain (LDD) and the n+ source/drain doping were formed by PH3 implantation with dosage 2 × 1013 cm-2 and 2 × 1015 cm-2 of PH3 respectively. The LDD implantation was self-aligned and the n+ regions were defined with a separate mask.
The LDD structure did not use on p-type devices. The p+ source/drain doping was done by B2H6 self-align implantation with a dosage of 2 × 1015 cm−2. Then, the interlayer of SiNX was deposited. Subsequently, the rapid thermal annealing was conducted to activate the dopants. Meanwhile, the poly-Si film was hydrogenated.
Finally, the contact hole formation and metallization were performed to complete the fabrication work. The structure cross section view for the n-type poly-Si TFT is given in Fig. 2-1.
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2.2 Equipment and Experiment Setup
In this section, the equipments to measure the device characteristics, namely the transfer behavior ID-VG curves and the capacitance curves, are described. In addition, the apparatus to DC stress the device is also illustrated. The ID-VG curves for the devices are measured by the Agilent 4156A precision semiconductor parameter analyzer. The C-V curves of the gate-to-source capacitance CGS and gate-to-drain capacitance CGD before and after stress with different frequencies are measured with the HP 4284A precision LCR meter. Before measuring the capacitance behavior, for every frequency the measure correction is performed with the open-circuit and short-circuit mode respectively for the needles before and after probing the electrode to eliminate the effect of the parasitic components in the surrounding and during probing. The DC stress is performed by the Agilent 4156A precision semiconductor parameter analyzer, which is the same one to measure the transfer characteristics.
The light was collimated and focused onto the device with top face white light illumination. Photo leakage current was induced by a halogen lamp irradiation stream with several neutral density filters (light intensity ranging from dark to 31320 lux) through the objective of a microscope, and the light intensity was measured by a digital luminous flux meter. Fig. 2-2 shows the photo leakage current, the power variation spectrum of the front light source in the range of 350-750nm.
The light was collimated and focused onto the device with bottom face white light illumination. However, compare with front light source we use halogen lamp irradiation, we use white light-emitting-diode (LED) as the back light source in our experiments. The white light LED backlight spectrum in the range of 350-750nm is also shown as Fig. 2-3.
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2.3 Extraction Methods of Device Parameters
Three important device parameters are extracted and studied in this work: the threshold voltage VTH, the sub-threshold swing S.S., and the field effect mobility μFE. Plenty methods are used to determine VTH, which may be the most important parameter in application. In most of the researches on TFT, the constant current method is adopted. In this work the threshold voltage is determined by this method, which extract VTH from the gate voltage at the normalized drain current ID=10 nA for VD=0.1V.
Sub-threshold swing S.S. (V/dec), is also a typical parameter to describe the control ability of gate toward channel. The sub-threshold swing should be ideally independent of drain voltage and gate voltage. However, in reality, the sub-threshold swing might increase with drain voltage due to short-channel effects. It might as well be affected by the serial resistance and interface traps and therefore become related to the gate voltage. In this work, it is defined as the minimum amount of gate voltage required to increase drain current by one order of magnitude.
The field effect mobility,
μ
FE, is determined from the maximum transconductance gm at low drain voltage, which in this work 0.1 V is used. The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, so the first order the first order I-V relation in the bulk Si MOSFETs can be applied to the poly-Si TFTs,which can be expressed as ]
2
gate oxide capacitance per unit area, W is channel width, L is channel length, VTH is the threshold voltage. If the drain voltage VD is much smaller compared with (VG-VTH), then the ID can be approximated as D FE ox VG VTH VD
L C W
I =μ ( − ) Therefore,
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the electron field effect mobility can be expressed as m
D
transconductance is defined as V const ox FE D
G
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Figure 2-1 The cross-section views of n-channel LTPS TFTs with LDD
structure.
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Figure 2-2 The photo leakage current and the power variation spectrum of
the light source.
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Figure 2-3 Emission spectrum of a phosphor-based white LED.
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Chapter 3
Photosensitivity Analysis of Low-Temperature Poly-Si Thin Film Transistor Based on Unit-Lux-Current
3.1 Introduction
Low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) have attracted much attention for Active Matrix Liquid Crystal Display (AMLCD) and Active Matrix Organic Light Emitting Diode (AMOLED) applications due to the high mobility and the capability of realizing integrated circuits on glass. It could reduce the difficulties of the connection of the surrounding circuits and the cost of the panel [3.1].
The photosensitivity of LTPS TFTs is a significant design consideration for achieving high image quality display panels since it will affect the leakage current. Furthermore, several ambient light sensors using the off current of LTPS TFTs have been reported [3.2-3.7]. Thus, the photosensitive behavior of LTPS TFT off current is of great interest. However, this photo-induced leakage current behavior is not included in the present SPICE device model. In this work, a new parameter is used to analyze the effects of illumination on LTPS TFTs. It’s dependence on the gate, drain bias and temperature. An equation is provided to properly describe ULC under various bias and temperature conditions for further exploration of photo leakage behaviors. A qualitative deduction is developed to account for the photo leakage mechanism. In addition, since LTPS TFTs suffer from huge variation owing to the diverse and complicated grain distribution in the poly-Si film [3.8], the ULC variation will also be discussed.
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3.2 Classification and Characterization of Photosensitivity 3.2.1 Sensing Area Consideration
Before the mechanism of photosensitivity is discussed explicitly, it should be first examined where is the most sensitive to the illumination inside LTPS TFTs. A special layout of the TFT with U-shaped source and drain electrodes configuration is adopted in this work, as shown in Fig. 3-1. Twenty-five TFTs are arranged in parallel and separated into two groups. The upper group consists of twelve TFTs and the lower one contains thirteen TFTs. The inner electrodes (about distance 33um) of the TFTs in these two groups are shorted together and so are the outer electrodes (about distance 59um) to form the U-shaped TFT.
An irradiation optical beam with 25µm light spot radius has been used to directly shine on the device. By scanning the beam along the channel direction of U-shaped TFT, the leakage currents of the LTPS TFT are measured in two cases with the inner or the outer electrodes as drain. As shown in Fig. 3-2, anomalous two peaks of the off current are observed. When the measurement is performed with outer electrodes as drain, the distance is larger, about 66um. On the other hand, when the inner electrodes are used as the drain, the distance is shorter, about 32um. The distance between the pair peaks is consistent with device’s real junction distance. It reveals the photo-induced current happens only at the drain side. Therefore, the following discussion of the photosensitivity mechanism will focus only on the drain region.
3.2.2 Definition of the index for photosensitivity and analysis
The typical ID-VG transfer characteristics of the LTPS TFT under illumination from dark to 31320 lux are shown in Fig. 3-3. It can be seen that the off current increases with the intensity of the incident light and it has weak gate bias dependence under
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higher ambient light intensity. There are several parameters can be use to describe this behavior of the photo-induced off current. To discuss photo effect of TFTs, the previous study [3.9] used an index RL/D defined as the ratio of the current under illumination (ITotal) to the current in the dark (IDark). RL/D is suitable to evaluate the performance of light sensors. However, it may not be proper to be used to analyze photo leakage mechanism. As shown in Fig. 3-4, because ITotal is less dependent on the gate voltage, RL/D is mostly determined by the behavior of IDark. It can not reflect photo behaviors of TFTs. Therefore, for our discussion, it may be necessary to find another index which can eliminate the influence of IDark.
Fig. 3-5 shows the relationships between drain current and illumination intensity for several bias conditions in the off region. It can be seen that all drain currents are proportional to the amount of radiant illumination. Thus, it can be taken that the total leakage current under illumination (ITotal) is composed of two components: One is the leakage current that is not caused by photo illumination (IDark) which is measured under dark state. And the other part is illumination induced leakage current (IIllum) which means the component induced by illumination. In this paper, we will offset IDark
and only consider IIllum which is defined to be the difference between ITotal and IDark. To analyze the photosensitivity of the LTPS TFTs in detail, we further define the slope of the curve in which the current versus illumination intensity as Unit-Lux-Current (ULC in abbreviation) to be a new index. The physical meaning of ULC is the photo leakage current induced “per unit-photo flux” and independent of the dark current.
Therewith, the total off current Itotal of LTPS TFT can be expressed as
⋅L
where L is the illumination intensity in lux.
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3.3 Insight of Photosensitivity
3.3.1 Field Effects on Unit-Lux-Current
Fig. 3-6 shows gate bias dependence of ULC under different drain biases. It is obvious that ULC is change severely under higher drain voltage. Fig. 3-7 shows drain bias dependence of ULC under different gate biases. When drain voltage Vd is lower than 8V, ULC increases linearly with drain bias [3.10], and gate bias effect is negligible. However, when Vd is large enough, ULC increases with drain bias more rapidly and gate bias effect becomes significant. As shown by the arrow line in Fig.
3-7, the linear ULC curve at low drain bias can be fit, and this is one of the two components of the total ULC. This component which increases with drain bias linearly and independent of gate bias is defined as ULC1. Then, the second component which subtracts ULC1 from the total ULC curve is called ULC2.
Furthermore, we plot ULC2 in Fig. 3-8. It is apparent that the log [ULC2] increases with drain bias linearly, indicating that ULC2 increases with drain bias exponentially when Vd is large enough. The parallel curves of log [ULC2] at different gate biases indicate that the dependence of gate bias is also exponential. Thus, ULC can be expressed by a linear combination of these two components as
2 drain voltage dependence and the zero drain bias offset of ULC1, respectively. γ is the scaling factor of ULC2, while η1 and η2 are the parameters about the exponential dependence on drain bias and negative gate bias of ULC2. As shown in Fig.3-9, the calculated results agree with our experiment data very well. The values of fitting factors α, β, γ, η1 and η2 are listed in Table. 3-1.
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Moreover, the mechanisms of two ULC components will be further discussed. The ULC can be taken into account both the leakage current induced in the gate-drain overlap depletion and in the lateral depletion regions [3.11]. When device is operating at the low drain voltage, the linear increase with drain bias of ULC1 is attributed to lateral depletion region by the channel-drain junction in reverse bias. In this region, ULC2 is negligible. When drain voltage is large enough, ULC2 increase with drain exponentially and gate bias effect becomes significant. Several mechanisms of leakage current were discussed in previous report [3.12-3.15]. It considered that the reverse lateral depletion at drain region extends and causes gate induced drain leakage (GIDL) in gate-drain overlap depletion junction. The amount of the photo current should be associated with the carrier generation in the space charge region. By the junction reverse saturation current and GIDL, the drain current owing to the GIDL effect is also in an exponential relation. This phenomenon is similar to our case of ULC2 component. The voltage difference between the drain and gate biases corresponds to the magnitude of electric field across the depletion region. A more negative gate bias means that the electric field would get stronger, as the same as a more positive drain bias. It suggests that larger electric field across the drain depletion region causes larger photo effect. Both drain and gate bias affects the electric field strength in the depletion region in a slightly different ways.
3.3.2 Temperature Effects on Unit-Lux-Current
We further take into account the temperature effect of ULC. Fig. 3-10 shows the illumination effect on photo leakage current at different temperatures of 25, 40, and 60oC under a certain bias condition of (Vd ,Vg) = (10V, -5V). The correlation between ITotal and illumination intensity is still linear at various temperatures.
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Drain bias dependences of ULC at different temperatures are shown in Fig. 3-11.
ULC in the range of low drain bias is significantly affected by temperature. While in the higher drain bias range, the temperature effect reduces gradually. From the discussion above, we have separated the ULC intoULC1 and ULC2. It can be seen that ULC1 is actually the term subject to the temperature effect. On the other hand, as shown in Fig. 3-12, ULC2 is totally temperature independent, which means ULC2 is the term purely induced by electric field. Therefore, ULC1 may be induced by mechanism like excess carrier diffusion or thermionic emission and thus it has weak dependence on the electric field, especially gate bias. ULC2 may be induced by mechanism like excess carrier drift or field emission and thus it has strong dependence on the drain and gate biases.
Since the lateral electric field is relatively small, the photo-induced current is a thermally generated current dominantly. The temperature effect on IDark can identify constant activation energy [3.16-3.17], which hints us to add the fitting factors α and β and in eq. (3-3) in the Arrhenius plot. Fig. 3-13 shows the relationship between α and β and 1/kT. These two factors increase with 1/kT exponentially and can be expressed by corresponding fitting parameters. The fitting values of EaA, EaB, A and B are listed in the inset. By the temperature effect discussed above, it is confirmative to separate ULC into two components. ULC1 is thermally activated and might be corresponding to the thermionic emission or carrier diffusion, while ULC2 is independent of temperature and possible owing to field emission or carrier drift.
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3.3.3 Mechanism of Unit-Lux-Current
Based on the experimental results of bias, temperature, and sensing location, a more complete mechanism of ULC is proposed to explain photosensitive effect on the leakage current of LTPS TFT. Fig. 3-14 illustrates the band diagrams under the condition of Vg<0 along the channel direction near the drain region at low and high drain biases. In the figure, Wd indicates the length of depletion region at the drain electrode side where electron-hole pairs can be generated under illumination in the poly-Si film. The generated electrons flow toward the drain electrode and the holes flow in the opposite direction. Wd consists of two regions. One is the high hole concentration region in the channel induced by the negative gate bias, the other is in the LDD region. The channel area is shielded by the gate metal, while the LDD region can be shined by the illumination. Based on the Poole-Frenkel effect lowering of a Coulombic barrier and phonon-assisted tunneling due to the electric field applied to a semiconductor [3.18], which enhances thermal emission and the trap-to-band field emission rate, the two components of ULC will be discuss. For the case at low drain bias with light irradiation, when the gate bias is changed, similarly to the abrupt p+n junction, the electric field of the other part in LDD region is invariable. Thus, the gate voltage independence of the ULC1 can be explained. As for the Vd effect, the lateral depletion region increases linearly with drain bias, corresponding to the parameter α in eq. (3). With extremely low drain bias, there is still a depletion region in LDD, in accordance with the parameter β in eq. (3). The conduction mechanism of the leakage current in the low drain field is thermal emission [3.19]. Consequently, the parameters α and of β of ULC1 are temperature dependent.
On the other hand, for the high drain bias with light irradiation, the electric field across the lateral depletion region is large enough to fully deplete the LDD region.
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Therefore, the increase of drain voltage will increase the electric field within the limited LDD length pinched by the n+ region. In such case, the more negative gate bias will also result in the larger field with the same depletion width of the LDD
Therefore, the increase of drain voltage will increase the electric field within the limited LDD length pinched by the n+ region. In such case, the more negative gate bias will also result in the larger field with the same depletion width of the LDD