Thesis Organization - 高速輸出入介面電路之靜電放電防護設計

CHAPTER 1 INTRODUCTION

1.2 Thesis Organization

In chapter 2, the HSPICE simulation to evaluate the parasitic capacitance of ESD diodes are described. Besides, device structure and layout description for (shallow-trench-isolation) STI diodes and MOS-bounded diodes are presented.

In chapter 3, the experimental results on DC I-V characteristics, TLP I-V curves, ESD robustness, and parasitic capacitance of the fabricated ESD diodes in a 0.13-μm CMOS process are reported and discussed. Furthermore, the design example of an ESD protection circuit for 5-GHz high-speed I/O applications in a 0.13-μm CMOS process is proposed.

In chapter 4, a high-speed I/O interface circuit with this ESD protection scheme had been designed and fabricated in a 0.13-μm CMOS process to verify the performance, including ESD robustness and parasitic effects. The high-speed I/O interface circuit includes the transmitter and receiver interface circuit. Simulation had

pad is below 500 fF. The experimental results had demonstrated that the ESD robustness with this ESD protection scheme can sustain a HBM ESD robustness of more then 2 kV. Finally, the future works about the modified design on the ESD protection circuit is given in Chapter 5.

CHAPTER 2 INVESTIGATION ON HIGH-FREQUENCY CHARACTERISTICS OF DIFFERENT ESD DIODE

STRUCTURES

With the increased operating frequency of modern high-speed I/O circuits, the maximum tolerated parasitic capacitance at the I/O pad is decreased. However, there is a tradeoff between the capacitance at the I/O pad and the ESD robustness. The parasitic loading effect of ESD protection devices for gigahertz high-speed I/O applications becomes more and more serious because the dimensions of the ESD protection devices can not be shrunk unlimitedly in order to maintain the required ESD robustness. From circuit perspectives, the protection circuits must be transparent to the internal circuit, and must not affect the signal under normal circuit operating conditions. The on-chip ESD protection circuit is placed between the I/O pad and the internal circuits, as shown in Fig. 2.1. The ESD clamp device at the I/O pad can be realized with various devices, such as diode, gate-grounded NMOS (GGNMOS), or silicon-controlled rectifiers (SCR). Traditionally, the GGNMOS is designed with large device dimensions and large drain-contact-to-poly-gate spacing in order to sustain acceptable ESD level [13]-[14]. The gate-coupled technique [15]-[17] or the substrate-triggering technique [18] had been used to uniformly turn on the multiple fingers in the GGNMOS to improve the ESD level. However, the large device dimensions consume much chip area and cause large parasitic capacitance. The wide drain diffusion junction contributes large parasitic capacitance at the I/O signal pad,

gigahertz high-speed applications. The other ESD device suitable for low-capacitance consideration is SCR, because SCR can sustain high ESD level in a small device size [19]-[20]. However, the high trigger voltage of SCR should be taken into consideration. For example, in a 0.25-μm CMOS process, the gate oxide breakdown voltage is around 10V, and the trigger voltage of SCR is higher than the gate oxide breakdown voltage. Therefore, extra trigger circuits should be used to turn on the SCR in time. The ESD devices shunt ESD current from the I/O pad to the power supply rails away from the internal circuit during ESD stresses. However, the ESD devices contribute parasitic capacitances and resistances on the signal path under normal operating conditions, which causes serious performance degradation at high frequency bands. A poorly designed ESD protection scheme may cause impedance mismatches, signal reflection, corruption of signal integrity, and inefficient power transfer. In order to provide efficient ESD protection without extra trigger circuits, diodes are commonly used for ESD protection in high-speed I/O applications, as shown in Fig. 2.2 [21]-[22]. Besides, low-capacitance bond pad design had been reported to enhance the high-speed performance [23].

In this chapter, the parasitic capacitance of STI and MOS-bounded diodes are calculated and simulated. In addition, the layout patterns of the diodes are reported and discussed.

2.1 Diode

Generally, the ESD diode is designed to be operated in the forward-biased condition to discharge the ESD current during ESD stresses, and is designed to be operated in the reverse-biased region under normal circuit operating conditions. The diode current abruptly rises at around 0.6V~0.7V, which is the cut-in voltage. The

turn-on resistance is around 1Ω to 5Ω in the forward-bias condition. In the reverse-biased condition, the diode current rises after the junction breakdown occurs.

This is because the current conduction begins when the junction goes into avalanche breakdown under reverse-biased conduction.

In the forward bias condition, the parasitic capacitance will be increased due to the decreased depletion region. The width of the depletion region will increase to avoid the minority carrier to pass through the depletion region when the ESD diode is in the reverse-biased condition, so the parasitic capacitance of ESD diode is decreased in the reverse-biased condition.

The ESD level of diodes operating in the forward-biased condition is better than that in the reverse-biased condition. By using the turn-on efficient power-rail ESD clamp circuit, the diodes can operate in forward-biased condition when ESD current comes to promote overall ESD level [24]. Therefore, the size of ESD diodes did not need very large. Moreover, the power-rail ESD clamp circuit does not contribute any parasitic effect to the internal circuit. Diode in the forward-biased condition is very useful in ESD protection design for high-speed applications.

2.1.1 STI Diode

The STI diode is the typical diode structure, and the foundry provides the STI diode. The schematic cross-sectional view of the p+/n-well STI diode (P-type diode) is shown in Fig. 2.3(a). The N+ diffusion (cathode) and P+ diffusion (anode) are separated by the shallow trench isolation (STI). The N+ diffusion surrounds the P+

diffusion. The schematic cross-sectional view of the n+/p-well STI diode (N-type diode) is shown in Fig. 2.3(b). The P+ diffusion (anode) and N+ diffusion (cathode)

the N+ diffusion. The n-well/p-well diode (NW-type diode) is shown in Fig. 2.3(c), The P+ diffusion in P-well (anode) and the N+ diffusion in N-well (cathode) are separated by the shallow trench isolation (STI). The P+ diffusion in P-well surrounds the N+ diffusion in N-well. When the abovementioned ESD diodes are under forward-biased ESD stress condition, the ESD current would flow from P+ diffusion to N+ diffusion.

2.1.2 MOS-Bounded Diode

The MOS-bounded diode had been reported with its ESD robustness verified in a 0.35-μm CMOS process, but the high-frequency device characteristics were not reported [25]. In a 0.13-μm high-speed (HS) CMOS process, the ESD robustness and the high-frequency characteristics of MOS-bounded diodes were investigate in this thesis. The cross-sectional views of the NMOS-bounded diode and PMOS-bounded diode are shown in Fig. 2.4(a) and 2.4(b), respectively. The NMOS-bounded (PMOS-bounded) diode has a NMOS (PMOS) inserted in the diode structure. The MOS-bounded diodes have the cathode (anode) of N+ (P+) diffusion, which does not touch the P+ (N+) diffusion in the diode structure. The anode (cathode) of P+ (N+) diffusion directly touches another N+ (P+) diffusion in the NMOS-bounded (PMOS-bounded) diode, where this N+ (P+) is floating. In this NMOS-bounded (PMOS-bounded) diode, the poly gate is fully covered by the N+ (P+) implementation.

With the poly gate between the anode and cathode, the turn-on speed can be enhanced to bypass the ESD stress current. Therefore, the MOS-bounded diode can provide more effective ESD protection to the internal circuits.

The NMOS-bounded (PMOS-bounded) diode is fully compatible to the general

CMOS processes without any additional process step or extra mask layer. The MOS-bounded diodes were implemented to evaluate its characteristic and ESD robustness in this work.

2.2 ESTIMATION FOR PARASITIC EFFECTS OF ESD DIODES

The equivalent circuit model of diode is shown in Fig. 2.5. The diode capacitance is modeled by cd. The capacitance cd is the combination of diffusion capacitance (cdiff), depletion capacitance (cdep), metal (cmetal), and poly capacitance (cpoly). The capacitance cd can be expressed as

cd = cdiff + cdep + cmetal + cpoly

where

cdiff is the diffusion capacitance, cdep is the depletion capacitance,

cmetal is the metal capacitance (depends on routing strategy), and cpoly is the capacitance (depends on routing strategy).

Using diffusion capacitance equations when the transit time (TT) models the diffusion capacitance, cause by injected minority carriers. In practice, TT is estimated from the pulsed time-delay:

= ∂

i∂id cdiff TT

vd TT (s) is the transit time with the default value of zero. Using depletion capacitance equations when the depletion capacitance is modeled by junction bottom and junction periphery capacitances:

1 1

cmetal WMeff XMeff LMeff XMeff M

XOM

( ) ( )

⎛ ε ⎞

=⎜⎝ ^ox ⎟⎠i + i + i

cpoly WPeff XPeff LPeff XPeff M

XOI

By the foundry junction model perimeters and the diode capacitance modeled as above, the estimation for parasitic effects of ESD diodes can be calculated via computer-aided-tool (CAD) such as SPICE or other simulation tools.

2.3 SIMULATION ON PARASITIC EFFECTS OF ESD DIODES

The three types of ESD diodes will be chosen in proper dimensions. Basically, the sizes of ESD diode in high-frequency applications should be as small as possible because the parasitic capacitance degrades performance. Besides, the ESD diode should sustain the required ESD level. In the first step, some proper sizes with the estimated parasitic capacitance below 100fF were selected, as shown in Table 2.1. All the parasitic capacitance of the three types of ESD diodes had been simulated by the simulator HSPICE to estimate the parasitic capacitance by the equations listed above.

2.4 LAYOUT DESCRIPTION OF ESD DIODES

The layout description of ESD diodes includes STI and MOS-bounded diodes.

Not only the ESD robustness but also the parasitic capacitances of these diodes are investigated. In this work, two-port GSG layout was adopted to facilitate the on-wafer probing to evaluate the parasitic capacitance contributed by the ESD devices. The layout top view of the experimental test chip includes the STI diodes and MOS-bounded diodes, as shown in Fig. 2.6. The device dimensions of the ESD devices are summarized in Table 2.2. The total layout area is 1500µm x 4500µm.

With the experimental results of the ESD devices, the optimal ESD device dimension can be obtained for high-speed applications.

2.5 SUMMARY

Two kinds of ESD diode structures for high-frequency applications have been simulated and thoroughly estimated, the proper device sizes had been chosen among the three types of STI diodes and two types of MOS-bounded diodes. All the diodes were fabricated in a 0.13-µm CMOS process. In order to obtain the complete data efficiently, the estimation of diode sizes by simulation must be done accurately, and the size ranges of diodes are very important. If the size ranges is too large, large amount of diode may cause too large chip area. Besides, too large diode sizes may cause large parasitic capacitance, which is not suitable for high-frequency applications.

Table 2.1 Simulation on parasitic effects of ESD diodes.

Diode Device W/L

(μm/μm) M Parasitic Capacitance (fF)

DION_L130E 4/5 5 68.6947

DION_L130E 10/10 1 64.0783

DIOP_L130E 4/5 5 87.7954

DIOP_L130E 10/10 1 82.9880

DIONW_L130E 4/5 5 95.5736

DIONW_L130E 10/10 1 49.7544

Table 2.2 Layout dimensions of three types STI and two types MOS-bounded of ESD diodes.

Item Pad Diode Type Width

(μm)

1 DIONW_L130E_DC2 20 5 1 50 100 66.10

2 DION_L130E_DC2 20 5 1 50 100 77.17

3 DIOP_L130E_DC2 20 5 1 50 100 75.24

4 DIONW_L130E_DC2 20 5 2 100 200 132.20

5 DION_L130E_DC2 20 5 2 100 200 154.33

6 DIOP_L130E_DC2 20 5 2 100 200 150.48

7 DIONW_L130E_DC2 20 5 3 150 300 198.30

8 DION_L130E_DC2 20 5 3 150 300 231.50

9 DIOP_L130E_DC2 20 5 3 150 300 225.71

10 DIONW_L130E_DC2 20 5 4 200 400 264.40

11 DION_L130E_DC2 20 5 4 200 400 308.66

12 DIOP_L130E_DC2 20 5 4 200 400 300.95

13 DIONW_L130E_DC2 20 5 5 250 500 330.50

14 DION_L130E_DC2 20 5 5 250 500 385.83

15 DIOP_L130E_DC2 20 5 5 250 500 376.19

16 Empty(De-Embedding)

27 DIONW_L130E_DC8 20 5 1 50 100 66.10

28 DION_L130E_DC8 20 5 1 50 100 77.17

29 DIOP_L130E_DC8 20 5 1 50 100 75.24

30 DIONW_L130E_DC8 20 5 2 100 200 132.20

31 DION_L130E_DC8 20 5 2 100 200 154.33

32 DIOP_L130E_DC8 20 5 2 100 200 150.48

33 DIONW_L130E_DC8 20 5 4 200 400 264.40

34 DION_L130E_DC8 20 5 4 200 400 308.66

35 DIOP_L130E_DC8 20 5 4 200 400 300.95

36 DIONW_L130E_DC8 20 5 5 250 500 330.50

37 DION_L130E_DC8 20 5 5 250 500 385.83

38 DIOP_L130E_DC8 20 5 5 250 500 376.19

39 Empty(De-Embedding)

40 Open(De-Embedding) 1

41 Short(De-Embedding) 1

42 M8

Only Empty(De-Embedding)

43 NMOS_BOUNDED_DIODE_L130E 20 5 1 50 100

44 NMOS_BOUNDED_DIODE_L130E 20 5 5 250 500

45 PMOS_BOUNDED_DIODE_L130E 20 5 1 50 100

46 PMOS_BOUNDED_DIODE_L130E 20 5 5 250 500

47 NMOS_BOUNDED_DIODE_L130E 20 5 10 500 1000 48 PMOS_BOUNDED_DIODE_L130E 20 5 10 500 1000

Table 2.3 Layout dimensions of three types STI ESD diodes.

Fig. 2.1 Typical on-chip ESD protection design for input/output (I/O) pad with power rail ESD clamp circuit.

Fig. 2.2 The typical I/O ESD protection circuit constructed by double diodes in CMOS IC.

P+ N+

Fig. 2.3 The schematic cross-sectional view of a STI diode structures (a) P-type (b) N-type, and (c) NW-type.

(a)

(b)

Fig. 2.4 The cross-sectional views of (a) NMOS-bounded diode, and (b) PMOS-bounded diode.

Fig. 2.5 Equivalent circuit model for diodes.

(a) (b)

(e)

(f)

Fig. 2.6 (a) P-type, (b) N-type, (c) NW-type STI diode structures and (d) NMOS-bounded, (e) PMOS-bounded diode structures and (f) layout top view (1500 μm × 4500 μm) of the ESD diode devices with wo-port GSG blocks in a testchip.

CHAPTER 3 EXPERIMENTAL RESULTS ON DIFFERENT ESD DIODE STRUCTURES AND AN EXAMPLE OF ESD PROTECTION DESIGN FOR 5-GHz HIGH-SPEED I/O

APPLICATIONS

In this chapter, the experimental results on different ESD diodes are investigated, including the ESD robustness and high-frequency characteristics. The first step is to make sure the right dc I-V curves of diode characteristics when test chips are backed, otherwise we can not confirm the test chips is the right characteristics of ESD diodes or not. When the diode characteristic is confirm, we can start the transmission line pulse generator (TLPG) to measure I-V curves, the purpose is in order to predict the performance of ESD robustness. Besides, the high-frequency S-parameter measurement system is used to evaluate the high-frequency characteristics of different ESD diodes and different bond pad structures. Base on the extracted capacitances of different ESD diodes and different bond pad structures, an example of ESD protection design for 5-GHz high-speed I/O applications is provided. With the design example, the input ESD protection scheme can be quickly designed if the specifications on ESD level and input parasitic capacitance of ESD devices and bond pad are assigned.

3.1 DC I-V CHARACTERISTICS

The curve tracer HP4145B is a semiconductor parameter analyzer, which is

characteristics of ESD diodes. The dc leakage of normal STI diode is around in the order of pA (in 0.13-μm CMOS processes). The dc I-V characteristics of the STI diodes are shown in Fig.3.2, the breakdown voltage is around below 10V and the leakage current of normal operation on voltage 1.2V is around several pA. The dc I-V characteristics of the MOS-bounded diodes are shown in Fig.3.3, the breakdown voltage is around below 2.9V and the leakage current of normal operation voltage on 1.2V is around several nA. Besides, the forward-biased current was compliance due to measurement setup.

3.2 TLP I-V CHARACTERISTICS SECONDARY BREAKDOWN CURRENT (IT2)

The transmission line pulse generator (TLPG) with a pulse width of 100ns [26]

is used to investigate ESD robustness of the fabricated diode devices and predict the ESD robustness of ESD devices; include the second breakdown current (It2). The human-body-model (HBM) ESD level (HBM VESD), and machine-model (MM) ESD level (MM VESD) can also be estimated by the proper adjustment of TLPG. The setup measurement are combine with high-voltage pulse generator (Keithley 2410), oscilloscope and triple-output power supply (Agilent E3631A) shown as Fig. 3.4. For three types of N-type diodes under forward stress conditions, the RON resistance is around 1.6Ω, the It2 current is over 6A. However, the It2 current was below 0.7A, which was very weak when under reversed stress condition as shown in Fig. 3.5. For three types of P-type diodes under forward stress conditions, the RON resistance is around 1.24Ω, the It2 current is over 6A. However, the It2 current was below 0.9A, which was very weak when under reversed stress condition as shown in Fig. 3.6. The

TLP It2 of the P-type diodes with W/L=5μm/5μm and different perimeters (20μm, 40μm, and 60μm) under forward ESD stress conditions are below 1.6A. The TLP It2 of the P-type diodes with W/L=15μm/5μm and different perimeters (40μm, 80μm, and 120μm) under forward ESD stress conditions are below 6A. The TLP It2 of the P-type diodes with W/L=150μm/30μm and different perimeters (360μm, 1080μm, and 1800μm) under forward ESD stress conditions are over 6A. The TLP It2 of the N-type diodes with W/L=5μm/5μm and different perimeters (20μm, 40μm, and 60μm) under forward ESD stress conditions are below 1.58A. The TLP It2 of the N-type diodes with W/L=15μm/5μm and different perimeters (40μm, 80μm, and 120μm) under forward ESD stress conditions are below 6A. The TLP It2 of the N-type diodes with W/L=150μm/30μm and different perimeters (360μm, 1080μm, and 1800μm) under forward ESD stress conditions are over 6A. The TLP It2 of the NW-type diodes with W/L=5μm/5μm and different perimeters (20μm, 40μm, and 60μm) under forward ESD stress conditions are below 1.7A. The TLP It2 of the NW-type diodes with W/L=15μm/5μm and different perimeters (40μm, 80μm, and 120μm) under forward ESD stress conditions are below 6A. The TLP It2 of the NW-type diodes with W/L=150μm/30μm and different perimeters (360μm, 1080μm, and 1800μm) under forward ESD stress conditions are over 6A. The TLP I-V curves of the P-type, N-type, and NW-type ESD diodes under different perimeters were characterized, as shown in Fig. 3.7 – Fig. 3.15 and Table 3.1 – Table 3.3. The experimental result shows that under the same perimeters, the ESD robustness is improved with larger width of the ESD diode.

3.3 HUMAN-BODY-MODEL (HBM) ESD ROBUSTNESS

The human body model is today the most commonly used discharge model in the microelectronic industry. The intention of the model is to reduce a discharge of a charged human being to a device with at least one pin grounded. Although the risk of an IC was getting touched by a charged human being has decreased significantly due to automatic handing. The HBM ESD test standard is well defined by international standards [27]-[29]. The It2 level and HBM ESD level of three types of N-type diodes with different total junction perimeters under forward and reversed ESD stress conditions are shown in Fig. 3.16 and Fig. 3.17. Under forward ESD stress conditions, the It2 level of N-type diode with 50-μm junction perimeters is ~2A, and the HBM ESD level is above 2kV. Under forward ESD stress conditions, the It2 level of N-type diode with 100-μm junction perimeters is ~4A, and the HBM ESD level is above 2kV.

Under forward ESD stress conditions, the It2 level of N-type diode with 150-μm junction perimeters is over 6A, and the HBM ESD level is above 2kV. Under forward ESD stress conditions, the It2 level of N-type diode with 200-μm junction perimeters is over 6A, and the HBM ESD level is above 2kV. Under forward ESD stress conditions, the It2 level of N-type diode with 250-μm junction perimeters is over 6A, and the HBM ESD level is above 2kV. Under reversed ESD stress conditions, the It2 level of N-type diode with 50-μm junction perimeters is below 0.2A, and the HBM ESD level is 0.5kV. Under reversed ESD stress conditions, the It2 level of N-type diode with 100-μm junction perimeters is below 0.3A, and the HBM ESD level is 1kV.

Under reversed ESD stress conditions, the It2 level of N-type diode with 150-μm junction perimeters is below 0.5A, and the HBM ESD level is 1kV. Under reversed ESD stress conditions, the It2 level of N-type diode with 200-μm junction perimeters is below 0.6A, and the HBM ESD level is 1kV. Under reversed ESD stress conditions, the It2 level of N-type diode with 250-μm junction perimeters is below 0.7A, and the

HBM ESD level is 1.5kV. Under forward ESD stress conditions, the It2 level of NW-type diode with 50-μm junction perimeters is ~2A, and the HBM ESD level is above 2kV. Under forward ESD stress conditions, the It2 level of NW-type diode with 100-μm junction perimeters is ~4A, and the HBM ESD level is above 2kV. Under forward ESD stress conditions, the It2 level of NW-type diode with 150-μm junction perimeters is over 6A, and the HBM ESD level is above 2kV. Under forward ESD stress conditions, the It2 level of NW-type diode with 200-μm junction perimeters is over 6A, and the HBM ESD level is above 2kV. Under forward ESD stress conditions, the It2 level of NW-type diode with 250-μm junction perimeters is over 6A, and the HBM ESD level is above 2kV. Under reversed ESD stress conditions, the It2 level of NW-type diode with 50-μm junction perimeters is below 0.3A, and the HBM ESD level is 0.5kV. Under reversed ESD stress conditions, the It2 level of NW-type diode with 100-μm junction perimeters is below 0.3A, and the HBM ESD level is 0.5kV.

Under reversed ESD stress conditions, the It2 level of NW-type diode with 150-μm junction perimeters is below 0.5A, and the HBM ESD level is 1kV. Under reversed ESD stress conditions, the It2 level of NW-type diode with 200-μm junction perimeters is below 0.6A, and the HBM ESD level is 1.5kV. Under reversed ESD stress conditions, the It2 level of NW-type diode with 250-μm junction perimeters is below 0.7A, and the HBM ESD level is 1.5kV. Under forward ESD stress conditions, the It2 level of NMOS-bonded-type diode with 50-μm junction perimeters is ~2A,

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