CHAPTER 4 5-GHz TRANSMITTER (TX) AND RECEIVER
4.5 Discussion and Summary
The TX_NMOS/RX_NMOS interface circuits with ESD protection circuits have been designed and investigated. The experimental results of TX_NMOS interface circuits with ESD protection circuits in the 0.13-μm CMOS process show much stronger ESD robustness with DX=2.15μm of TX_NMOS with large perimeters of ESD devices. Increasing ESD device perimeters can have higher ESD robustness.
Besides, the experimental results of RX_NMOS interface circuits with ESD protection circuits in the 0.13-μm CMOS process also showed that the thick gate oxide RX_NMOS has higher ESD robustness then thin gate oxide RX_NMOS. The post-layout simulated result shows that the parasitic capacitance of the ESD devices can be further reduced by placing the ESD devices under the bond pad. Two types of RX interface circuit with ESD protection circuit have been designed and verified.
Besides, the ESD levels of TX_NMOS and RX_NMOS with ESD protection also have been evaluated in the 0.13-μm CMOS process.
Table 4.1 The combinations of MNESD ESD protection schemes under different dimensions of TX_NMOS drain side.
TX_NMOS
5 64.9 129.8 323.9 65.24 130.48 192.8 0.64
6 7.5 25 38.36 7.5 25 31.1 1.36
7 17.5 35 63.24 17.5 35 45.1 1.36
8 22.5 45 88.11 22.5 45 59.1 1.36
9 27.5 55 117.99 27.5 55 73.1 1.36
10 64.9 129.8 323.9 65.24 130.48 192.8 1.36
11 7.5 25 38.36 7.5 25 31.1 2.15
12 17.5 35 63.24 17.5 35 45.1 2.15
13 22.5 45 88.11 22.5 45 59.1 2.15
14 27.5 55 117.99 27.5 55 73.1 2.15
15 64.9 129.8 323.9 65.24 130.48 192.8 2.15
400 0.18
Table 4.2 The combinations of EPTSCR ESD protection schemes under different dimensions of TX_NMOS drain side.
TX_NMOS
5 64.9 129.8 323.9 65.24 130.48 192.8
6 7.5 25 38.36 7.5 25 31.1
7 17.5 35 63.24 17.5 35 45.1
8 22.5 45 88.11 22.5 45 59.1
9 27.5 55 117.99 27.5 55 73.1
10 64.9 129.8 323.9 65.24 130.48 192.8
11 7.5 25 38.36 7.5 25 31.1
12 17.5 35 63.24 17.5 35 45.1
13 22.5 45 88.11 22.5 45 59.1
14 27.5 55 117.99 27.5 55 73.1
15 64.9 129.8 323.9 65.24 130.48 192.8
16 7.5 25 38.36 7.5 25 31.1
17 17.5 35 63.24 17.5 35 45.1
18 22.5 45 88.11 22.5 45 59.1
19 27.5 55 117.99 27.5 55 73.1
20 64.9 129.8 323.9 65.24 130.48 192.8
8.4
Table 4.3 The combinations of MNESD ESD protection schemes under different dimensions of RX_NMOS gate side.
TX_NMOS
1 64.9 139.8 323.9 65.24 140.48 192.8 1.2V_W 5
2 64.9 129.8 323.9 65.24 130.48 192.8 3.3V_W 5 400 0.18
DP Dn MNESD
5 1 5 1
Item
Table 4.4 The combinations of EPTSCR ESD protection schemes under different dimensions of RX_NMOS gate side.
TX_NMOS
5 64.9 129.8 323.9 65.24 130.48 192.8
6 7.5 25 38.36 7.5 25 31.1
7 17.5 35 63.24 17.5 35 45.1
8 22.5 45 88.11 22.5 45 59.1
9 27.5 55 117.99 27.5 55 73.1
10 64.9 129.8 323.9 65.24 130.48 192.8
5 1
Table 4.5 The simulation results under difference corners.
Vo-pp-min (mV)
Corner Pattern1 Pattern2 TT 126 126 SS 63 63 FF 102 102 FS 98 98 SF 127 127
Table 4.6 The combinations of two types of ESD protection schemes.
5 64.9 129.8 323.9 65.24 130.48 192.8
6 7.5 25 38.36
Top Site Device Bottom Site Device
P-type Diode NW-type Diode
5 1
P-type DiodeP-type DiodeP-type Diode BSEPTSCRBSEPTSCRBSEPTSCR
59.6 8.4
Core Circuit Only
ESD Device
59.6 8.4
59.6 8.4
Table 4.7 The parasitic capacitance under different simulated results.
Not under pad 152.51 130.30
Under pad 150.26 126.36
Reduction 2.25 3.94
Enhancement 1.48% 3.02%
Not under pad 172.50 171.80
Under pad 170.34 171.76
Reduction 2.16 0.04
Enhancement 1.25% 0.02%
Not under pad 216.45 194.65
Under pad 215.23 192.79
Reduction 1.22 1.86
Enhancement 0.56% 0.96%
Not under pad 260.43 217.12
Under pad 259.02 212.35
Table 4.8 The combinations of EPTSCR ESD protection schemes under different dimensions of TX_NMOS drain side.
Dp Dn TX_NMOS
PS NS PD ND Non-Socket CDM (V)
Table 4.9 The combinations of MNESD ESD protection schemes under different dimensions of RX_NMOS gate side.
Dp Dn
PS NS PD ND Non-Socket CDM (V)
Table 4.10 The combinations of EPTSCR ESD protection schemes under different dimensions of RX_NMOS gate side.
Dp Dn
PS NS PD ND Non-Socket CDM (V)
(a)
(b)
Fig. 4.1 To simulate TX interface circuit with TX_NMOS of ESD protection schemes of (a) MNESD device, (b) EPTSCR device.
VDD
(a)
(b)
Fig. 4.2 To simulate RX interface circuit with RX_NMOS of ESD protection schemes of (a) MNESD device, (b) EPTSCR device.
VDD
Fig. 4.3 The EMMI (photon emission microscope) photograph to locate the failure location in ESD diode DP.
Fig. 4.4 The RX interface circuit with ESD protection scheme.
(a)
(b)
Fig. 4.5 (a) The test signal specifications and (b) test patterns for RX interface circuit.
(a)
(b)
Fig. 4.6 The output waveform of RX interface circuits in typical corner when input (a) test pattern 1 and (b) test pattern 2.
(a)
(b)
Fig. 4.7 Two types of ESD protection schemes of (a) type I and (b) type II.
EPTSCREPTSCR BSEPTSCR
Fig. 4.8 Cross-sectional view of ESD devices under input pad.
Fig. 4.9 Layout top view of ESD devices under pad (type I).
N+
Fig. 4.10 Layout top view of ESD devices under pad (type II).
Fig. 4.11 Layout top view (1300 μm × 1371.4 μm) of the two types of ESD protection scheme blocks in a test chip.
CHAPTER 5
CONCLUSIONS AND FUTURE WORKS
5.1 Main Results of This Thesis
The high-frequency characteristics of the ESD diodes have been investigated by on-wafer two-port GSG measurement. From the experimental results, the parasitic capacitance of the ESD devices becomes larger when the ESD device has larger layout area. However, lower parasitic capacitance was observed in higher operating frequency. In a 0.13-µm CMOS process, the optimized dimensions of ESD diodes for the 5-GHz high-speed I/O interface circuits with 2-kV HBM ESD robustness have been obtained.
An ESD protection design example for the high-speed I/O interface circuits has also been proposed in this thesis. By including two types of turn-on efficient power-rail ESD clamp circuits into the high-speed I/O interface circuits, the ESD clamp devices at the input pin are operated in the forward-biased conduction, rather than the junction breakdown condition. Therefore, the dimension of ESD devices for the input pin could be reduced to reduce the input capacitive loading effect. By placing the ESD devices under the bond pad, the input capacitive load can be further reduced. This work has been successfully verified in a 0.13-µm CMOS process. The database of parasitic capacitance and ESD robustness of the ESD diodes were established. The experimental results have confirmed that the ESD robustness is more than 2kV under the HBM ESD test with proper ESD device.
5.2 Future Works
To further decrease the dimensions of the ESD device, and to enhance ESD robustness, other ESD device models, such as SCR, may need to be established. SCR is suitable for ESD protection design with low-capacitance consideration, because SCR can sustain high ESD level in a small device size. Besides, latchup issue can be avoided, because the holding voltage of SCR is higher than the operation voltage of the internal circuits which are fabricated in advanced CMOS processes, such as the 65-nm CMOS process. However, the high trigger voltage of SCR should be taken into consideration. With suitable triggering circuit to turn on SCR quickly, SCR will become the most promising ESD device for ESD protection design for high-speed I/O applications.
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簡歷
姓 名：黃 俊
學 歷：
國立台北科技大學電子工程系 (89 年 9 月~ 92 年 1 月)
國立交通大學IC 設計產業碩士專班 (94 年 2 月~ 96 年 2 月)
PUBLICATION LIST
PATENTS
[1] Ming-Dou Ker, Chun Huang, and Yuh-Kuang Tseng, “ESD Protection Design for Low-Capacitance Specification,” pending for U.S.A. and R.O.C. Patents.