Chapter 1 Introduction
1.2 Thesis Organization
This thesis contains two building blocks of low voltage low-IF receiver RF front-end. One is the 0.7V 2.45-GHz single-to-balanced LNA and the other is 0.7V 2.45-GHz folded-switching mixer. We will present the design flows and characteristic analyses of these two circuits.
In Chapter 2, we will introduce the design of low-voltage folded-switching mixer including the analyses of conversion voltage gain, noise figure, linearity, and DC stability. A basic review of single-balanced and double-balanced mixer architecture is also presented in this chapter. At last, the simulation and experimental results and their comparisons are presented.
In Chapter 3, a simple conclusion about this work is made and future works are discussed.
In Chapter 4, we will describe the design of low-voltage single-to-balanced LNA and show the simulation results as an appendix. Also, we will present the analyses of input matching, noise figure, and power consumption in terms of circuit component
parameters.
Chapter 2
Low-Voltage (0.7V)
Folded-Switching Mixer
2.1 Review of the Basic Mixer
Mixers employed in the receiver path perform frequency translation to a lower frequency for further processing by multiplying two signals in the time domain. Since linear, time-invariant systems cannot produce outputs with spectral components not present at the input, mixers must be either nonlinear or time-varying elements in order to provide frequency translation.
Mixers based directly on multiplication, such as Gilbert cell mixers [7], [8], generally have superior performance because they ideally produce only the desired intermodulation product. Furthermore, since the inputs to a multiplier enter at separate ports, higher port-to-port isolation can be achieved among all three ports (RF, LO, and IF). In this type, the output current of mixer can be expressed as：
[ t ] { I I t }
i
out= sgn cos ω
LO BIAS+
RFcos ω
RF (2.1)The output thus consists of sum and difference components, each the result of an odd harmonic of the LO signal mixing with the RF signal. Fig. 2-1 shows two types of mixers based on the multiplication.
(a) (b)
Fig. 2-1(a) Single-balanced mixer (b) Double-balanced mixer
The single-balanced topology as shown in Fig. 2-1(a) has less input-referred noise for a given power consumption than the double-balanced counterpart. However, this circuit is more susceptible to noise in the LO signal. In addition, odd harmonics of the LO appear directly in the output as a consequence of the DC bias current multiplying with the LO signal, which is known of the LO-IF feedthrough. On the other hand, the double-balanced mixer as shown in Fig. 2-1(b) exploits symmetry to remove the undesired output LO component through the differential pairs M3-M4 and M5-M6 providing opposite signal phases to cancel the feedthrough from the LO to the IF and generates less even-order distortion. The double-balanced mixer also has better port-to-port isolations by the symmetry. With these advantages makes the topology be widely used in receiver architecture. However, it stacks three transistors makes the circuit unsuitable to operate at low supply voltage. There exists a demand for searching a new topology to meet the low-voltage operation, but still keeps all advantages of the double-balanced mixer.
2.2 Low-Voltage Folded-Switching Mixer Design
Typically, the low-voltage design technique uses LC-tank capacitively coupled topology, [21], to separate both the DC and AC path of a cascade circuit as shown in Fig. 2-2.
Fig. 2-2 Equivalent DC and AC signal path
Based on this topology, if we want the mixer to be differential, it needs too much on-chip inductors resulting in a large chip size, [22]. In terms of operation at low supply voltage, the goal is to reduce the voltage drops across the load resistors and the switching transistors. This can be done by designing a switching mixer in which only
a small part of dc current from the transconductor flows through the switching stage and the load resistors. Therefore, we need to change the common-source transconductors in the double-balanced mixer but remaining the switching stage as in the double-balanced mixer.
2.2.1 Transconductors for Folded-Switching Mixers
(a) Resistive load (b) Active load
(c) CMOS inverter (d) Ac-coupled CMOS inverter Fig. 2-3 Four types of transconductors for folded-switching mixer
In the case of the doubled-balanced mixer (see Fig. 2-1(b)), the single NMOS transistor is used as the transconductor. Fig. 2-3 shows four different transconductors for application in low-voltage folded-switching mixer. Indeed, they represent
improvement of the single NMOS transconductor with respect to operation at low supply voltages.
The transconductor with resistive load is the simplest modification of the single NMOS transconductor (see Fig. 2-3(a)). The ac current In, which is produced in the NMOS transistor, splits to the current through the switching stage Is and through the resistor Ir. The fact that a part of the ac current flows through the resistor R represents the drawback of this transconductor. In order to reduce Ir the value of the resistor R has to be increased. As a consequence must be taken to keep the dc voltage at the node A sufficiently high to prevent the transistor M1 entering linear region. At low supply voltage this problem is even important.
The drawback of the transconductor with resistive load can be improved by using the transconductor with active load as shown in Fig. 2-3(b). By replacing the resistor with the PMOS transistor the ac current through this transistor Ip is further reduced owing to the high output impedance of the PMOS transistor. Instead of using PMOS transistor only to increase the impedance between the node A and Vdd, it can be also used to amplifier the RF signals. In this way the leakage of the ac current toward the ac ground through the output impedance of the PMOS transistor can be ideally completely avoided. Therefore, a CMOS inverter as shown in Fig. 2-3(c), which is used as the transconductor, is obtained.
In the CMOS inverter, the RF signal amplificated by the PMOS transistor is a result of current reuse principle [23]. This is an efficient way to have a high gain and a low noise figure with a low power consumption. The ac current Is is equal to the sum of the ac current In and Ip. Based on that the total transconductance is equal to gmn + gmp, where gmn is the transconductance of transistor M1 and gmp is the transconductance of transistor M2. Before going further with a detailed analysis of the folded-switching mixer that uses the CMOS inverter as the transconductor, it is
instructive to check the lowest supply voltage. It is determined by the threshold voltages Vt and by the overdrive voltages of the transistors M1 and M2. The overdrive voltages Vovn of M1 and Vovp can be calculated using
Vrfdc is the biasing voltage applied at the gates of the transistors M1 and M2. Finally, the minimal supply voltage Vdd (min), at which the mixer can operate, is expressed as
t clear that the minimum supply voltage Vdd (min) must be higher than 1 V. This is the disadvantage of the CMOS inverter, which is used as the transconductor in the low-voltage folded-switching mixer.
In order to overcome the described limitation, the biasing for NMOS and PMOS transistors in the CMOS inverter have to be separated. In this way we obtain an ac-coupled complementary transconductor as shown in Fig. 2-3(d). If Vrfdcn is the gate biasing voltage of M1 and Vrfdcp of M2, (2.4) becomes
rfdcn
Choosing Vrfdcn to be greater than Vrfdcp, Vdd (min) can be further reduced. In this work, we set Vrfdcn equal to 0.7 V and Vrfdcp to be DC ground and assume Vt is
a minimum supply voltage using in this work. Combining the ac-coupled complementary transconductor with the switching stage and load resistors, the ac-coupled folded-switching mixer is obtained and shown in Fig. 2-4.
Fig. 2-4 Ac-coupled folded-switching mixer
2.2.2 Gain and Noise Figure
Assuming that LO signal is an ideal square wave, the voltage gain of the mixer shown in Fig. 2-4 can be approximated by, [25],
( )
⎥⎦⎤⎢⎣⎡ +
= g g R
G mn mp
π log 2
20 (2.7)
where gmn is the transconductance of M1 and M2, gmp is the transconductance of M3 and M4 and R is the load resistor. Since only a small part of the dc current from the switching stage flows through the transconductor, large load resistors can be used.
Hence, the voltage gain is improved, but at the same time the switching transistors have to handle a large output signal swing. Therefore, the dc voltage V2 and V2’ has to be kept sufficiently high and voltage V1 sufficiently low (see Fig. 2-4). On the
other hand, voltage V1 should be sufficiently high in order to keep the transistors M1 and M2 saturated.
The noise figure of the ac-coupled folded-switching mixer with current-reuse, under the assumption that the LO signal is ideal square wave and take into account the noise folding from the image frequency, can be approximated by, [25],
( )
where Rs is the source resistance and the coefficient γ is equal to 2/3 for long channel transistors and need to be replaced with a larger value for submicron MOSFETs, [24],.
2.2.3 Linearity
Nonlinearity in the mixer voltage transfer function is caused by operation of the switching transistors in the linear region. The switching transistors will be turned off by the high voltage swing at the nodes V1 and V1’ (see Fig. 2-4). In this case a high current pushed by the transistors M3 or M4 will cause a high voltage across the output impedance of the transistors M1 or M2 that will turn the switching transistors M7 and M6 or M8 and M5 off. Linearity manly depends on input signal dynamic range which does not make the operation of transistors in the linear region. In the folded-switching mixer with current-reuse, the linearity can be improved by decreasing the DC voltages V1 and V1’, and the deviation from a linear transfer function can be reduced by keeping the switching transistors far from the linear region.
2.2.4 DC Stability
In order to design a robust ac-coupled folded-switching mixer with current-reuse that can stand at least supply voltage variations of 10%, it is necessary to calculate the
and ∆Vrfdcp. Small signal analysis is applied to this calculation assuming that the variations of voltages Vrfdcn and Vrfdcp are small. Substituting the small signal model for each transistor (parallel connection of transistor output impedance and ideal current source with value gmVin, where gm is the transconductance and Vin the small signal voltage applied at the gate) the variations of voltage V1 and V1’ can be expressed as transconductance of the switching transistors. In the denominator of (2.9) gms dominates and reduces the variations of the voltage V1 by a larger value gms.
2.3 Layout and Measurement Consideration
Layout is an important step in optimizing a radio frequency circuit design. A poor layout could result in great degradation between expected and actual circuit’s performances. The chip layout of the low-voltage folded-switching mixer is shown in Fig. 2-5 and is fabricated in TSMC 0.18-µm CMOS technology. To minimize the impacts of substrate noise on the circuit, guard rings are added to the devices and inductors, which also improve the quality factor Q of the inductor. Furthermore, traces connected to all inductors are made wide enough to minimize series parasitic resistances and inductances, and thus avoid inductor Q degradation. The RF and LO input are placed in opposite position to improve the port-to-port isolations. Since PCB on-chip testing is to measure the performances of the mixer, two shielded differential signal GSGSG pads are placed at RF and LO input respectively. In low-voltage operation, the resistances of the biasing traces have large effects on circuit’s operation and performances. It may cause undesired voltage drops on the DC path and hence
reduces the voltage headroom, an important issue needed to be taken into account.
Therefore, the biasing traces must be as short and wide as possible to reduce the parasitic resistance of metal lines. The total layout area of the mixer is 1.24 × 1.19 mm2 .
The low-voltage mixer is designed for PCB on-wafer measurement so the layout must follow the rules of CIC’s (Chip Implementation Center) probing testing [13].
The measurement of the mixer is PCB on-wafer so we have to take the effects of bond wires into account in the design of the mixer. The measurement needs two input differential GSGSG probes, one for RF port and the other for LO port. The output signals IFp and IFn are bonded and connected to SMA connectors for measuring. Fig.
2-5 shows the layout of low-voltage mixer. Fig. 2-6 shows the die photograph of mixer. Fig. 2-7 shows the picture of the testing board. Fig. 2-8 is the picture of PCB on-wafer measurement setup for the ac-coupled folded-switching mixer. The S-parameter measurement setup is shown in Fig. 2-9. Fig. 2-11 shows the measurement setup for noise figure. Fig. 2-11 is the setup for measuring conversion power gain and one dB compression point and the measurement setup for IIP3 is shown in Fig. 2-12.
Fig. 2-5 The layout of ac-coupled folded-switching mixer
Fig. 2-6 Die photograph of low-voltage mixer
Fig. 2-7 PCB testing board picture of the mixer
Fig. 2-9 Measurement setup for S-parameter
Fig. 2-10 Measurement setup for noise figure
Fig. 2-11 Measurement setup for conversion gain and P1dB
Fig. 2-12 Measurement setup for IIP3
2.4 Simulation and Experimental Results
The low-voltage folded-switching mixer was simulated and fabricated by CMOS 0.18-µm technology. The measurement results show that it has 6.21dB RF port return loss, 12.7dB LO port return loss, 8.99dB conversion voltage gain and 6.96dB conversion power gain at 0dBm LO power, -9dBm P1dB, and 4dBm IIP3. The total power consumption is 2.87 mW very close to the simulated one, 2.83mW.
Fig. 2-13 shows the RF port input matching. The measured RF port input matching is shifting down to 1.5 ~ 1.9 GHz due to the inductance of L1 or L2 (see Fig.
2-4) increasing and the parasitic capacitances to the substrate being more serious than simulation. At 2.45 GHz, The measured RF port input matching is -6.21 dB and the simulated one is -13.2 dB. Fig. 2-14 is the comparisons between measured and simulated LO port input matching. The measured result is matched to the simulation.
But more parasitic capacitances to the substrate than the simulation result in not as sharp as the simulated curve at 2.45 GHz. The measured LO port input matching is -12.7 dB and the simulated one is -34.5 dB at 2.45 GHz.
Fig. 2-15 shows the measured and simulated conversion power gain. The primary reason for the two curves not matching is that the load resistors becoming larger by the process variations make the transistors in the switching stage (see Fig.
2-4) operate in linear region. The larger load resistors have more voltage drops across them and force the transistors in switching stage entering linear region due to insufficient voltage head room. By simulation again, the modified curve shown in Fig.
2-15 confirms this conclusion. There is 3-dB difference between the modified and measured conversion power curves resulting from the twice of simulated RF port input matching to the measured one. The measured conversion power gain at 0 dBm LO power is 6.96 dB. Fig. 2-16 shows the simulated and measured one dB
compression point. The simulated and measured P1dB is -15.5 and -9 dBm respectively. Fig. 2-17 is the comparisons between the simulated and measured third order intercept point. The simulated and measured IIP3 is -6 and 4 dBm respectively.
The linearity is improved due to the conversion gain decreasing. Fig. 2-18 is IF output waveform. From Fig. 2-18, the conversion voltage gain by the calculation is 8.99 dB.
We can not provide the measured noise figure because the measurement type is not accepted by CIC. The summary of the simulated and measured performances of the low- voltage folded-switching mixer is shown in Table 2-1.
Table 2-2 shows the comparisons with recently published works. Compared with other low-voltage mixers, this work has moderate conversion gain, higher linearity, and the lowest power consumption under 0.7V supply voltage.
Fig. 2-13 Simulated and measured RF port input matching
Fig. 2-14 Simulated and measured LO port input matching
Fig. 2-15 Simulated and measured conversion power gain
Fig. 2-16 Simulated and measured one dB compression point
Fig. 2-17 Simulated and measured third order intercept point
Fig. 2-18 IF output waveform of low-voltage mixer
Table 2-1 Summary of the performances of low-voltage folded-switching mixer
Specification Simulation Measurement
IF 1 MHz 1 MHz
Supply voltage (V) 0.7 0.7 RF input matching (dB) -13.2 -6.21 LO input matching (dB) -34.5 -12.7
Conversion power gain (dB)
11.4 @ LO 0dBm 6.96 @ LO 0dBm
P1dB (dBm) -15.5 -9
IIP3 (dBm) -6 4
NF (dB) 10.3 N/A Conversion voltage gain
(dB)
13.8 8.99
Core power dissipation (mW)
2.83 2.87
Total power dissipation (mW)
20.46 24.87
Table 2-2 Comparisons with recently published works
[25] [26] [27] This work
Gilbert cell folded-switching
Vdd (V) 1 0.6/0.8 1 0.7
Switched CMOS 0.18-μm
Chapter 3
Conclusion and Future Work
3.1 Conclusion
In this thesis, we analyze the design of the low-voltage folded-switching mixer and low-voltage single-to-balanced LNA for the proposed architecture of low-IF receiver RF front-end. The two circuit blocks are implemented in TSMC CMOS 0.18-µm technology and simulated through Eldo-RF simulator. We have presented the measured parameters of the mixer in the Chapter 2. But the LNA is still under fabricated; we only provide simulated results in the Appendix.
A fully integrated, low-voltage, low-power, high gain, ac-coupled folded-switching mixer with current reuse is presented. The main advantages of the proposed new mixer topology are high voltage gain (8.99 dB), moderate noise figure (10.3 dB in simulation), moderate linearity (P1dB = -9 dBm and IIP3 = 4 dBm), operation at low supply voltage (Vdd = 0.7 V), and low power consumption (2.87 mW), and simplicity due to no common-mode feedback is necessary. As a result of process variations make the load resistors become larger and hence the measured results of the proposed mixer are not as good as the simulated results.
3.2 Future work
For higher frequency applications more accurate RF CMOS component models such as large size MIM capacitors and different inductance spiral inductors with higher Q-value should be built up for exactly matching network design in the future.
All parasitic effects including parasitic capacitance, series resistance and inductance must be considered carefully. A more precise and efficient EDA tool for extraction of the parasitic effects is quietly important.
For the RF front-end integrating with base band circuits, reduced supply voltages for RF front-end are necessary. Therefore it needs more efforts to make the RF and analog circuit blocks operate at sub-1V supply voltage and still have enough dynamic ranges and other comparable circuit performances.
In the future, the low-voltage folded-switching mixer and the low-voltage single-to-balanced LNA (see Chapter 4) need to be integrated in a single chip to realize the proposed low-IF receiver architecture.
Chapter 4 Appendix ：
Low-voltage (0.7V)
Single-to-Balanced Low-Noise Amplifier
4.1 Low-Voltage Single-to-Balanced LNA Design
As the first stage of receiver, a low-noise amplifier’s (LNA) main function is to provide enough gain to overcome the noise of the subsequent stages while adding as little noise as possible. Besides, an LNA should accommodate large signals without distortion, and frequently must also present the specific impedance, such as 50Ω, to the input source. The impedance is particularly important if a passive filter precedes the LNA, since the transfer function of many filters are quite sensitive to the quality of the termination.
In this work, we present a low-voltage single-to-balanced LNA operating at 0.7V supply voltage. It consists of two stages. One is the single-ended folded-cascode LNA
and the other is common-source/common-gate PMOS pair active balun. The
and the other is common-source/common-gate PMOS pair active balun. The