Chapter 2 Low-Voltage (0.7V) Folded-Switching Mixer
2.4 Simulation and Experimental Results
The low-voltage folded-switching mixer was simulated and fabricated by CMOS 0.18-µm technology. The measurement results show that it has 6.21dB RF port return loss, 12.7dB LO port return loss, 8.99dB conversion voltage gain and 6.96dB conversion power gain at 0dBm LO power, -9dBm P1dB, and 4dBm IIP3. The total power consumption is 2.87 mW very close to the simulated one, 2.83mW.
Fig. 2-13 shows the RF port input matching. The measured RF port input matching is shifting down to 1.5 ~ 1.9 GHz due to the inductance of L1 or L2 (see Fig.
2-4) increasing and the parasitic capacitances to the substrate being more serious than simulation. At 2.45 GHz, The measured RF port input matching is -6.21 dB and the simulated one is -13.2 dB. Fig. 2-14 is the comparisons between measured and simulated LO port input matching. The measured result is matched to the simulation.
But more parasitic capacitances to the substrate than the simulation result in not as sharp as the simulated curve at 2.45 GHz. The measured LO port input matching is -12.7 dB and the simulated one is -34.5 dB at 2.45 GHz.
Fig. 2-15 shows the measured and simulated conversion power gain. The primary reason for the two curves not matching is that the load resistors becoming larger by the process variations make the transistors in the switching stage (see Fig.
2-4) operate in linear region. The larger load resistors have more voltage drops across them and force the transistors in switching stage entering linear region due to insufficient voltage head room. By simulation again, the modified curve shown in Fig.
2-15 confirms this conclusion. There is 3-dB difference between the modified and measured conversion power curves resulting from the twice of simulated RF port input matching to the measured one. The measured conversion power gain at 0 dBm LO power is 6.96 dB. Fig. 2-16 shows the simulated and measured one dB
compression point. The simulated and measured P1dB is -15.5 and -9 dBm respectively. Fig. 2-17 is the comparisons between the simulated and measured third order intercept point. The simulated and measured IIP3 is -6 and 4 dBm respectively.
The linearity is improved due to the conversion gain decreasing. Fig. 2-18 is IF output waveform. From Fig. 2-18, the conversion voltage gain by the calculation is 8.99 dB.
We can not provide the measured noise figure because the measurement type is not accepted by CIC. The summary of the simulated and measured performances of the low- voltage folded-switching mixer is shown in Table 2-1.
Table 2-2 shows the comparisons with recently published works. Compared with other low-voltage mixers, this work has moderate conversion gain, higher linearity, and the lowest power consumption under 0.7V supply voltage.
Fig. 2-13 Simulated and measured RF port input matching
Fig. 2-14 Simulated and measured LO port input matching
Fig. 2-15 Simulated and measured conversion power gain
Fig. 2-16 Simulated and measured one dB compression point
Fig. 2-17 Simulated and measured third order intercept point
Fig. 2-18 IF output waveform of low-voltage mixer
Table 2-1 Summary of the performances of low-voltage folded-switching mixer
Specification Simulation Measurement
IF 1 MHz 1 MHz
Supply voltage (V) 0.7 0.7 RF input matching (dB) -13.2 -6.21 LO input matching (dB) -34.5 -12.7
Conversion power gain (dB)
11.4 @ LO 0dBm 6.96 @ LO 0dBm
P1dB (dBm) -15.5 -9
IIP3 (dBm) -6 4
NF (dB) 10.3 N/A Conversion voltage gain
(dB)
13.8 8.99
Core power dissipation (mW)
2.83 2.87
Total power dissipation (mW)
20.46 24.87
Table 2-2 Comparisons with recently published works
[25] [26] [27] This work
Gilbert cell folded-switching
Vdd (V) 1 0.6/0.8 1 0.7
Switched CMOS 0.18-μm
Chapter 3
Conclusion and Future Work
3.1 Conclusion
In this thesis, we analyze the design of the low-voltage folded-switching mixer and low-voltage single-to-balanced LNA for the proposed architecture of low-IF receiver RF front-end. The two circuit blocks are implemented in TSMC CMOS 0.18-µm technology and simulated through Eldo-RF simulator. We have presented the measured parameters of the mixer in the Chapter 2. But the LNA is still under fabricated; we only provide simulated results in the Appendix.
A fully integrated, low-voltage, low-power, high gain, ac-coupled folded-switching mixer with current reuse is presented. The main advantages of the proposed new mixer topology are high voltage gain (8.99 dB), moderate noise figure (10.3 dB in simulation), moderate linearity (P1dB = -9 dBm and IIP3 = 4 dBm), operation at low supply voltage (Vdd = 0.7 V), and low power consumption (2.87 mW), and simplicity due to no common-mode feedback is necessary. As a result of process variations make the load resistors become larger and hence the measured results of the proposed mixer are not as good as the simulated results.
3.2 Future work
For higher frequency applications more accurate RF CMOS component models such as large size MIM capacitors and different inductance spiral inductors with higher Q-value should be built up for exactly matching network design in the future.
All parasitic effects including parasitic capacitance, series resistance and inductance must be considered carefully. A more precise and efficient EDA tool for extraction of the parasitic effects is quietly important.
For the RF front-end integrating with base band circuits, reduced supply voltages for RF front-end are necessary. Therefore it needs more efforts to make the RF and analog circuit blocks operate at sub-1V supply voltage and still have enough dynamic ranges and other comparable circuit performances.
In the future, the low-voltage folded-switching mixer and the low-voltage single-to-balanced LNA (see Chapter 4) need to be integrated in a single chip to realize the proposed low-IF receiver architecture.
Chapter 4 Appendix ：
Low-voltage (0.7V)
Single-to-Balanced Low-Noise Amplifier
4.1 Low-Voltage Single-to-Balanced LNA Design
As the first stage of receiver, a low-noise amplifier’s (LNA) main function is to provide enough gain to overcome the noise of the subsequent stages while adding as little noise as possible. Besides, an LNA should accommodate large signals without distortion, and frequently must also present the specific impedance, such as 50Ω, to the input source. The impedance is particularly important if a passive filter precedes the LNA, since the transfer function of many filters are quite sensitive to the quality of the termination.
In this work, we present a low-voltage single-to-balanced LNA operating at 0.7V supply voltage. It consists of two stages. One is the single-ended folded-cascode LNA
and the other is common-source/common-gate PMOS pair active balun. The
schematic is shown in
Fig. 4-1. Following subsections we will discuss the analyses of input matching network, noise figure, and power consumption of the proposed LNA.
Fig. 4-1 Schematic of low-voltage single-to-balanced LNA
4.1.1 Input Matching
The input matching network is using inductive source degeneration. Fig. 4-2(a) is the input stage of the LNA and Fig. 4-2(b) is the small-signal equivalent model for the input stage of the LNA.
(a) (b)
Fig. 4-2 Narrowband LNA (a) with inductive source degeneration (b) and its equivalent small-signal model
Applying KVL to the input loop in the Fig. 4-2(b) we can write
1 )
Therefore, the input impedance is
s
For matching to the source impedance Rs,
s
And at series resonance,
gs
It can be seen from above equations that at series resonance the input impedance is purely real and proportion to Ls. By choosing Ls appropriately, this real term can be made equal to 50Ω. The gate inductor Lg is used to set the resonance frequency once the Ls is chosen to satisfy the criterion of a 50-Ω input impedance.
4.1.2 Noise Figure
In this subsection we will introduce the power-constrained noise optimization technique and apply this to the design of the proposed LNA [6], [9], [10]. First, use (2.5) to determine the necessary optimum device width for the power-constrained optimum NF.
Then, bias the device with the amount of current allowed by power constrain. Finally, select the value of source degeneration inductance required for the desired input impedance and set the gate inductance to resonate at the operating frequency.
Having outlined the basic design procedure, we now turn the attention to the
derivation of the noise figure.
Fig. 4-3 shows the complete small-signal model for LNA noise calculation.
Fig. 4-3 Small-signal noise model of the MOS
In this model, Rl represents the series resistance of the inductor Lg, Rg represents the distributed gate resistance of the NMOS device and its value is given by [11],
L
device. The noise power due to Rl can be neglected because the metal wire of the inductor has significantly lower sheet resistance. In salicided CMOS processes the sheet resistance (Rsheet) can be greatly reduced, so the thermal noise contribution of Rg to the output noise power is also neglected. For simplicity, assuming that the channel thermal noise dominates for noise figure calculations, we have
m
Where Gmis the overall input stage transconductance and at resonance is equal to
in
Substitute (4.9) to (4.8), yielding
2
Substitute (2.9) into Nadd f
=ω denotes the quality factor of the input matching network.
According to (2.10), the best noise figure is obtained for Qin approach to ∞, which means Zin must be zero and the input matching condition and the minimum noise figure can not be reached simultaneously. But if we set the device width with Wopt , a reasonable input match is guaranteed while providing nearly the best noise figure with specified power consumption by the inductive source degeneration.
To gain more insight to (2.10), let us rearrange the NF by substitute Zin
gs
We can indicate that NF decreases as Lg increases. This equation provides valuable design guideline.
4.1.3 Power Dissipation
In this subsection we will derive the dependence of power dissipation on technology and circuit parameters under matching condition with a given bias voltage.
At first,
DD D
D
I V
P =
(4.13)where IDis the drain current of the M1operated in saturation region and IDis
( )
2Finally, we want to express gm and Cgs in terms of circuit element parameters under matching condition. That is
s
Then, substitute (4.16) and (4.17) into (4.15), we get
⎟⎟⎠
From (4.19), we conclude that PD decreases as Lg goes up. A similar situation is in NF.
4.1.4 On-Chip Active Balun
There are various types of baluns [11] such as a passive type, a source/drain type [12], a push-pull active type [13], a distributed active type [14], and a
common-source/common-drain FET pair active type [15], [16]. The passive balun has a large circuit area and is not suitable for integration request. A push-pull type and distributed active balun does not have low power consumption. A source/drain type does not have broadband performance. On the other hand, a common-source/common-drain FET pair type as shown in Fig. 2-4 has broadband performance and low power consumption and hence is a strong candidate for this work.
Fig. 4-4 Differential topology for active balun
The RF signal applied to the gate of the transistor will ideally split equally in magnitude and have 180° phase difference between the two output signals (see Fig.
4-4). In other words, the small signal gate-source voltage for the pair is equal, and can be expressed as
2 2
1 RF
gs gs
V V
V = = (4.20)
Because of the non-ideal current source results in unequal signal distribution, therefore leading imbalance in the differential signal. In this work, we proposed a modified topology as shown in Fig. 2-5 to improve output impedance of the current
Fig. 4-5 New differential active balun topology
In Fig. 4-5, we use an inductor Lt to replace the current source. Besides, the NMOS pair is replaced by the PMOS one for the reason of biasing this balun. So the original current source biasing is turned to fixed gate voltage biasing while the topology has the same circuit function as the one shown in Fig. 4-4. Further more, it is unsuitable for low supply headroom that a current source is stacked below the NMOS pair (see Fig. 4-4). In Fig. 4-5, the inductor Lt served as a RF choke is short-circuited at DC and hence ideally has no voltage drop to reduce voltage headroom, which makes the topology shown in Fig. 4-5 suitable to operate at low supply voltage. In addition, Lt is like a source degeneration inductor and hence improves linearity of the LNA. The complete schematic of proposed low-voltage single-to-balanced LNA is
shown in
Fig. 4-1.
4.2 Layout and Measurement Consideration
The most layout guidelines for the single-to-balanced LNA are the same in section 2.3. Fig. 4-6 shows the layout of the LNA, and the total chip size is 1.393 × 1.383 mm2. The low-voltage LNA is designed for on-wafer measurement so the layout must follow the rules of CIC (Chip Implementation Center)’s probing testing [13].
This circuit needs a 3-pin RF GSG probe, a 5-pin differential RF GSGSG probe, and two three- pin DC probes. Fig. 4-7 shows the on-wafer measurement setup with the four probes. The top and bottom probes are DC PGP probes which provide power supply and necessary DC bias for the circuit. The left and right is RF GSG and RF GSGSG probes respectively. The Fig. 4-7 ~ Fig. 4-10 show the measurement setup for S-parameters, noise figure, 1 dB compression point, and input-referred third-order intercept point. We will discuss the simulation results in the following subsection.
Fig. 4-6 Chip layout of the proposed LNA
Fig. 4-7 On-wafer measurement diagram
(a) (b)
Fig. 4-8 Measurement setup for (a) S-parameters (b) noise figure
Fig. 4-9 Measurement setup for 1-dB compression point
4.3 Simulation Results and Comparisons
The simulation results at 2.45GHz reveal that input matching is -37.6dB (shown in Fig. 4-11), gain (S21/S31) is 13.6 / 14.2dB (shown in Fig. 4-12), reversed isolation (S12/S13) is -69/-47dB (shown in Fig. 4-13), noise figure is 2.81dB (shown in Fig.
4-14), power gain is 14.6dB, P1dB is -12.7dBm (shown in Fig. 4-15), and IIP3 is -8.24dBm (shown in Fig. 4-16). The simulated gain and phase mismatch is below 1dB and 2 degrees around 180° in the 700MHz bandwidth from 2GHz to 2.7GHz (see Fig.
4-17 and Fig. 4-18). The total power consumption is 15.66mW. The summary of performances of proposed LNA is listed in Table 4-1. Table 4-2 shows comparisons of the proposed LNA and recently published low-voltage LNA designs.
Fig. 4-11 Simulated input matching (S11)
Fig. 4-12 Simulated gain (S21/S31)
Fig. 4-13 Simulated reversed isolation (S12/S13)
Fig. 4-14 Simulated noise figure
Fig. 4-15 Simulated 1-dB compression point
Fig. 4-16 Simulated input-referred third-order intercept point
Fig. 4-17 Simulated gain mismatch between S21 and S31
Fig. 4-18 Simulated phase mismatch between S21 and S31
Table 4-1 Performance summary of the low-voltage single to balanced LNA
Specification Simulation
Frequency 2.45 GHz
Vdd 0.7 V
S11 -37.6 dB
S21/S31 13.6 / 14.2 dB S12/S13 -69 / -47 dB
NF 2.81 dB
Power Gain 14.6 dB
P1dB -12.7 dBm
IIP3 -8.24 dBm
Power Consumption 15.66 mW
Table 4-2 Comparisons of recently published low-voltage LNA designs and this work
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