Chapter 1 Introduction
1.4 Thesis Outline
In Chapter 1, the various kinds of applications, the advantages and the disadvantages of Poly-Si TFT’s are introduced in a brief overview of the Poly-Si TFT technology. Then, several mobility models for Poly-Si TFT’s are discussed, and these models mainly emphasize on the effect of energy barrier height caused by grain boundary defects in Poly-Si TFT’s.
Finally, the motivation of this work to study the parasitic resistance modeling of Poly-Si TFT’s with LDD structure is expressed.
In Chapter 2, the fabrication process and the measurement experimental conditions of the Poly-Si TFT’s used in this work are firstly described in brief. Following that, the proposed mobility model is presented and the physical basis of the proposed mobility model is also interpreted. The mobility extraction method from the measured data used in this work is
introduced and the extracted field effect mobility of the Ploy-Si TFT without LDD structure is then modeled over the wide range of gate voltage and temperature by the proposed mobility model. Besides, the measured transfer characteristics of the Poly-Si TFT without LDD structure are also simulated over the wide range of gate voltage and temperature basing on the field effect mobility fitting results of the proposed mobility model.
In Chapter 3, the parasitic resistance extraction method used in this work is introduced to extract the values of the parasitic resistance under different gate biases and several temperatures for the Poly-Si TFT’s with various LDD lengths. The dependence between the extracted parasitic resistance and the gate voltage is checked to discuss the possible mechanism. Next, the device simulation results including the current density distribution results and the vertical electric field distribution results performed by Silvaco TCAD are presented. Afterwards, the parasitic resistance model basing on the experimental results and the simulation results is proposed. The extracted parasitic resistance of the Poly-Si TFT’s with various LDD lengths is then modeled over the wide range of gate voltage and temperature by the proposed parasitic resistance model. Finally, the measured transfer characteristics of the Poly-Si TFT’s with various LDD lengths are also simulated over the wide range of gate voltage and temperature basing on the field effect mobility fitting results of the proposed mobility model from the Poly-Si TFT without LDD structure and the parasitic resistance fitting results of the proposed parasitic resistance model from the Poly-Si TFT’s with various LDD lengths.
In Chapter 4, the conclusions of the works done in this thesis are given.
In Appendix, the proposed mobility model is derived in detail and the physical basis is also interpreted particularly. In addition, the proposed model is verified in different devices including N-type devices and P-type devices and the analysis of the verification results are given.
Chapter 2
Modeling of the Poly-Si TFT’s without LDD Structure
2.1 Device Fabrication Process and Measurement Conditions
The typical top-gate, coplanar self-aligned Poly-Si TFT’s which were fabricated on the glass substrates and crystallized by excimer laser annealing (ELA) recrystallization technology are used in this study. The Poly-Si TFT’s with and without LDD structure were also fabricated, respectively. The schematic cross-sectional view of the devices with LDD structure is shown in Fig.2-1, and that of the devices without LDD structure is shown in Fig.2-2. The device fabrication process is described below.
First, the oxide buffer layer was deposited on the glass substrate to prevent the diffusion of the impurities existing in the glass substrate from the silicon layer. Then, the undoped 50-nm-thick a-Si layer was deposited on the buffer layer. After that, the a-Si films were recrystallized by ELA method with 420 mJ / cm2 laser energy, and the recrystallized Poly-Si films were patterned into the active islands. Afterward, the gate insulator layer was deposited.
Here the gate insulator layer was combined with the 50-nm-thick oxide layer and the 20-nm-thick nitride layer. Next, phosphorus ions were implanted to form the n＋ source/drain regions and the n－ LDD regions. These dopants were activated by thermal process. Finally, metal layer was deposited and then patterned for the source/drain and gate regions as the metal pads.
The electrical characteristics of the 6μm channel width and 6μm channel length N-type Poly-Si TFT without LDD structure were measured under various temperatures which varies form 233K to 373K to check the accuracy of the proposed mobility model, and those of the 6μm channel width and 6μm channel length N-type Poly-Si TFT’s with different LDD lengths which varies from 0.5μm to 3.5μm were also measured over the wide temperature range to
check the influence of the LDD structure. Therefore, the further study of the parasitic resistance effect can be achieved basing on these measured data.
2.2 Modeling of Field Effect Mobility
2.2.1 The Proposed Mobility Model for Poly-Si TFT’s
In Poly-Si TFT’s, the gate-bias-induced charges will be captured by the trap states associated with the grain boundaries. At small gate biases, the energy barrier height at grain boundaries is still large and influences field effect mobility very seriously. Free carriers transport through grain boundaries by thermionic emission to overcome the energy barrier height at small gate biases. Therefore, field effect mobility will increase as temperature increases.
On the contrary, at large gate biases, the energy barrier height at grain boundaries is almost suppressed by gate-bias-induced charges. Thus, the dominated mechanism of field effect mobility is changed to phonon scattering and mobility will decrease with increasing temperature. Both thermionic emission effect and phonon scattering effect were considered in the proposed mobility model and the equation is given as: [14]
β
L
GB is the grain boundary size of the Poly-Si film;μ
G is the carrier mobility at the intra-grain regions;E
A is the activation energy, or the energy barrier height at grain boundaries;k is Boltzmann constant;
μ
T0 is the constant mobility at high gate biases at 298K;T is the environment temperature with the unit of Kelvin;
T
0 is the reference temperature which defined as the room temperature, 298K;β
is the temperature dependence coefficient to describe phonon scattering effect.Besides, oxide-silicon interface scattering effect also has to be considered. A common empirical form to describe interface scattering effect is used in the proposed mobility model.
Then, the final field effect mobility can be given as:
(
effGS T)
FET = + ⋅
V
−V θ
μ μ
1 (2-2) where
θ
is the gate bias dependence coefficient to describe oxide-silicon interface scattering effect and VT is the threshold voltage of device.2.2.2 Mobility Extraction Method
The field effect mobility of the Poly-Si TFT without LDD structure is extracted from the measured data according to the general drain current equation in linear region as shown below:
The drain current versus gate voltage (i.e. IDS-VGS, the transfer characteristic) data were all measured at drain voltage VDS=0.1V under different environment temperatures, then the mobility can be calculated individually to get the complete mobility versus gate voltage results (
μ
-VGS) at VDS=0.1V for each environment temperature. The calculation method is described as:where the threshold voltage VT is extracted by constant current method and the normalized
threshold current is set as
W
/L
×10−9A.2.2.3 Mobility Modeling Results
The measured transfer characteristic data of the 6μm channel width and 6μm channel length N-type Poly-Si TFT without LDD structure at drain bias VDS=0.1V over the temperature range from 233K to 373K are used to extract the field effect mobility values.
After that, the proposed mobility model is then applied to model the extracted field effect mobility.
First, the average grain size (i.e. LG) value of the Poly-Si film has to be determined.
Hence, the sample of the Poly-Si film after ELA recrystallization process with 420 mJ / cm2 laser energy was analyzed by the scanning electron microscopy (SEM). The top view SEM image of the Poly-Si film is shown in Fig.2-3 and the value of the average grain size is taken as 0.8μm.
In addition, the activation energy (i.e. EA) is also extracted at each gate voltage from the measured transfer characteristic data. The activation energy is extracted from the slope of the Ln(IDS) (the natural logarithm of the drain current) versus 1/kT (the reciprocal of the thermal energy) curve at each gate voltage, and the curves for several gate voltages are shown in Fig.2-4. In fact, the value of the activation energy is equal to the negative number of the slope and then the activation energy is extracted. The activation energy of the Poly-Si TFT without LDD structure is shown in Fig.2-5.
After the global fitting step according to the proposed mobility model, the comparison between the extracted field effect mobility and the modeling field effect mobility for the Poly-Si TFT without LDD structure is shown in Fig.2-6 and excellent agreement over the wide range of gate voltage and temperature is obtained. The values of the all model parameters of the proposed mobility model for the Poly-Si TFT without LDD structure are summarized in Table I.
2.3 Modeling of Transfer Characteristics
Furthermore, the transfer characteristics are simulated from Eq.(2-3) by adopting the mobility fitting results of the proposed mobility model. The comparison of the measured transfer characteristics and the modeling transfer characteristics for the Poly-Si TFT without LDD structure is shown in Fig.2-7. Good agreement over the wide range of gate voltage and temperature between the raw measured transfer characteristic data and the modeling transfer characteristic results is achieved spontaneously.
Chapter 3
Modeling of the Poly-Si TFT’s with LDD Structure
3.1 The Parasitic Resistance Effect of LDD Structure 3.1.1 Parasitic Resistance under Various LDD Lengths
According to the measured transfer characteristic data from the Poly-Si TFT without LDD structure, the device resistance is calculated at each gate voltage and the relation between the device resistance and the gate voltage is obtained. These device resistance values are taken as the reference values of the channel resistance. Because the Poly-Si TFT’s with and without LDD structure were all fabricated in the same run, the channel resistance of these devices is regarded as identity. Therefore, the additional resistance caused by LDD structure can be obtained by subtracting the reference channel resistance from the device resistance calculated from the Poly-Si TFT’s with LDD structure at each gate voltage, and this additional resistance can be regarded as the parasitic resistance.
The parasitic resistance caused by LDD structure is calculated for the 6μm channel width and 6μm channel length Poly-Si TFT with 0.5μm, 1μm, 1.5μm, 2μm, 3μm and 3.5μm LDD length. The relation between the parasitic resistance and the gate voltage is checked for various LDD lengths over the whole gate bias range, and the phenomenon of the decreasing parasitic resistance with increasing gate voltage is observed in the all Poly-Si TFT’s with LDD structure. Thus, the decided dependence between the parasitic resistance caused by LDD structure and the gate voltage is now confirmed.
In order to further study the influence of the gate bias on the parasitic resistance of the Poly-Si TFT’s with different LDD lengths, a percentage analyzing method is used under well-above threshold region. The parasitic resistance value at VGS=3V is taken as the reference resistance and the ratio of the parasitic resistance to the reference resistance is
calculated at each gate voltage from VGS=3V to VGS=15V for the all Poly-Si TFT’s with LDD structure. The decreasing percentage comparison between the Poly-Si TFT’s with different LDD lengths is shown in Fig.3-1. It is obvious that the percentage decreases more rapidly for the Poly-Si TFT’s with shorter LDD lengths.
Besides, the comparison between the parasitic resistance and the LDD length under several well-above threshold gate biases is also checked in Fig.3-2. The linear relation is observed in the long LDD length region. The parasitic resistance of the short LDD length region, such as 0.5μm and 1μm, seems larger than the resistance value predicted from the linear relation observed in the long LDD length region. It is clear that gate voltage plays an important role in parasitic resistance from the above, especially for short LDD region. Hence, the influence of the gate voltage can be deduced that the gate bias may only control a limited region around the gate electrode.
3.1.2 Device Simulation Results
The device simulation tool, Silvaco TCAD including the process simulator ATHENA and the device simulator ATLAS, is applied to perform the device simulation and to further study the influence of the gate voltage and the LDD length on the parasitic resistance. The device structure used in this device simulation work is shown in Fig.3-3.
The current density distribution of the device with and without LDD structure is firstly simulated and compared in Fig.3-4 and Fig.3-5. It is very obvious that the current density distribution shows a very different performance around the gate electrode between the two structures. The current path seems to extend from the channel region into the LDD region in the device with LDD structure. In other words, this current extending effect seems to cause the extended channel length, ΔL. On the contrary, the current path of the device without LDD structure is regular, the current extending effect does not occur.
In addition, the vertical electric field distribution of the two device structures is also
simulated, and the simulation results are shown in Fig.3-6. Both the device structures show the respectable vertical electric field distribution alongside the gate electrode. This electric field may be the reason that the current path of the device with LDD structure extends into the LDD region. Because of the existence of the vertical electric field around the gate electrode, the current path is induced and bounded unceasingly even the carriers have flowed out the gate-electrode-directly-controlled region, i.e. the channel region. But for the device without LDD structure, the current extending situation is not noticeable. That may be due to that the extended vertical electric field distributes just above the highly-doped source/drain region and the current extending effect is concealed.
According to the simulation results for the device with LDD structure given above, it seems that there is a parasitic transistor with the channel length which is equal to the extended channel length, ΔL. The channel resistance and the resistance caused by the parasitic transistor can be combined in series.
Finally, the dependence between the extended channel length and the gate voltage is checked by simulating the current density distribution for the device with LDD structure at different gate voltages. The same simulation work is also done for the device without LDD structure. The simulation results are shown in Fig.3-7. From the simulation result of the device with LDD structure, the extended channel length ΔL increases with increasing gate bias, but the variation is not very huge. The variation of the ΔL values is less than 0.2μm from low gate bias (VGS=3V) to high gate bias (VGS=15V). Besides, the extended channel length is not notable for the device without LDD structure at every gate bias.
3.2 Modeling of Parasitic Resistance
3.2.1 The Parasitic Resistance Model for Poly-Si TFT’s with LDD Structure
From the parasitic transistor assumption, the first part of the proposed parasitic resistance model can be set up. Similar to a simple Poly-Si TFT structure, the equation includes theactivation energy term to describe the temperature response due to thermionic emission effect.
In addition, it is expectable that the power dependence on gate voltage will be less than unity because the gate bias does not control the extended channel region directly. Thus, the parasitic resistance model equation basing on the parasitic transistor effect can be written as:
(
GS TN)
αΔL is the channel length of the parasitic transistor, i.e. the extended channel length;
W is the channel width of the parasitic transistor, the same as the width of the device;
V
TN is the effective threshold voltage of the parasitic transistor;α
is the gate voltage dependence coefficient;E
AN is the activation energy of the parasitic transistor;k is Boltzmann constant;
T is the environment temperature with the unit of Kelvin;
K
N0 is a fitting parameter and means the product of Ceff andμ
N. The Ceff term is the effective gate insulator capacitance of the parasitic transistor, andμ
N is the carrier mobility at the intra-grain region of the parasitic transistor.Following the parasitic transistor, the resistance caused by the remaining LDD region in the device with larger LDD length is considered. Without modulating by gate voltage, this region can be treated as a pure resistor with a constant resistance at some temperature. In order to study the temperature response of the Poly-Si TFT’s with LDD structure particularly, the temperature response of this series resistance has to be checked. Due to the higher doping
concentration in LDD region than in channel region, plenty of the ionized space charges exist in LDD region. Therefore, the mechanism of the temperature response in the series resistance region is preferred to be considered as impurity scattering effect. Then the parasitic resistance model equation basing on the series resistance can be written as:
γ
R
T0 is the constant resistance of the series resistor at 298K;T is the environment temperature with the unit of Kelvin;
T
0 is the reference temperature which defined as the room temperature, 298K;γ
is the temperature dependence coefficient to describe impurity scattering effect.After giving the proposed parasitic resistance model equations basing on parasitic transistor effect and impurity scattering effect, the completed parasitic resistance model can be finally written as:
( )
3.2.2 Parasitic Resistance Modeling Results
The measured transfer characteristic data of the 6μm channel width and 6μm channel length N-type Poly-Si TFT’s with LDD structure at VDS=0.1V over the temperature range from 233K to 373K are used to calculate parasitic resistance values. The proposed parasitic resistance model is then applied to model the extracted parasitic resistance.
First, the value of the extended channel length ΔL (i.e. the channel length of the parasitic transistor) is checked. From the simulation results and the experimental data analysis such as Fig.3-2, ΔL is estimated at about 0.6μm to 0.7μm. In order to simplify the parameter
extraction procedure, the value of ΔL is chosen as the constant value, 0.65μm. But for the Poly-Si TFT with 0.5μm LDD length, the value of ΔL will be set as 0.5μm, that is, it is considered as that the parasitic resistance of the Poly-Si TFT with 0.5μm LDD length is only contributed by the parasitic transistor effect. Besides, it is hard to extract the effective threshold voltage of the parasitic transistor (i.e. VTN), so this parameter is treated as a fitting parameter for the time being.
The activation energy of the parasitic transistor (i.e. EAN) is also extracted at each gate voltage from the extracted parasitic resistance of the Poly-Si TFT with 0.5μm LDD length.
The activation energy is extracted from the slope of the Ln(RP) (the natural logarithm of the parasitic resistance) versus 1/kT (the reciprocal of the thermal energy) curve at each gate voltage, and the curves for several gate voltages are shown in Fig.3-8. Then, the extracted activation energy of the parasitic transistor is shown in Fig.3-9. In addition, the activation energy of the parasitic transistor is shown and compared with the activation energy of the Poly-Si TFT without LDD structure in Fig.3-10. From the figure, it can be found that the dependence between the gate voltage and the activation energy of the parasitic transistor is a little slighter than the dependence between the gate voltage and the activation energy of the Poly-Si TFT without LDD structure because the gate bias does not modulate the parasitic transistor directly.
Moreover, the value of the temperature dependence coefficient to describe impurity scattering effect
γ
is also checked. Theγ
coefficient can be extracted from the slope of theMoreover, the value of the temperature dependence coefficient to describe impurity scattering effect