Chapter 1 Introduction
1.2 Thesis Overview
This thesis introduces a high sensitivity front-end circuit and a super-regenerative receiver with low power consumption and low energy efficiency operation.
In Chapter 2, the oscillator-based front-end circuit with self-calibration mechanism is presented. The system considerations about oscillator design and frequency calibration are addressed. Then the circuit implementations and measurement result are presented in detail.
In Chapter 3, the fundamental operation in super-regenerative receiver will be shortly addressed, followed by the introduction of the generic SR-RX architecture. In Chapter 4, the proposed SR-RX with ∆Σ-PWD and fast frequency calibration is presented with its design consideration. Then the circuit implementations and measurement result are presented in detail. Finally, the conclusions and future work of this thesis are described in Chapter 5.
Equation Chapter 2 Section 1
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
4
Chapter 2
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
2.1 Introduction
This chapter introduces an oscillator-based self-calibrated front-end circuit for DNA detection application with piezoresistive microcantilever. Next section introduces the design considerations with carefully analysis. Then the circuit implementations are presented. Followings are the measurement setup and experimental results.
Fig. 2.1 Architecture of microcantilever for DNA detection.
Chapter 2
2.2 The Proposed Front-end Circuit Architecture
The main target for detecting the piezoresistive microcantilever is to separate the different equivalent resistance between the connections of probe DNA and target DNA as shown in Fig. 2.1. The probe DNA is the DNA that is used for experimental test.
The target DNA is embedded on the microcantilever after post-processing [4][5].
After the probe DNA hybridizing with the target DNA because of the matching generic series, the cantilever may bend over and the equivalent resistance will change (increase or decrease may vary due to architecture and material). In this application, the resistance variation is as low as 0.02% of the original resistance. In the published papers, there are many way that are adopted to detect the resistance variation [6]-[8].
One conventional way to detect the variation of resistor may apply bridge topology which may suffer from the resistor offset problem as shown in [9] as shown in Fig. 2.2 (a). Another high dynamic range sensing topology by monitoring the current on the resistance can detect very wide range (140 dB) resistor variation [10][11] as shown in Fig. 2.2 (b). However, the resolution is not smaller enough to separate the tiny variation because of the limitation of clock frequency of the decoder that is used to transfer the resistance to digital code.
R
R R
R
sensorV
out+
-
AMP(a)
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
Fig. 2.2 Conventional way for resistance variation detection architecture (a) bridge architecture (b) current sensing architecture.
In this work, we proposed an oscillator-based self-calibrated topology as shown in Fig. 2.3. The system composes of an sensor-merged oscillator, a buffer, a divider, a mixer, a frequency to digital (F-to-D) converter, and a calibration controller.
÷ 4
Fig. 2.3 Proposed DNA detection architecture.
Chapter 2
The microcantilever is embedded in the ring oscillator whose frequency is decided by the three delay element with different time constant. The detail analysis with the oscillation frequency and the sensing resistance will be analyzed in the following section. The oscillation frequency is pull to rail-to-rail by an inverter buffer for the digital circuit. A divided by 4 block is connected at the output of the buffer which can make sure that the output clock is 50% duty cycle and to prevent the frequency-pulling due to the external clock FCLK at another input of mixer. The mixer down-converts the frequency difference between FCLK and FDIV to the output frequency at FOUT. Then the digital output can be obtained through the F-to-D converter to convert the output frequency to the digital code.
F
DIV=10 MHz
F
CLK=9.8 MHz
R F
OUT=200 kHz
F
DIV=10.002 MHz (0.02% variation)
F
CLK=9.8 MHz
R +
∆R F
OUT=202 kHz
After DNA hybridization
Fig. 2.4 Operation of down-conversion.
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
8
From this topology, the resistance variation is reflected by the output frequency of oscillator. The small variation that is caused by the resistance is amplified in the time domain due to the down-converter action. An example is shown in Fig. 2.4. The original frequency variation is 2 kHz. Compared with the oscillation frequency 10 MHz, the variation is hard to tell. Hence, the down-converter is designed to amplify the variation frequency in time domain. The output frequency is 200 kHz which is quite smaller for the variation frequency to separate. The required resolution of the decoder is much relaxed to design.
The output frequency of the oscillator before sensing resistance is varied due to process, voltage, and temperature variation. Hence, a calibration loop must be added in the system that can calibrate the oscillation frequency. In the proposed system, a self-calibrated scheme is adopted for frequency tuning which will be told in detail later.
2.3 Circuit Implementations
The proposed oscillator-based self-calibrated front-end circuit is depicted in Fig.
2.3. The calibration controller is implemented by Verilog synthesis. The detailed circuit implementations are introduced next with simulation results.
2.3.1 Sensor-merged Ring Oscillator
As shown in the sensor merged oscillator is composed by three delay stages. The oscillation frequency is decided by three-stage time constant. Because of the system detection requirement, the frequency shift due to the resistance variation must be as large as possible. In circuit analysis, R1=R2, C1=C2, and three MOS is equivalent for simplicity. The following is three cases.
Chapter 2
Fig. 2.5 Sensor-merged ring oscillator.
Case I: R
sensC
3=R
1C
1From mathematical analysis, the loop gain of the oscillator can be obtained as
3
The circuit oscillates when the phase shift of frequency dependent term equals 180°, that is the imaginary part of the loop gain is zero when s=jω. Then we can get the function
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
10
To analyze the frequency drift due to the resistance variation, the assumption is made that ∆ω is the frequency shift due to the resistance change. Then from the equation (2-1) loop gain changes to
3 3
By calculating the imaginary part of the loop gain, the oscillation frequency is shown as
Which we can find out that the output frequency is a linear function of the small resistor drift coefficient ∆ω with a one over square root three constant slope.
Case II: R
sensC
3<R
1C
1Calculate the oscillation frequency by making the imaginary part as zero
2
Rearranging the equation above that we can get the oscillation frequency
( )
0 0
2osc sens
ω
=ω ω
+ω
(2-9)Chapter 2
As shown in Case I the oscillation frequency, to analysis the frequency drift due to the resistance shift the ∆ω is modeled as the variation.
3 3
By calculating the imaginary part of the loop gain, the oscillation frequency is shown as
From the equation that when the ωsens>ω0,the frequency slope with small resistor range is smaller than Case I.
Case III: R
sensC
3>R
1C
1The pole of the sensor stage is assumed to be ωsens that is much smaller than the other two stages. Followed by the analysis above, the loop gain of the oscillator is
3
As shown in Case I, to analysis the frequency drift due to the resistance shift the
∆ω is modeled as the variation.
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
By calculating the imaginary part of the loop gain, the oscillation frequency is shown as
From the equation that when the ωsens<ω0, the frequency slope with small resistor range is larger than Case I.
From the three cases above, to sum up, the RC design of the sensing stage should be larger than other stage. The simulation result is shown in Fig. 2.6. From the figure, the simulation result has the same tendency of our analysis above.
1.17 kHz/Ω
Fig. 2.6 Simulation result of different cases.
Chapter 2
The phenomenon also can be explained in the large signal view. The ring oscillator can be viewed as feedback system with three delay cells with different time constant RC. Case I means that three delay cells contribute same delay time for the specific loop delay time. Case II means that the sensor stage with smaller RC time constant contributes less delay and the other two stages contribute more delay. On the other hand, Case III means that the sensor stage with larger RC time constant has more delay time than other two stages. For example, if the output frequency is 25 MHz, the loop delay should be 40 ns. For Case III, the sensor delay may contribute 20 ns while other two delay cells contribute 10 ns, respectively. The resistance variation reflects the time constant of the delay cell. Because that the sensor stage contributes large delay time, the variation of the time constant is also larger than that in Case II and Case I. Hence, the frequency slope versus the sensor resistance is largest in three cases.
After analyzing the RC design of each stage, the ring oscillator is designed with optimized output frequency slope, as shown in Fig. 2.7. The sensing resistor is designed to be 2.5 kΩ; the output frequency Fsensor is set to 24 MHz; the slope is 7 kHz/Ω. The resistance variation due to DNA hybridization can be as small as 0.02% of the sensing resistor. Hence, the output frequency drift is around
7 / 2.5 0.02% 3.5
f kHz k kHz
∆ = Ω × Ω × = (2-16)
7 kHz/Ω
2.498 2.499 2.5 2.501 2.502
Rsensor(kΩ)
Fig. 2.7 Simulation result of oscillation frequency vs. sensing resistor.
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
14
Because of the PVT variation, the oscillation frequency is drifted away from the wanted frequency. The oscillator adopts the 8-bits capacitor array to regulate the output frequency. Fig. 2.8 shows the transfer curve of the oscillation frequency with different control bits.
tt+27 ℃ ff+0 ℃
ss+80 ℃
0
D
ctrl(code)
50 100 150 200 250
20 25 30 35 40
F
sensor(MH z )
Fig. 2.8 The transfer curve of oscillation frequency vs. digital control code.
2.3.2 Mixer and F-to-D Converter
From the above analysis, it can be concluded that the output frequency variation due to DNA hybridization is 3.5 kHz. To separate the difference of oscillation frequency, the resolution of F-to-D converter must smaller than 3.5 kHz. As shown in Fig. 2.4, the operation of mixer amplifies the frequency difference on time-domain.
The circuit implementations of the mixer and F-to-D converter are shown in Fig. 2.9.
Chapter 2
Fig. 2.9 Mixer and F-to-D converter.
The output of oscillator is send into a divided by 4 block to prevent frequency pulling between FCLK and Fsensor. Because that FCLK is given from instrument, the driving ability is stronger that the output of oscillation. Hence, when two frequency is very close, the oscillation frequency will be pulled to the frequency of FCLK. Without the divider, the pulling range is about 30 kHz that may limit the detection range of DNA hybridization. With the divider to act as a buffer, the pulling range will be reduced to less than 5 kHz. The simulation result is shown in Fig. 2.10. A DFF is used to act as mixer. The divided signal FDIV is sampled by the external clock FCLK and the output frequency is the frequency of the subtraction of FDIV and FCLK. The F-to-D converter is a counter that transfers the period of the output frequency to digital code.
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
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Fig. 2.10 Simulation result of frequency pulling.
The design of mixer output frequency FOUT is based on the sensing resistor variation which causes 3.5 kHz frequency drift. If the FOUT is designed too high, the time difference is hard to tell. For example, for FOUT=500 kHz, after DNA hybridization, FOUT=503.5 kHz. The period difference is 14 ns, which means that the counter clock Fcounter must larger than 71MHz. The clock rate is not practical for low-power design. Hence the FOUT must be as low as possible. However, if the output frequency is too low, the frequency change will become too low that make the mixer output frequency very close to 0 Hz which will mistake the frequency information. In the presented system, FOUT is designed to be 100 kHz. After DNA hybridization, FOUT=103.5 kHz which means that counter clock Fcounter is larger than 3 MHz. Hence in our design, Fcounter is 5 MHz.
2.3.3 Frequency Calibration Controller
The ring oscillator for front-end sensing is sensitive to the PVT variation and the sensor resistance value which may vary due to post-process variation and the sensor
Chapter 2
shape. Hence, a calibration scheme is required to establish the initial frequency before DNA hybridization. In the proposed calibration scheme the target frequency is based on the mixer output frequency FOUT. The architecture is shown in Fig. 2.11. A 8-bit cap array with control signal Dctrl<7:0> is added in ring oscillator to regulate the oscillation frequency. The initial value of Dctrl is 0000000, which means the oscillation frequency is the maximum in tuning range. Output frequency is also the maximum if the FCLK is fixed. A target digital code is stored in a register array to compare the output digital code of counter Dsens and the target digital code DTarget. The difference of the digital code is accumulated in another register that stores the control code Dctrl to regulate oscillation frequency. Initially, FDIV is larger than FCLK. When calibrating, if FDIV goes lower than FCLK, the mixer frequency is still the difference of two frequencies with absolute value. Hence, the calibration scheme needs to make sure that the FDIV won’t go lower than FCLK to prevent positive feedback.
÷ 4
Fig. 2.11 Frequency calibration architecture.
From the Fig. 2.12, the simulation result shows that the operation of the frequency calibration. The upper graph is the decimal value of Dctrl<7:0> that increases slowly to make the mixer output frequency close to the target frequency. The down graph shows the output waveform of mixer. At the beginning of calibration, the frequency of output
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
18
frequency is much higher than the target frequency 100 kHz. After frequency calibration, the output frequency of mixer can be calculated to be 98.4 kHz. The resolution of the calibration is acceptable.
10.16 µs
Fig. 2.12 Simulation result of frequency calibration.
2.4 Measurement Setup and Experimental Results
This section presents the testing environment, including the instruments and component circuits on the PCB. The experimental results of the proposed circuit will also be presented.
2.4.1 Measurement Setup
The chip is implemented in a 0.35-µm CMOS bio-MEMS process. The chip is originally designed for SoC that concludes DNA microcantilever with different shape (with the cooperation of Prof. Chih-Ting Lin and his research group), front-end circuit, and wireless RF module at back-end (with the cooperation of Prof. Shey-Shi Lu and his research group) as shown in Fig. 2.13(a). The chip photograph is shown in Fig.
Chapter 2
2.13(b). The total chip area is occupied with 5 mm x 6.08 mm. The oscillator-based self-calibrated readout circuit occupies small area compared with other building block.
(a)
(b)
Fig. 2.13 (a) SoC architecture (b) Chip photograph.
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
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The measurement setup is shown in Fig. 2.14. The mixer clock FCLK and counter clock Fcounter is given by a function generator for different frequency. The output frequency of counter is monitored by oscilloscope to observe the output frequency variation.
Fig. 2.14 Measurement setup.
2.4.2 Experimental Results
The measured characteristics of frequency variation versus time of the DNA SoC are shown in Fig. 2.15, where black squares and red circles represent match and mismatch DNAs, respectively. In these experiments, phosphate buffered saline (PBS) buffer is injected to initialize the DNA sensor. After the DNA sample injection and hybridization, unbinding DNAs are washed away by the PBS buffer. Finally, the sensing chamber is dried to obtain steady signals. Clearly, from Fig. 2.15, the difference of frequency-variation between match and mismatch DNA samples is 130 kHz. This result demonstrates unequivocally the sensing capability of the developed DNA SoC. It can be noted that there is 50 kHz frequency change in mismatch sample
Chapter 2
which is resulted from the non-specific binding of mismatch DNAs. This non-specific binding phenomenon has the same effect in match DNAs experiments. Therefore, this shifting can be eliminated by post signal process.
Fig. 2.15 Temporal responses of frequency variation for match and mismatch DNA conditions.
Fig. 2.16 shows the experimental result of match DNAs in different concentrations. The experimental protocol is the same as previous experiments but this experiment is designed to evaluate the sensitivity. In the graph, 200 kHz and 125 kHz frequency changes are induced by 1µM and 100 pM DNA, respectively. As a result, it presents an available detection range from 100 pM to 1 µM. This performance also demonstrates the developed DNA SoC is functional for most clinical applications.
Design and Implementation of a Front-end Circuit for Piezoresistive Sensing Applications
22
Fig. 2.16 Temporal responses of frequency variation for match DNA with different concentrations.
From the above measurement, the output frequency shift is larger than what we expected when designing system. To enlarge the detection range, the mixer output is set to 300 kHz for larger detection range. The measured frequency in Fig. 2.15 and Fig.
2.16 is the FCLK plus the output frequency of mixer. However, because the digital circuit in calibration and the MCU shares the same power domain, the failure of SRAM implementation makes the supply node and ground node short. Hence, the calibration scheme is unable to measure.
Table 2-1 shows the summary table of the DNA detection SoC. The oscillation frequency is 24 MHz, the detection sensitivity is designed 7 kHz/Ω. The total front-end system consumes 1 mW with 3-V supply.
Equation Chapter 3 Section 1
Chapter 2
Table 2-1 Performance summary of the DNA detection SoC
Technology TSMC 0.35µm Bio-MEMS CMOS
Chip Area 30.4 mm2
DNA sensor
Structure Cantilever Beam
Dimension (length, wide, thickness) 180, 80, 1.5 (µm)
Resistance 2.5 kΩ
Self-calibrated Readout Circuit
Power Consumption 1 mW @ 3 V
OSC Frequency 24 MHz
Detection Sensitivity 7 kHz/Ω
Digital Output Resolution 2 kHz/LSB
Resistance Resolution < 0.02 %
Introduction of a Super-Regenerative Receiver
24
Chapter 3
Introduction of a Super-Regenerative Receiver
3.1 The Fundamental of SR-RX
The SR-RX was invented by Armstrong in 1922. The main characteristics of the SR-RX are the low power operation and theoretically high front-end gain, which is suitable for demodulating amplitude-shift keying (ASK) and on-off keying (OOK) signal [12]. However the disadvantages of the SR-RX are bad frequency selectivity and requirement of high quality factor passive components [13][14]. However, for the biomedical applications, the power consumption is the most critical consideration in wireless system. The SR-RX is an appropriate candidate for this scenario.
The basic operation of super regenerative receiver is categorized into three modes:
linear mode, logarithmic mode, and self-quenching mode. The following is going to introduce these three operation modes and analysis the pros and cons of each operation modes [15].
3.1.1 Linear Mode
The fundamental operation of SR-RX is based on the start-up time of oscillator which is influenced by the injected signal power. As shown in Fig. 3.1, the core circuit is an oscillator which is controlled by a signal called quench signal. When quench signal is high, the oscillator can start oscillation. When quench signal is low, on the other hand, the oscillator is turned off.
The start-up time of the oscillator is based on the amplitude of the injected signal from antenna. When the receiver receives ASK ‘0’, the oscillator need to spend more
Chapter 3
time to start oscillation, while need less time to build oscillation when receives ASK
‘1’.
Fig. 3.1 Operation of linear mode SR-RX.
For linear mode operation, the oscillation built in a quench cycle is reset before the output voltage reaches saturation value. As shown in Fig. 3.1, when receiver
For linear mode operation, the oscillation built in a quench cycle is reset before the output voltage reaches saturation value. As shown in Fig. 3.1, when receiver