Chapter 4 Design and Implementation of SR-RX with ∆Σ-PWD and Fast Frequency
4.3 Design Considerations and System Analysis
4.5.2 Device-Under-Test Print-Circuit Board
The receiver is designed in TSMC 1P6M 0.18-µm CMOS process. The raw die is directly mounted on print-circuit-board (PCB). Including the ESD-protection pads, this chip occupies an area of 1.5 mm × 1.55 mm. Because the system needs a high-Q inductor for better sensitivity, the area of the inductor is quite large. Except the inductor, the core area is only about 0.5 mm2. The chip micrograph is shown in Fig.
4.14.
DCO
LNA
ED+LM
∆Σ−based
PWD Freq.
Calibration
Fig. 4.14 Chip micrograph
Chapter 4
A PCB is fabricated in order to test the SR-RX, and the PCB for the DUT is shown in Fig. 4.15. There are 6 power domains that is supplied by different LDO components: analog, digital, and 3V which is used for FPGA board. The 3-bit SIPO control signals are connected to the signal board. The data and clock are also connected to pins and sent to the chip. The input of the LNA is connected by a transformer and a matching network before receiving the signal from antenna. The output of ∆Σ-PWD will connect to the logic analyzer (LA) for spectrum analysis or connect to FPGA for demodulation.
SIPO
∆Σ-PWD output CLK
Antenna Matching network
+ transformer
Fig. 4.15 PCB for SR-RX testing
4.5.3 Experimental Results
The proposed SR-RX incorporating the ∆Σ-PWD and the fast frequency calibration dissipates 1.37 mA from a 1-V supply. The RX front-end which employs an on-chip inductor (Q~7) draws 900 µA, while the PWD only draws 60 µA.
To examine the effect of frequency calibration, a spectrum analyzer is used to monitor the LNA input to observe the leakage signal from the DCO. As shown in Fig.
Design and Implementation of SR-RX with ∆Σ-PWD and Fast Frequency Calibration
54
4.16 (a), before calibration, the initial oscillation frequency is at 388 MHz. After the frequency calibration, the DCO frequency is moved to near the desired 400 MHz. The reference frequency is chosen at 50 MHz. Fig. 4.16 (b) shows the calibration time, which is about 250 ns. This is close to the predicted 12 cycles (240 ns). This calibration time is less than the time span for transmitting one-bit data at 1 Mbps (1µs).
Before After
(a)
Enable
Finish 250 ns
(b)
Fig. 4.16 (a) Measured DCO output frequency, before and after frequency calibration.
(b) Measured calibration time.
Chapter 4
Fig. 4.17 shows the measure spectrum at the ∆Σ-PWD output. An external transmitter (from CC1100) sends OOK signal with periodic 101010 data with output power of -50 dBm to the RX chip. The ∆Σ-PWD output bit stream is recorded by a logic analyzer and converted to the output spectrum. For an OSR of 8, the SNR is around 10.8 dB, estimated with a bandwidth of 500 kHz. The idle tone in the MATLAB model simulation is eliminated because of the noise dithering of the pulse-width at the output of limiting amplifier. Hence, the idle tone in the 1st-order DSM can be reduced by noise dithering. However, the in-band noise floor is increased.
BW
Fig. 4.17 Spectrum at the
∆Σ-
PWD output.Fig. 4.18(a) shows the recorded PW at the limiting amplifier output versus the input power (Pin). From the graph, it is observed that when the input power is larger than -75 dBm, the output PW is increased with input power. Fig. 4.18(b) shows the measured frequency selectivity profile. The 3-dB bandwidth is around 13 MHz. The frequency selectivity is limited by the low-Q passive component (Q~7 for on-chip inductor). To enhance the frequency selectivity, off-chip high-Q inductors or Q-enhancement mechanism can be considered.
Design and Implementation of SR-RX with ∆Σ-PWD and Fast Frequency Calibration
56
(a)
(b)
Fig. 4.18 (a) Measured output pulse-width vs. PIN (b)Measured output pulse-width vs.
input frequency.
To demonstrate the overall RX operation, the output over-sampled code is decimated to extract the baseband data. Fig. 4.19 shows the transmitted and received data waveforms at 1-Mbps data rate. The transmitted data are sent by the CC1100, and are received/demodulated by the proposed RX with the ∆Σ-PWD. As shown in Fig.
4.19, the proposed SR-RX functions correctly.
Chapter 4
Data rate=1 Mbps RF power=-50 dBm Transmitted
Data
Received Data
1 µs
Fig. 4.19 Transmitted and received data at 1 Mbps.
Fig. 4.20 shows the measured bit error rate of the receiver. The FPGA send a PRBS to CC1100 and transmit to the proposed receiver. And the receiver demodulates the bit stream by FPGA and compared with the transmitted waveform. The number of bits for comparison is 1024. For BER less than 0.1%, the comparison will have 0 or 1 error bit when the BER is less than 0.1%.
Fig. 4.20 Measured bit error rate.
Table 3.1 shows the measured result compared with the original design target.
Table 3.2 shows the comparison table with the published papers.
Design and Implementation of SR-RX with ∆Σ-PWD and Fast Frequency Calibration
58
Table 4-2 Performance Summary
Design Target Measurement Result Process TSMC 0.18-µm CMOS TSMC 0.18-µm CMOS
Supply Voltage 1 V 1 V
Data Rate 1 MHz 1 Mbps
Center Frequency 400 Mbps 400 MHz
Seneitivity <-75 dBm -50 dBm
Modulation ASK/OOK OOK
Power Consumption < 1.5 mW 1.37 mW
Energy Efficiency < 1.5 nJ/b 1.37 nJ/b
Table 4-3 Comparison table
This work
07’JSSC [19] 09’JSSC [18] 10’JSSC [21]Resonator
On-chip
On-chip PCB On-chipFreq. Cal.
Time
250 ns
83 µs NA 1.5 µsChapter 5
Chapter 5
Conclusions and Future Works
5.1 Conclusions
This thesis introduces two systems blocks for wireless piezoresistive sensing applications. First, an oscillator-based self-calibrated front-end circuit is presented with high sensitivity to the resistance variation. The second system is a super-regenerative receiver with ∆Σ-PWD and fast frequency calibration.
In the front-end circuit design, an oscillator transfers the resistance information into frequency domain and a mixer down converts the frequency to lower frequency for demodulation. The down-conversion operation means the amplification in time domain to enhance the system sensitivity to the resistance variation.
In the receiver design, the proposed super-regenerative receiver adopts the
∆Σ-PWD to demodulate the received signal to improve the limitation of the conventional demodulator. A fast frequency calibration is also proposed to regulate the oscillation frequency to the specific frequency band with the SAR algorithm to finish the calibration in 12 reference cycles.
5.2 Future Works
The all digital operation is required in down-conversion system for the front-end circuit. It will consume too much power to pull the oscillation output signal to full swing. Hence, the power consumption can be reduced by implement the passive mixer
Conclusions and Future Works
60
with analog switches which can operate in very low power consumption. And the dynamic range of mixer can be increased.
The DCO oscillation frequency is drifted when receiving data in reality for a long while. Hence, instead of the foreground calibration as shown in this thesis, the back-ground calibration should be implemented in the SR-RX to prevent the operation frequency drifting for temperature or voltage variation. The sensitivity of the receiver can be more enhanced with other mechanism such as Q-enhancement technique.
References
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62
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