Thesis organization

In this thesis, we used FUSI HfSix as metal gate and Hf0.7La0.3ON as gate dielectric for n-MOSFETs.

In chapter 1, a brief review of high-κ/metal gate technology was given to describe their

application in CMOSFETs. It also shows the motivation to use FUSI HfSix metal gate and Hf0.7La0.3ON dielectrics.

In chapter 2, the detailed fabrication process of HfSix/Hf0.7La0.3ON n-MOSFETs and measurement procedure will be described.

In chapter 3, the device parameter extraction will be discussed first. Chapter 3.2 and 3.3 shows the results from the measurement and the detailed discussion of characteristics of HfSix/Hf0.7La0.3ON capacitors and n-MOSFETs. From the measurement, low EOT, low effective work function, low threshold voltage, low leakage current and high electron mobility were extracted. It also shows the comparison with other reported n-MOSFETs.

Chapter 4 summarizes the findings in this thesis and provides the suggested directions of future studies.

Fig. 1-1 Leakage current versus gate voltage for various thickness of SiO2 layers [1].

Year of

Equivalent Oxide Thickness (EOT) Requirements Extended Planar

Bulk (Å) 11 9 7.5 6.5 5.5

UTB FD-SOI (Å) 7 6

DG MOSFET (Å) 8

Gate Poly Depletion and Inversion-Layer Thickness Requirements Extended Planar

Bulk (Å) 7.4 3.1 2.9 2.8 2.7

UTB FD-SOI (Å) 4 4

DG MOSFET (Å) 4

Saturation Threshold Voltage Requirements Extended Planar

Fig. 1-2 International Technology Roadmap for Semiconductors (ITRS) 2007 for high performance logic technology. [2]

Manufacturable solutions exists, and are being optimized Manufacturable solutions are known

Interim solutions are known Manufactruable solutions are not known

Fig. 1-3 Static dielectric constant verse band gap for several popular metal oxides [3].

Fig. 1-4 Energy band offset of popular high-κ materials.

Fig. 1-5 The three contributions to the capacitance equivalent thickness (CET): gate oxide, poly depletion, and quantum delocalization.

Poly depletion

Oxide

p-type Si Poly-Si gate

EOT

tSi

tgate

gate Si

CET EOT t = + + t

Quantum delocalization

0 10 20 30 40 50 60 70 80 90 100

Fig. 1-6 The relationship between work function and atomic number. [13]

Fig. 1-7 The process flow of FUSI gate. (a) Gate patterning and S/D silicidation. The hard mask is not removed after pattering so that it can protect the gate from being silicided during the S/D silicidation, (b) Dielectric deposition and planarization, (c) Hard mask removal and Ni deposition, (d) Ni fully silicidation and removal of the remaining Ni.

Poly-Si

Silicidation

Hard mask Planarized oxide

Ni

(a) (b)

(d) (c)

Fig. 1-8 Energy band diagram and charging characteristic of interface states for the metal-dielectric system [28].

Fig. 1-9 Reported high-k materials in recent years. [31]

Chapter 2

The Experimental Steps and Measurements

In this thesis, HfSix/Hf0.7La0.3ON/Si MIS capacitor and transistor were fabricated to investigate their electrical characteristics. The starting wafer was 4-inch, (100) oriented p-type wafer with one side polished. After standard RCA clean (Fig. 2-1), wafers were put into the chamber of the physical vapor deposition (PVD) system, where Hf0.7La0.3O thin films were deposited on the wafers. Subsequently, oxygen post deposition anneal (PDA) was imposed on these samples.

After the PDA, a plasma nitridation were imposed on the Hf0.7La0.3O surface wafers to form Hf0.7La0.3ON film. Then, amorphous Si of 5 nm was deposited on the Hf0.7La0.3ON surface followed by a PVD deposition of 20 nm Hf. For the HfSix/Hf0.7La0.3ON/Si MIS capacitor, a 30 nm thick Mo was deposited by PVD to prevent Hf oxidation after the Hf deposition. For HfSix/Hf0.7La0.3ON/Si transistor, an additional amorphous-Si layer of 150 nm was deposited by PVD to avoid ion implantation damage through the gate. Gates of all samples were defined by lithography and etching.

After defining the gate, a phosphorous ion implantation at 35 KeV, 5×10¹⁵ cm^-2 dose was used to form n⁺source/drain (S/D) regions of transistors. Afterwards, rapid thermal anneal (RTA) at 1000^oC, 5 sec was used to activate carriers in S/D region. The FUSI HfSix gate was

also formed at this high temperature RTA, which is different from a conventional low temperature FUSI process. For comparison, TaN gates were also deposited on the Hf0.7La0.3ON to form the TaN/Hf0.7La0.3ON/Si MIS capacitor.

To analyze the electrical characteristics of these devices, we used HP4156 semiconductor parameter analyzer to measure the I-V characteristics. Besides, the HP4284A precision LCR meter was used to evaluate the C-V characteristic. The whole process is shown in Fig. 2.2 ~ Fig. 2.15.

1. DI water rinse, 5 min

2. H₂SO₄ : H₂O₂ = 3:1 , 10 min, 75~85^oC 3. DI water rinse, 5 min

4. HF : H2O = 1:100, 10~15 s 5. DI water rinse, 5 min

6. NH₄OH : H₂O₂ : H₂O = 1:4:20 , 10 min, 75~85^oC 7. DI water rinse, 5 min

8. HCl : H2O2 : H2O = 1:1:6, 10 min, 75~85^oC 9. DI water rinse, 5 min

10. HF : H₂O = 1:100, 10~15 s 11. DI water rinse

12. Spinner dry

Fig. 2-1 Standard RCA clean process.

Si

Fig. 2-2 4-inch (100) P-type wafer.

Si Hf

0.7

La

0.3

O

Fig. 2-4 Hf_0.7La_0.3O deposition by PVD.

Si

Fig. 2-3 Standard RCA clean.

Plasma Nitridation

Si Hf

0.7

La

0.3

O

Fig. 2-6 Plasma nitridation to form Hf0.7La0.3ON.

Si Hf

0.7

La

0.3

O

Fig. 2-5 Low temperature oxygen PDA.

O

2

PDA

Si Hf

0.7

La

0.3

ON

Amorphous Si

Hf

Fig. 2-8 Hf deposition by PVD (20nm).

Si Hf

0.7

La

0.3

ON

Amorphous Si

Fig. 2-7 Amorphous Si deposition by PVD (5 nm).

Si Hf

0.7

La

0.3

ON

Amorphous Si

Hf

Amorphous Si

Fig. 2-10 Amorphous Si deposition by PVD (150 nm) for n-MOSFETs.

Si Hf

0.7

La

0.3

ON

Amorphous Si

Hf

Fig. 2-9 Mo deposition by PVD (30 nm) for capacitors.

Mo

Lithography Patterning

Amorphous Si

Si Hf

_0.7

La

_0.3

ON

Hf

Fig. 2-11 Lithography patterning for capacitors and n-MOSFETs.

Amorphous Si P/R

Si Hf

0.7

La

0.3

ON

Amorphous Si

Hf

Mo

P/R

MASK

Etching

Si Hf

0.7

La

0.3

ON

Amorphous Si

Hf P/R

Mo

Fig. 2-12 Etching for capacitors and n-MOSFETs.

Si Hf

0.7

La

0.3

ON

Amorphous Si

Hf P/R

Amorphous Si

Si Ion Implantation

Fig. 2-13 Phosphorus ion implantation to form n⁺ source/drain for n-MOSFETs (35 KeV, 5×10¹⁵ cm^-2 dose).

Hf

_0.7

La

_0.3

ON

Amorphous Si

Hf Mo

Si

Amorphous Si

Hf

Amorphous Si

Hf

_0.7

La

_0.3

ON

S

D

Fig. 2-14 RTA at 1000°C, 5 sec for capacitors and n-MOSFETs.

Si

Amorphous Si

Hf

0.7

La

0.3

ON

HfSi

S D

Si Hf

_0.7

La

_0.3

ON

TaN

Fig. 2-15 A TaN gate capacitor for comparison.

Si Hf

0.7

La

0.3

ON

Mo

HfSi

Chapter 3

Result and Discussion

3.1 Device parameter extraction

In this thesis, EOT and VFB were extracted from the Quantum C-V simulation. Threshold voltage and mobility extraction was described in detail in the following sections.

3.1.1 Threshold voltage extraction

There are various methods for determining the threshold voltage. Here we use the linear extrapolation method, which is one of the most common techniques to extract the threshold voltage. This method is based on:

2

where W and L are channel width and channel length, respectively. Cox is the gate oxide capacitance per unit area and Vth is the threshold voltage. µ_eff is the field effect mobility,

which will be discussed in the next sub-section.

The drain current is measured as a function of gate voltage at a low drain voltage = 0.1 V.

The low drain voltage is to ensure that the operation is under the linear region. The IDS-VGS

curve differs from a straight line at VGS < Vth due to sub-threshold current and at VGS >Vth due to series resistance and mobility degradation. There is a linear region at the neighboring of

VGSat which gm is maximum. The IDS-VGS curve can be fitted a straight line to extrapolate to

ID=0 by means of finding the point of gm, max. Therefore, the Vth is extracted from the VG-axis intersection. The resultant threshold voltage is given by:

2

DS

th GSi

V =V −V (3.2)

where VGSi is the value of the intersection point.

3.1.2 Mobility extraction

According to Eq. (3.1), the effective mobility can be expressed as:

( )

^{2/ 2} The effective mobility is usually plotted against an effective normal field Ε , which is _eff

defined as:

3.2 Characteristics of HfSi

x

/Hf

0.7

La

0.3

ON capacitors

Fig. 3-1 shows the C-V characteristic of the HfSix/Hf0.7La0.3ON/Si MIS capacitor. The characteristic of the TaN/Hf0.7La0.3ON/Si capacitor is also shown in Fig. 3-2 for comparison.

The FUSI HfSix gate was formed by depositing 20 nm Hf on thin 5 nm amorphous-Si followed by 1000^oC RTA while the TaN gate was formed by depositing 150 nm TaN directly

density, close to that using the TaN gate. This result proves that the FUSI HfSix has no poly-Si depletion. In addition, the VFB of the HfSix gate is more negative than for the TaN gate by 0.05 V, which is needed for low Vthoperation. An EOT of 1.2 nm was obtained by the quantum-mechanical (QM) C-V simulation. A low φ_{m eff,} of 4.33 eV was obtained from a

VFB-EOT plot for the HfSix/Hf0.7La0.3ON/Si capacitor, as shown in Fig. 3-3. This low effective work function makes them suitable for NMOS applications.

In Fig. 3-4, the leakage current of HfSix is 9.2×10^-4 A/cm² at 1 V below the VFB. It is about 5 orders of magnitude lower than that of SiO2 at a 1.2 nm EOT. This low leakage current is mainly due to the higher dielectric constant of Hf0.7La0.3ON. Hf0.7La0.3ON with higher dielectric constant can have larger physical thickness at the same EOT as SiO2. Therefore, the direct tunneling current can be highly decreased. The low leakage current also proves the good thermal stability of the HfSix/Hf0.7La0.3ON gate structure after a 1000^oC RTA.

In contrast, the leakage current of TaN is 2.8 × 10^-3/cm² at 1 V below the VFB, as shown in Fig.

3-5. The higher leakage current at low voltages using TaN gate than that of HfSix may be due to the sputter-induced damage to the Hf0.7La0.3ON gate dielectric.

3.3 Characteristics of HfSi

x

/Hf

0.7

La

0.3

ON n-MOSFETs

Figures 3-6 and 3-7 show the ID-VD and ID-VG transistor of the 1.2 nm EOT HfSix/Hf0.7La0.3ON n-MOSFETs. Good transistor characteristics can be seen from Fig. 3-6

and 3-7. A small Vth of only 0.18 V was extracted from the linear ID-VG plot, as shown in Fig.

3-8. This is due to the low φ_{m eff,} of 4.33 eV found from the C-V measurements.

The mobility as a function of effective electric field for the HfSix/Hf0.7La0.3ON n-MOSFETs is shown in Fig. 3-8. High peak electron mobility of 215 cm²/V-s is obtained at a small EOT of 1.2 nm.

Altogether, the small EOT of 1.2 nm, low Vth of 0.18 V, good peak mobility of 215 cm²/V-s and simple high-temperature FUSI processing makes HfSix/Hf0.7La0.3ON device a potential candidate for n-MOSFET application.

Table 3-1 summarizes and compares the important transistor characteristics for various FUSI gate/high-κ n-MOSFETs.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0

0.5 1.0 1.5 2.0 2.5

Capacitance Density (µF/cm2 )

Gate Voltage (V)

HfSi 1000^oC RTA

Fig. 3-1 C-V characteristics of the HfSix/Hf0.7La0.3ON/Si capacitor.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0

0.5 1.0 1.5 2.0 2.5

Capacitance Density (µF/cm2 )

Gate Voltage (V) TaN 1000o

C RTA

Fig. 3-2 C-V characteristics of the TaN/Hf0.7La0.3ON/Si capacitor.

Fig. 3-3 VFB-EOT plot of the HfSix/Hf0.7La0.3ON/Si capacitor. The extracted effective work function of HfSix from the plot is 4.33 eV.

0 1 2 3 4

-1.0 -0.5

φ

_m,eff

= 4.33 eV

V FB (V)

EOT (nm)

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 1E-10

1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

Current Density (A/cm2 )

Gate Voltage (V)

HfSi_x 1000^oC RTA

Fig. 3-4 J-V characteristic of the HfSix/Hf0.7La0.3ON/Si capacitor.

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 1E-10

1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

Current Density (A/cm)

Gate Voltage (V)

TaN RTA 1000^oC

Fig. 3-5 J-V characteristic of the TaN/Hf0.7La0.3ON/Si MIS capacitor.

0.0 0.5 1.0 1.5 2.0 2.5

-1 0 1 2 10

^-10

10

^-8

10

^-6

10

^-4

10

^-2

10

⁰

HfSi

x/Hf

0.7La

0.3ON

Drain Current (A)

Gate Voltage (V)

Vd=0.1 V

Fig. 3-7 I_D-V_G characteristic of the HfSix/Hf0.7La0.3ON n-MOSFET.

-0.5 0.0 0.5 1.0 1.5 2.0 0.0000

0.0002 0.0004 0.0006 0.0008 0.0010 0.0012 0.0014

Gate voltage (V)

Drain Current (A) gmV

D= 0.1V V_th=0.18V

Fig. 3-8 ID-VG characteristic of HfSix/Hf0.7La0.3ON n-MOSFETs in linear scale. The extracted Vth is 0.18 V.

0.0 0.2 0.4 0.6 0.8 1.0 0

200 400

600 _Universal

HfSi_x/Hf_0.7La_0.3ON

Electron Mobility(cm2 /V-sec)

Effective field (MV/cm) Fig. 3-9 The mobility of the HfSix/Hf0.7La0.3ON n-MOSFET.

Table 3-1 Comparison of device parameters for several FUSI gate/high-κ n-MOSFETs.

Ref. Metal gate High-κ Vth (V) EOT (nm) RTA temp.

[35] FUSI NiSi La2O3 0.12 1.5 400^oC, 30 s

[36] FUSI YbxSi HfAlON 0.1 1.7 Low temp.

[37] FUSI NiSi2 HfSiON 0.47 1.7 450-650 ^oC, 1 min

[38] FUSI NiSi HfSiON 0.5 1.43 Low temp.

[39] TaN HfLaON 0.18 1.6 1000^oC

This work FUSI HfSix HfLaON 0.18 1.2 1000^oC, 5 s

Chapter 4

Conclusion

In this thesis, HfSix and Hf0.7La0.3ON have been studied for n-MOSFET applications.

This structure has been demonstrated with good device characteristics. We have fabricated the FUSI HfSix gate on Hf0.7La0.3ON with 1.2 nm EOT. After 5 sec, 1000^oC RTA, the device displayed a low threshold voltage of 0.18 V, low effective work function of 4.33 eV, low leakage current of 9.2×10^-4 A/cm² at 1 V and high peak electron mobility of 215 cm²/V-s.

Thermal stability at 1000^oC RTA ensures that the device can endure the high temperature at the gate-first process. The gate-first and self-aligned process of HfSix/HfLaON n-MOSFETs make this device compatible with current VLSI lines.

It has been shown that FUSI HfSix, like FUSI NiSix has a wide range of work-function tuning [23]. The incorporation of n-type dopants to the poly-Si pre-gate has the potential to shift the effect work function to a lower value, which is suitable for NMOS operation. On the other hand, the incorporation of p-type dopants into the poly-Si or phase control technique might be used for PMOS application. The band-edge FUSI HfSix CMOS still needs to be further developed.

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Vita

姓名：陳冠霖 性別：男

出生年月日：民國 73 年 5 月 12 日 籍貫：台灣省高雄縣

住址：高雄縣大寮鄉永芳村永芳路六鄰 48 之 38 號 學歷：國立清華大學工程與系統科學系

(民國 91 年 9 月~民國 95 年 6 月) 國立交通大學電子研究所固態電子組 (民國 95 年 9 月~民國 97 年 6 月)

論文題目：

使用完全矽化閘極-高介電常數介電質之低臨界電壓金氧半電晶體

A Low Threshold n-MOSFET Using Fully Silicided Gate and High-κ Dielectric

在文檔中 使用完全矽化閘極-高介電常數介電質之低臨界電壓金氧半電晶體 (頁 23-0)