Chapter 1 Introduction
1.2 Thesis organization
This thesis contains mainly two circuits; one is low noise amplifier and the other is wide IF bandwidth mixer, which will be discussed in chapter2 and chapter3 respectively. In each chapter the circuit will be introduced and then analyzed. For clearly analyzing, dividing the circuit into smaller block and analyzing blocks step by step is adopted. In the following of each chapter, simulated and measured results will be presented.
In chapter2 is the low noise amplifier designed by CMOS TSMC 0.18μm mixed signal/RF process. With the transformer feedback in the input, the input impedance can be achieve -12dB for 10~18GHz. Due to the feedback loop of transformer and transistor’s parasitic capacitor, no additional elements needed for input matching.
Thus in this schematic the noise of the input port is only from the gate noise of the input transistor. The simulated results shows the LNA has 17dB gain (S21) and 3.5dB NF for 10~18GHz with 37.6mW power consumption.
In chapter3 is the wide IF bandwidth down-converting mixer. The mixer is designed within two on-chip baluns, and thus Marchand Balun will be first introduced.
Then the proposed wideband mixer will be shown and analyzed. The mixer has 7dB conversion gain and 9GHz IF bandwidth.
In Chapter4 are the short conclusions of the two circuits (LNA, mixer). The drawbacks of the circuits will be pointed out and some unexplained phenomenon will be shown. Those unexplained problems are the aim of future work.
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Chapter 2 Transformer Feedback CMOS Low Noise Amplifier
2.1 Introduction
Wide-band communication system (like UWB for 3.1 to 10GHz; 57 to 64GHz millimeter wave system) have received much attention due to high data rate and high speed communication. In such a wideband system, LNA is in the first stage after antenna in the front-end receiver block. To interface with the antenna and the preselect filter, LNA requires input match to 50Ω over the bandwidth. Meanwhile LNA must provide high gain and the most important, low noise.
Several typologies have been proposed for wideband input matching. (a) distributed amplifier[1]:distributed amplifier (DA) can achieve much wider input matching by several stages of amplifier. However, DA has gain problem due to long transmission line loss and consumes more power and chip area. It is unsuitable for modern wideband system. (b) negative feedback amplifier[2]: negative feedback amplifier can achieve wideband matching due to parasitic capacitance. This configuration doesn’t provide high gain and may has stable problem. (c) common gate configuration:
common gate configuration[3] has good linearity and wideband input matching. Due to the simplicity of common gate input-matching mechanism, it has low noise but smaller gain than common source amplifier. (d) filter configuration[4]: With inductors and capacitances in the input of degenerated common source amplifier, it forms a Chebyshev filter structure in the input. The input matching bandwidth is dependent on the order of Chebyshev filter. Therefore it can achieve wider input matching but the
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noise figure is degraded by the imperfect effect of inductors and capacitances.
Fig. 2-1. Proposed LNA schematic
In this chapter, a LNA designed in CMOS TSMC 0.18μm mixed signal/RF process is proposed. The LNA has no additional input tuning circuits for lower noise. Input matching is achieved due to parasitic capacitance (Cgd, Cgs) and transformer feedback. The design consideration is analyzed, followed by the post-simulated results and the conclusion.
2.2 Circuit Analysis
The architecture of proposed LNA is shown in Fig. 2-1. By cascading two stages (stage2 and stage3) to amplify signal, the LNA can achieve enough gain above 10 GHz. The output buffer is implemented for 50Ω output-matching. For input matching analysis, ZA in Fig. 2-2 can be approximated as a resistor RA at high frequency.
Looking into common gate transistor M2, the impedance ZL is [3]
( )
where Ro is the output resistor of M2
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( ) 1
2
X s ω C gs
ω
= − ( ) ( ) 1 // // 1
Zo ω jXo ω j Cgd2 RA j Lω d
= = ω
The impedance ZL is close to 50Ω over the bandwidth due to the common gate typology of transistor M2. it can be assumed that ZL is 50Ω for simplified calculation.
A transformer model [5] is shown in Fig. 3 where L1=0.5nH, L2=1nH, k=0.6, n=2 in proposed LNA.
Fig. 2-2. Proposed LNA input stage
Fig. 2-3. (a) Transformer (b) Equivalent circuit of transformer
By replacing the transformer equivalent circuit into Fig. 2-2, the input matching small signal circuit is shown in Fig. 2-4.
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Fig. 2-4. Input matching small signal circuit.
Zd is an inductor and simplified input matching mechanism is shown in Fig. 2-5.
Fig. 2-5. Simplified input matching mechanism.
To calculated input impedance for high frequency, Cgs1、Cgd1 must be taken into account[6] and the S11 smith chart is shown in Fig. 2-6.
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Fig. 2-6. S11 of proposed LNA.
Due to the transformer feedback and the parasitic capacitance, the real part of S11 in Fig. 2-6 is close to 50 Ω over 10~18GHz. Meanwhile the circuit has low NF because only the parasitic capacitance in the gate of M1.
2.3 Simulated results
This section presented the post-simulated results of the proposed LNA operating over 10-18GHz under typical-typical corner with a supply voltage of 1.8V. This work is designed and simulated using TSMC 0.18µm mixed signal/RF CMOS 1P6M technology. The transformer and inductors in the circuit is verified by EM-simulation (ADS momentum).
Fig. 2-7. Post-simulated S11 versus frequency.
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Fig. 2-8. Post-simulated S21 versus frequency.
Fig. 2-9. Post-simulated S22 versus frequency.
Fig. 2-10. Simulated NF versus frequency.
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Fig. 2-11. P1dB for 15GHz.
The S-parameter is shown in Fig. 2-7, Fig. 2-8, and Fig. 2-9 where S11 in Fig.
2-7 < -15dB over 11~17GHz. The gain (S21) in Fig. 2-8 is 17dB from 10 to 18GHz with variation less than 1dB. S22 in Fig. 2-9 is less than -10dB over 10~18GHz. The transistor’s size and the transformer must be fine tuned to provide a good input impedance matching and low noise. The simulated noise figure is shown in Fig. 2-10.
In Fig. 2-10, it has been shown that the minimum NF is 2.5dB at 10GHz, and increase to 3.4dB at 18GHz. The P1dB in Fig. 2-11 is -22.6dBm for 15GHz. The total power consumption is 37.6mW.
The layout of the LNA is shown in Fig. 2-12. The chip area is 1mm by 0.8mm.
Fig. 2-12. Proposed LNA layout. 1mm X 0.8mm
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2.4 Conclusion
In this paper, a novel wide bandwidth LNA is proposed based on CMOS TSMC 0.18μm mixed signal/RF process. Only by parasitic capacitance and transformer feedback, it can achieve input matching over 10~18GHz. And due to the simplicity of the wideband input matching mechanism, very low noise can be achieved from 10~18GHz.
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2.5 Reference
[1] Sullivan, P.J.; Xavier, B.A.; Ku, W.H,“An integrated CMOS distributed amplifier utilizing packaging inductance”, Microwave Theory and Techniques, IEEE Transactionson Volume 45, Issue 10, Part 2, Oct. 1997 Page(s):1969 - 1976 [2] Shih-Chih Chen; Ruey-Lue Wang; Ming-Lung Kung; Hsiang-Chen Kuo, “An
Integrated CMOS Low Noise Amplifier for 3-5 GHz UWB Applications”
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on 19-21 Dec.
2005 Page(s):225 - 228
[3] Yang Lu; Kiat Seng Yeo; Cabuk, A.; Jianguo Ma; Manh Anh Do; Zhenghao Lu,”
A novel CMOS low-noise amplifier design for 3.1-to 10.6-GHz ultra-wide-band wireless receivers” Circuits and Systems I: Regular Papers, IEEE Transactions on [see also Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on]Volume 53, Issue 8, Aug. 2006 Page(s):1683 - 1692
[4] Andrea Bevilacqua, and Ali M. Niknejad, “An Ultrawideband CMOS Low-Noise Amplifier for 3.1–10.6-GHz Wireless Receivers,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
[5] Long, J.R,” Monolithic transformers for silicon RF IC design”, Solid-State Circuits, IEEE Journal of Volume 35, Issue 9, Sept. 2000 Page(s):1368 - 1382 [6] Hu, R.,” Wide-band matched LNA design using transistor's intrinsic gate-drain
capacitor”, Microwave Theory and Techniques, IEEE Transactions on Volume 54, Issue 3, March 2006 Page(s):1277 - 1286
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Chapter 3
Down-Converting Mixer for Millimeter Wave Applications
3.1 Introduction
To transform the radio-frequency (RF) signal to a much lower intermediate frequency (IF), down-converter mixer is to be used. For example, in the IEEE802.11 a/b/g receiver, the 2.45GHz incoming RF signal will be down-converted by mixers to the 10MHz IF signal where the local oscillator is set to 2.44GHz. The basic operation of the mixer can be shown in Fig. 3-1. It translates frequency by multiplication of two signals (a RF signal and LO signal).
Fig. 3-1. The basic operation of the mixer.
Although there are many topologies of mixers (single balanced、double balanced、
triple balanced… ), the double balanced circuit configuration have been readily appearing in microwave and millimeter wave applications for it’s good isolations.
However, not all the technology developed in double balanced circuit configuration
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for further improving the mixer’s performance, at low frequency or even a few GHz, are applicable at tens of GHz. For example as indicated in Fig. 3-2, the schematic is a typical double balanced mixer (excluding the dotted line current sources). In order to enhance the conversion gain, it is perhaps to use large Rc. However as Rc increasing, the voltage drop between Rc will also increasing, driving out of the original bias condition. Increasing the power supply voltage Vbias is a solution but it will consume more power. The alternated solution is externally injecting current by using the two current sources as indicated in Fig. 3-2. However this solution can’t be applied at tens of GHz, since the current are usually made of p-type transistors, the output impedance of the current source Zc tend to decrease at high frequency and thus deteriorated the mixer’s performance at high frequency.
The challenge in designing a well-performing microwave or millimeter-wave mixer is even obvious when considering another factor: IF bandwidth. So far, most of the mixers with normal-biased transistors, as contrast to resistive transistors with no drain to source bias, have their wide-band proclamation illustrated by shifting the LO across the intended RF bandwidth, while keeping the IF band-width comparatively small, i.e., wide RF-bandwidth but narrow IF-bandwidth. With an IF bandwidth of hundreds of MHz, a large output signal voltage can be easily achieved by replacing each Rc in Fig.
3-2 with an appropriate p-type transistor as a active load, for which is capable of providing a large impedance at low frequency. However, when the IF bandwidth is extended to several GHz, the rapidly decreasing impedance of this active p-type load becomes a liability, as it leads to a large variation of the conversion gain over the intended bandwidth: extremely high impedance at the low-end of the IF frequency range while at high-end it is mediocre or no better than that of mixers using Rc.
Likewise, the use of extra current source and large Rc for 10.20dB conversion gain will lose its appeals as IF bandwidth increases, because the IF voltage is now mainly
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determined by the much lower input impedance of the following stage rather than Rc itself.
Fig. 3-2. The schematic is a typical double balanced mixer with the dotted line current source for current injecting method.
Fig. 3-3 is the schematic of a millimeter-wave receiver which will be used in the form of array for the determination of the anisotropy of the cosmic microwave background radiation, and it demands the employment of several wide IF bandwidth mixers. As indicated by the number inside the crossed circle, the first mixer will down-convert the amplified 78.3 - 113.1GHz signal to DC - 34.8GHz, or more precisely, 0.2 - 34.8GHz. Four bands are then separated using amplifiers, filters and another three mixers, with each has the same IF bandwidth of 8.7GHz; the LO frequencies are fixed at 17.6GHz, 17.6GHz and 26.3GHz for equal bandwidth partition. Though the commercial Marki M1R0920, Hittite HMC292 and HMC329 can be used for mixers 2, 3 and 4, respectively, their conversion losses require the
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adjacent amplifiers inside and outside module to be very high-gain. Besides, these passive mixers' poor impedance matching at RF, LO and IF ports inevitably contribute to the rippled responses versus frequency in their corresponding bands. The existing system's shortcomings therefore prompt us to design the wide IF-bandwidth down-converting mixers with matched ports, low noise temperature, positive over-all conversion gain and, most important of all, a clear IF output spectrum. In this paper, we intend to focus on the second mixer, which has its input frequency range being 8.7 - 17.4GHz and LO set to 17.4GHz, as shown in Fig. 3-4. The reason why not using a 8.7GHz LO to down-convert the RF is because this LO is bordering the IF band, thus any residual LO at IF output is hard to remove; by contrast, a 17.4GHz LO will not have this problem.
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Fig. 3-3. Schematic of the wide-band receiver. With fLO= 8.7GHz, the incoming 78.3 - 113.1GHz signal will first be amplified and then down converted into DC to 34.8GHz, which will be further split into four separate bands of equal bandwidth. The front-end amplifier and mixer are located inside the cryostat from sensitivity consideration, while the rest are at room temperature.
Fig. 3-4. Distribution of the four IF bands with fLO = 8.7GHz. The DC - 4fLO
frequency range will be divided into 4 bands. The first band can be extracted using a low-pass filter while the second, third and forth bands have to be down-converted first using mixers with their LO frequency set to 2fLO, 2fLO and 3fLO, respectively.
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3.2 Wide IF Bandwidth Down-Converting Mixer Design
A. Input RF circuit design
In designing the RF input circuit, the transistors’ size must be chosen properly.
Since the RF incoming signal at frequency 8.7~17.4GHz, the transistor must provide enough gain (S21) and acceptable power consumption at such high frequency. Fig.
3-5 shows the simulated transistor’s S-parameter with TSMC 0.18um RF-CMOS processing ADS design kit. The curves in Fig. 3-5 are with transistor’s size W=160um VDS=1.16V, VGS=0.7V, and Id=8.67mA; the S21 is about 7dB in RF bandwidth, and the power consuming 10mA.
Fig. 3-5. Simulated S-parameters of the transistor. The solid lines are from the large transistor biased at Vds = 1.16Volt, Vg = 0.7Volt, and Id = 8.67mA;
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In order to have better LO-IF isolation, the mixer will be designed in double balanced Gilbert cell topology. This topology requires two differential signals (LO、
RF). While designing RF circuit converting single-ended RF signal to differential-mode is a challenge especially at high RF frequency. Granted, there are many circuit configurations available for converting the single-ended RF signal to differential-mode, and one is the differential pair with one input port grounded, as shown in Fig. 3-6. However this configuration will cause two problems as follows.
One is that if RF signal is presented at one transistor’s and the other transistor’s gate is grounded, the RF signal will be at RFdiff in two paths; one is a common-source path, the other is common-drain and common-gate path. Due to the parasitic capacitors, the two paths are physically asymmetric and the balanced performance of the RF differential-mode signal is worse than passive Marchand balun. The other problem is RF-to-IF isolation. If a 3GHz out of band signal is presented, this configuration will provide about 7 dB gain and pump the signal to mixer. Amplifying out of band signals will degrade RF-to-IF isolation and burden the filter before the mixer. On the other hand Marchand balun has signal degradation of -20dB at low frequency which is capable of rejecting lower out of band signal.
Lastly, conversion gain degradation notwithstanding, differential-mode signal can indeed be extracted from the drain and source nodes of the transistor, as indicated by arrow 2 where the capacitor Cp is for high frequency phase compensation. With good common-mode suppression for the fundamental frequencies, if two signals 9GHz and 11GHz are presented in transistor’s gate, the two signals on Vα will mostly be differential-mode; however, the 2GHz and 20GHz signals (due to the nonlinearity of the first transistor) at Vα are mostly common-mode. When the nonlinearity of the differential-pair transistors comes to play, differential-mode 7GHz (9GHz minus 2GHz), 9GHz (20GHz minus 11GHz), 13GHz (9GHz plus 2GHz), and 31GHz
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(20GHz plus 11GHz) signals all appear at RFdiff. Since the IF bandwidth is 8.7GHz, the unintended signals thus disturb the output spectrum.
Fig. 3-6. Different circuit configurations used to convert the single-ended RF signal into the differential-mode RF signal at RFdiff. Perfect differential-mode LO and idea IF balun are assumed in analyzing these two different conversion approaches.
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Fig. 3-7. Input RF circuit schematic. The transistor has five 32um-long gate fingers and is biased at Vd = 1.16Volt, Vg = 0.7Volt, and Id = 8.67mA. The Marchand balun is used to provide a differential-mode RFdiff.
To minimize all the lower out of band signals and unwanted differential-mode signals and their harmonics at RFdiff, a distributed Marchand balun is adopted in designing this mixer's RF circuit, as shown in Fig. 3-7. Granted, there are other types of passive baluns that can be used; however, their stated merits are mainly for applications of a few GHz [6], [7]. Distributed Marchand balun made of coupled lines, on the other hand, has been proved applicable at much higher frequency [8].
Neglecting its loss, an ideal Marchand balun have its S-parameters expressed as
[ ]
where the frequency-dependent coupling factor is set to be -4.8dB. Therefore, port 1,
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as indicated by the number in the figure, is matched while the output signals on ports 2 and 3 are 180 degrees out of phase in this ideal case [9], [10]. As the balun will indeed be fabricated on the lossy silicon substrate, this RF front-end loss will greatly affecting this mixer's noise performance. Even worse, with capacitive loading the balun's input impedance can be anything but 50Ω. A one-stage transistor circuit is then added in front of this balun for wide-band input matching [5].
As this input RF circuit operates at 8.7 to 17.4GHz, which is far beyond the reach of the active load using p-type transistors, a series RdLd is chosen for the transistor's drain bias branch, whereas the gate bias is through a large resistor. Of course, with relaxed constrain on chip size and much elaboration, transformer feedback can indeed be applied for achieving even better Sin while retaining a low noise temperature [11].
As for the bi-symmetric class-AB input stage [12], [13], the resistive version tends to be noisy while the inductive version takes too much space. Besides, the nature of the RF signal in our system means it is far from high power
Fig. 3-8. Spiral inductor under test. (a) This 3.5-turn spiral inductor has its line width set to 6um, the inner radius is 31um, and the line separation is 2um. (b) On the Smith chart, the solid lines are the S11 and S21 from 0.1 to 20GHz provided by the vendor; the dashed lines are the simulated results. Capacitance of both the 50*50um2
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input and output pads has been properly de-embedded.
Prior to the design of the Marchand balun, accuracy of the electromagnetic simulation needs to be confirmed. Fig. 3-8 shows the S11 and S21 of a 3.5-turn spiral inductor. The solid curves are provided by the vendor; the dashed curves are the simulated results where 10Ω-cm resistance is chosen for the lossy silicon substrate, the top-layer metal is 6um-wide, and the input and output pads capacitance has been properly de-embedded. Fig. 3-9 shows the layout and schematic of the intended spiral broadside-coupled Marchand balun where input port 1 is connected to the center of one spiral, the output port 2 and port 3 are each extracted from the edge of the spiral.
Two tapered ground are needed to provide the short-circuited nodes on the center of
Two tapered ground are needed to provide the short-circuited nodes on the center of