• 沒有找到結果。

4.1 Nets decomposition

topology, separating a net into two-pin nets before global routing stage will not benefit by this character. Below I will explain how we divide a steiner tree topology, a result of global router, and separate it into two-pin pairs.

The global router returns a steiner tree that comprises many dot-to-dot segments, a dot may be a steiner point or a pin. First we categorize all dot-to-dot segments into three types:pin to pin as type0, pin to steiner point as type1 and steiner point to steiner point as type2. All type0 segments already connect two pins so we only need to handle type1 and type2 segments. We start from a type2 segment (Figure 20(b)) and extend from one end until attached a type1 segment, e.g. find a pin (Figure 20(c)) and then we extend from the other end (Figure 20(d)), and then we get a pin-to-pin pair and path. We call this kind of two-pin nets a trunk. After we get a trunk we extend from its’ steiner point to get other two-pin nets called a branch. A branch record the path extending from a steiner point to a pin, and we will take a pin of the trunk that is nearest to the steiner point as the other pin of the pin pair of the branch (Figure 21).

This is for the pseudo pin-to-path routing in NEMO, which mentioned at section 2.2.

If there is no type2 segment, we can form a trunk from a type1 segment (Figure 22).

And if a branch has any steiner point, we will get sub-branches from it.

Because we now have a global router that produces steiner tree routing

(a) (b) (c) (d) Figure 20 Separate a steiner tree into two-pin nets (a) A steiner tree with

one end (d) extend from the other end and get a trunk.

many dot-to-dot segments (b) start from a type2 segment (c) extend from

(a) (b) (c)

Figure 21 Separate a steiner tree (continued) (a) find a branch from a steiner point of the trunk (b) find an other branch (c) branches record path extending from steiner point and a addition pin of trunk.

(a) (b) (c)

Figure 22 Separate a steiner tree (continued) (a) find an other trunk from a type1 segment (b) get a trunk (c) find a branch and stop the separating process.

4.2 Tool design flow

The design flow is showed as Figure 23. We maintain a routing database that initially record the input information, and then give global router necessary information to produce topology. After separate steiner tree topology into two-pin nets topology, NEMO will query data from routing databas and then start detailed routing.

Final ow

on th d a routing result. As the

figure you can see that there are some buttons at left-top, they are open file, routing e

ly the routing result that already fixed will save in the routing database and sh e screen. Figure 24 shows the screenshot of the GUI an

, fit, zoom-in, zoom-out, and redraw. And at right, you can see the control panel from top to down:cursor coordinate, metal and via layer checker buttons (choose to show) and routing result information.

Figure 23 Tool design flow

Figure 24 Screenshot of the GUI

Chapter 5

Experiment Results

To compare with old version NEMO, we perform this tool on a 1.2GHz Sun Blade-2000 workstation with 2GB memory. We route ISCAS89 benchmarks showed as Table 1; “#Lay” shows the number of available routing layer; “#2-pin nets” shows the number of two-pin connections after net decomposition. Table 2 shows the result of old version NEMO with an old version global router, and result of this work with a new global router. In this table, “# of Vias” shows the number of vias, “WL” shows the total wire length in micrometer, “Non-prefer” shows the non-prefer length in micrometer and the percentage of WL. Compare with old version, we can see that non-prefer length are reduced at all six cases and run time are reduced at large test cases. Due to precisely estimating path cost, non-prefer length should be reduced. And accurately constructing minimum cost paths is helpful to reduce the run time when

uting a large case.

Table 1. Statistics of ISCAS89 series benchmark circuits

Circiut Size(μm) Pins # Lay # 2-pin nets

Table 2. Comparison of the rout eries benchmarks

NEMO (old ve NEMO (this version)

ing result of ISCAS89 s

Table 3. Statistics of Ibm-series Benchmark circuits

Circiut Size(μm) Pins # Lay # 2-pin nets

Besides we route the ISPD98 benchmarks [15], which originally only provide partition information, but people set some detail information for placement. We use the result of a placer ragon [16 ich generate

route these benchma workstatio th AMD Opte n 2.0GHz processor and 16GB me . We modify some routing information for NEMO. First the pins are a line not a point, NEMO can not handle ituation yet, s ed t ns to a point. Second, all layers have different rule but for convenience and simplification we ade all layers with the same rule. Table 3 lists the statistics for eight circuits of

arks. Our result is showed as Table 4, and we compare it with the sult of a commercial tool called Nanoroute. Only the first case we have shorter run time, and it shows that our tool need much more time to handle dense cases. We may called D ], wh s LEF/DEF output files, and

improve that by a better rip-up and reroute method. Wire length is similar, but we

roduce 0% s m han e. W k i y be sed d

wire refinement. Our wire refinement just handles a few cases for DRC, and there still exist many redundant wires and vias in the final result. We

, esu ld les e th onl tle via an

result of Nanoroute.

. C ris the seri u res

Our Tool Commercial Tool

p about 1 via ore t Nanorout e thin t ma cau by the ba

Chapter 6 Conclusions

We improve and enhance NEMO’s structure in the aspect of gridline system, path searching and construction. The gridline system is clear in present

plementation. And path searching is estimated pre uction is

tel to rec addi iles orma utpu atio E

will be m by n rule checker and s generate a DRC free result.

we bine ges iv lobal ter wi EMO a

position process. Finally ck rogra s a routing tool w raphic

nter hich p es ba pl erati ch as z

Chapter 7 Bibliography

[1] J. Cong,

[4] R. E. Lunow, “A Channelless, Multilayer Router,” in 25th ACM/IEEE Design Automation Conference, pp. 667-671, 1998.

[5] C.-C. Tsai, S. Chen, and W. Feng, “An H-V Alternation Router,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol.

11(8), pp. 976-991, August, 1992.

[6] J. Dion and L. M. Monier, “Contour: A Tile-based Gridless Router,” Western Research Laboratory Research Report 95/3, Palo Alto, California.

] L.-C. Liu, H.-P. Tseng, and C. Sechen,”Chip-level area routing,” in Proc. Int.

Symp. Physical Design, Apr. 1998, pp. 197-204.

[8] Z. Xing and R. Kaog, “Shortest Path Search Using Tiles and Piecewise Linear Cost Propagation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No.2, pp. 145-158, Feb. 2002.

J. Fang, and K. Khoo, “DUNE: A Multi-Layer Gridless Routing System with Wire Planning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 5 pp. 633-646, May, 2001.

[2] M. Sato, J. Sakanaka, and T. Ohtsuki, “A fast line-search method based on a tile plane,” in IEEE Int. Symp. Circuits and Systems, May 1987, pp. 588-591.

[3] A. Margarino, A. Romano, A. De Gloria, F. Curatelli, and P. Antognetti, “A tile-expansion router,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-6, pp. 507-517, July 1987.

[7

[9] T. Ohtsuki, “Gridless ro uting algorithms based on

computational geometry,” in Pr , May 1985, pp.

802-809

0] S. Q. Zheng, J. S. Lim, and S. Iyengar, “Finding obstacle-avoiding shortest paths

near shortest paths and

ded Design of Integrated Circuits and

Multi-Layer Planes and Pseudo-Tile Propagation,”

uters ─ New wire ro

oc. Int. Conf. Circuits and System

[1

using implicit connection graphs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, pp. 103-110, Jan. 1996.

[11] Y. Wu, P. Widmayer, M. Schlag, and C. Wong, “Rectili

minimum spanning trees in the presence of rectilinear obstacles,” IEEE Trans.

Comput., Vol. C-36, pp. 321-331, Mar. 1987.

[12] J. Cong, J. Fang, and K. Khoo, “An implicit connection graph maze routing algorithm for ECO routing,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1999, pp. 163-167.

[13] J. Ousterhout, “Corner stitching: A data-structuring technique for VLSI layout tools,” IEEE Transactions on Computer-Ai

Systems, Vol. CAD-3, pp.87-100, Jan. 1984.

[14] Y.-L. Li, H.-Y. Chen, and C.-T. Lin, “NEMO: A New Implicit Connection Graph-Based Gridless Router with

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No.4, pp. 705-718, Apr. 2007.

[15] http://vlsicad.ucsd.edu/UCLAWeb/cheese/ispd98.html [16] http://er.cs.ucla.edu/Dragon/

相關文件