* =
Noise Distribution
Total Distribution
V
THFigure 3.8: Amplitude distribution from noise and ISI.
These ISI terms impact on the amplitude of received data at sampling time, and repre-sented by two delta functions whose values are ISI0 and ISI1, respectively with prob-ability p and (1− p). p is the probability of a−1 = 0 and (1− p) is the probability of a−1 = 1. In order to simplify the calculation, let p = (1− p) = 0.5.
The total amplitude distribution including the effects from noise and ISI is shown in Fig. 3.8. It is obtained by the convolution of noise and ISI distribution. The valuse of ISI and po(Ts) in this figure are acquired above, and then calculate the parameter of noise distribution.
The frequency response of a first-order LTI system is H(f ) = 1
1 + τ s = 1
1 + j(2πτ f ). (3.12)
Moreover, the relation between the power spectral densities of input and output in the frequency domain can be expressed as
Sout(f ) =|H(f)|2Sin(f ) = 1
1 + (2πτ f )2Sin(f ). (3.13) If the additive white noise of the input in receiver has double-sided power spectral density N0
2 , the total noise power can be calculated from Eq.(3.13) and written as
Ptotal= σ2· Tb =
∞
−∞
N0 2
1 + (2πτ f )2df = N0
4τ (3.14)
where σ is the noise variance.
Section 3.2 Bit Error Rate Analysis 19
Figure 3.9: The BER with various sampling time.
Total BER shown in Fig. 3.8 is
BER = 1
From this equation, it can be comprehended that BER is related to sampling point (Ts), bandwidth of the system (τ ) and noise power spectral density (N0).
Use MATLAB to simulate the BER with various parameters. Fig. 3.9 shows the relation of BER and sampling point in a first-order LTI system with equal N0 and bandwidth. According to Fig. 3.9, this system obtains lower BER when the sampling point (Ts) is closer to Tb. This conclusion also can be explained based on the formula of received data. From Eq. (3.8), the amplitude of received data at sampling time can be written as
p(Ts) = 1− αTsTb. (3.16)
20 Chapter 3: Clock and Data Recovery
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
−14
−13
−12
−11
−10
−9
−8
−7
−6
−5
−4
f−3dB/data rate log 10BER
Ts = T
b
N0 = 5*10−3
N0 = 6*10−3
N0 = 7*10−3
N0 = 8*10−3
Figure 3.10: The BER with various bandwidth at Ts = Tb.
The amplitude reaches maximum at Ts = Tb and the BER in Eq. (3.15) is going to be minimum if N0 and bandwidth are identical.
From Fig. 3.9, the optimal sampling point in the LTI system is at Ts= Tb. In order to find the bandwidth with lower BER, simulate the BER with various bandwidth at Ts = Tb, and the result is demonstrated in Fig. 3.10. From this figure, it depicts there is a trade-off between the noise and the ISI influence. When the bandwidth becomes boarder, the noise injects into the receiver and causes higher BER. However, if the bandwidth is excessively small, the impact of ISI is significant and limits the BER. At Ts = Tb, it exists an optimal bandwidth to acquire minimum BER and the value is 40%
of the data rate.
Although the optimal sampling point is at Ts= Tb based on above simulation results, the typical sampling point is in the middle of the received data (i.e.Ts = 0.5Tb) in traditional CDR circuits. The simulation result is in Fig. 3.11. Therefore, the bandwidth is designed to about 70% of the data rate in the receiver with traditional CDR circuits.
Section 3.2 Bit Error Rate Analysis 21
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
−8
−7
−6
−5
−4
−3
−2
−1
f−3dB/data rate log 10BER
Ts = 0.5T
b
N0 = 5*10−3
N0 = 6*10−3
N0 = 7*10−3
N0 = 8*10−3
Figure 3.11: The BER with various bandwidth at Ts = 0.5Tb.
3.2.3 Timing Jitter
Timing jitter is also one of the factors influencing the BER, and is mainly caused by two sources. One is data jitter and the other is the uncertainty of the sampling clock.
These two causes will be respectively illustrated later.
In previous sections, assume the data transitions defined as the time of the data crossing the decision threshold (VT H) occur at mTb (m ∈ integer), and the amplitude fluctuation dominates the BER. However, the actual time of data transition deviates from the expected value thanks to the non-ideal effects mentioned before, e.g. noise and ISI. This phenomenon is called data jitter and leads to timing jitter depicted in Fig. 3.12(a). The data jitter reduces the eye diagram of received data on the horizontal direction. Fig. 3.12(b) shows this appearance. When the data jitter alters larger, the sampling window where the BER can achieve the target becomes smaller. Furthermore,
22 Chapter 3: Clock and Data Recovery
V
THJitter
T
b Original Sampling WindowSampling Window Impacted by Jitter
(a) (b)
Figure 3.12: (a)The timing jitter and (b)sampling window of received data.
VT H
Figure 3.13: The BER caused by the data jitter.
if the sampling point is fixed, the BER increases due to the error detection caused by the data jitter. Fig. 3.13 shows the BER from jitter which is the area under the tail of P DFdata(t). P DFdata(t) is the probability distribution of total jitter, and σd represents the variance of the data jitter. If there are no noise and ISI, and sampling clock is ideal, the BER only influenced by data jitter is written as
BER(Ts) = 1
The errors induced by data jitter are independent of those from amplitude fluctuations that come from noise and ISI. Use MATLAB to simulate the BER caused by data jitter and demonstrate the result in Fig. 3.14. Based on this figure, if the received data is only influenced by the data jitter, the optimal sampling point is in the middle of the data.
Therefore, the traditional CDR circuits can acquire recovered data precisely.
Section 3.2 Bit Error Rate Analysis 23
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−14
−12
−10
−8
−6
−4
−2 0
Ts (UI) log10BER
σd= 0.04 (UI) σd = 0.05 (UI) σd = 0.06 (UI) σd = 0.07 (UI)
Figure 3.14: The simulation result of BER with various the data jitter.
Another source to impact on the BER is clock jitter. The probability distribution function of clock jitter, P DFclk(t), in various CDR is distinct. In the traditional CDR, the P DFclk(t) is related to not only the jitter from clock generator, but also the data jitter. Because the clock of these architectures is regenerated by some logic gates which received data control, the data jitter impacts on the clock jitter as well. σc represents the variance of the clock jitter, and the P DFclk(t) is written as
P DFclk(t) = 1
√2πσc · e−(t−Ts)
2
2σ2c . (3.19)
Because the clock is not regenerated in the blind oversampling CDR, the clock jitter does not relate to data jitter. The sampling time is not at 0.5Tb similar to that in the typical CDR, but has an offset from the middle of one bit period. Therefore, the P DFclk(t) of oversampling CDR is consisted of the jitter generated from clock generator and the sampling time offset. The probability distribution function of the sampling time
24 Chapter 3: Clock and Data Recovery
Figure 3.15: The PDF of data jitter in (a)typical CDR, and (b)oversampling CDR.
offset is
where M is the number of clocks to sample data and has been mentioned in Section 3.1.2. Finally, combine the original clock jitter from the oscillator and this sampling time offset, and the P DFclk(t) is written as
Fig. 3.15(a) and (b) separately demonstrate the probability distribution function of clock jitter in traditional CDR and blind oversampling CDR.
3.2.4 Overall BER and Comparison
From previous sections, the noise, jitter and ISI all impact on the BER independently.
Combine all the causes to discuss the BER in this section. The BER related to noise and ISI terms has been illustrated in Eq.(3.15). Now add the timing jitter into this equation and temporarily assume that the sampling clock is ideal. According to [4], the
Section 3.2 Bit Error Rate Analysis 25
BER without clock jitter at sampling time (Ts) is
BER(Ts) = 1
The simulation result of MATLAB is depicted in Fig. 3.16. Here supposes the band-width of previous circuit is 70% of data rate and vary N0 to demonstrate the relation between BER and the sampling point. It can be seen from this figure that the finally optimal sampling point is not in the middle of the received data. If the data influenced more seriously by noise and ISI, the optimal sampling point is closer to Tb in the LTI system. Otherwise, if the data impacted more critically by timing jitter, the optimal sampling point is closer to middle of the data (0.5Tb).
0 0.2 0.4 0.6 0.8 1
Figure 3.16: The relation between BER and Ts with various N0.
26 Chapter 3: Clock and Data Recovery
Additionally, when N0 is fixed and the bandwidth of previous circuit is 70% of data rate, the jitter(σj) is altered to observe the relation between BER and sampling point.
This simulation result is shown in Fig. 3.17. It can be seen that the optimal sampling point is not identical with various jitter.
0 0.2 0.4 0.6 0.8 1
10−10 10−8 10−6 10−4 10−2 100
Ts(UI)
BER
f−3dB/datarate = 0.7, N
0= 6e−3[V2/Hz]
σj = 0.05 (UI) σj = 0.07 (UI) σj = 0.09 (UI) σj = 0.11 (UI)
Figure 3.17: The relation between BER and Ts with various jitter.
Based on Fig. 3.16 and Fig. 3.17, the optimal sampling point is not at 0.5Tb, but alters dependent on various situations. Therefore, traditional CDR circuits which always sample at the middle of received data can not recover signal with lower BER. In order to improve this drawback, an eye-opening monitor CDR is proposed in this thesis and introduced in the later section.
If the sampling clock is not ideal and has jitter like that modeled in Eq.(3.21) and Eq.(3.19), the actually total BER at sampling time (Ts) is derived as
BER =
Tb
0
P DFclk(T s)· BER(Ts) dTs. (3.23)
Section 3.3 Proposed Eye-Opening Monitor CDR 27
Traditional Sampling Position
Tb 0.5Tb Tb 0.5Tb
Optimal Sampling Position
BER
0.5UI
BER
0.7UI
Figure 3.18: (a)Ideal received data, and (b)received data in reality.
3.3 Proposed Eye-Opening Monitor CDR
No matter what kind of CDR it is, the sampling time is perferably at middle of one bit period (Ts = 0.5Tb) to recover data. Nevertheless, when data is transmitted, it is impacted by channel loss and the received data is not looked like that in Fig. 3.18(a) but in Fig. 3.18(b). Hence, the optimal sampling point is not at 0.5Tb, but alters dependent on distinct received data. This conclusion is obtained from BER analysis discussed in preceding sections. From Fig. 3.16 and Fig. 3.17, the lowest BER is not at 0.5Tb. Thus, propose an architecture based on the oversampling CDR including an eye-opening monitor technique. It has not only the advantages of oversampling CDR, but also the additional capability that can select a more appropriate sampling clock when channel loss exists.
3.3.1 Eye-Opening Monitor
In communication system, the received signal quality is related to its eye diagram.
Therefore, eye-opening monitor (EOM) technique is normally used to extract informa-tion from the received signal. For instance, a ”window monitor” and a ”window counter”
are implemented to inspect optical signal quality in [5]. The ”window monitor” uses two reference levels overlapped with the eye diagram of input signal and finds the signal falling between the two reference levels. Furthermore, the ”window counter” counts the number of bits inside the window. When the number exceeds a threshold, it means that the signal quality in working fibre degrades and then the system is switched to receive
28 Chapter 3: Clock and Data Recovery
signal from a standby fibre. In [6], the eye-opening monitor can adaptively adjust the decision threshold level of the receiver and the clocks recover the input data at half a clock period in the receiver. Moreover, the eye-opening monitor is used in feedback of adaptive transversal filter equalizers in [7]. The eye diagram monitor evaluates output data of the filter and adjust its coefficients. This EOM circuit architecture maps not only the vertical (amplitude) opening of the eye diagram but also the horizontal (tem-poral) opening and is called two-dimensional(2-D) EOM. [8] has used the eye-opening monitor technique to implement CDR circuit, but it needs off-chip PC-based algorithm to find out the optimal sampling position. In addition, it consumes large power and area.
3.3.2 Proposed EOM CDR Architecture
Propose a CDR circuit including a two-dimensional eye-opening monitor to detect the input signal and select proper sampling clock to recover data with low BER. Firstly, use two reference levels, VREF,H and VREF,L, to form a window overlapping on the eye diagram of input signal, and find the part of signal which does not fall in this window.
The signal out of this window is more appropriate to be read than other parts, because it has more open eye diagram and lower bit error rate. Moreover, determine the size of window by adjusting the reference voltage.
Secondly, use multiphase clocks to sample those signals, and process the results with logic gates. After the majority voting mechanism, the most adequate sampling clock is selected in the end. The architecture of this EOM CDR is depicted in Fig. 3.19. No matter how the received data is impacted by noise, ISI and jitter, this EOM CDR can recover data at more proper position.
The reference voltage can decide the size of window. When the window gets larger, the sampling clock is closer to the position where data has the lowest BER. The relation between selected sampling clock and window size is demonstrated in Fig. 3.20.
Moreover, use MATLAB to simulate the BER analysis related to the sampling clocks and various reference voltage (i.e. distinct window size). In Fig. 3.21, it can be seen
Section 3.3 Proposed Eye-Opening Monitor CDR 29
Eye - Opening Monitor (EOM)
Multi-phase Clock Generator Phase Selector
Figure 3.19: The block diagram of the EOM CDR.
if the system asks the BER of recovered data should be lower than a specific value (assume 10−12 here), the EOM CDR can achieve this request by modifying the reference voltage. Here, assume the amplitude of input data is 0.2V peak-to-peak and the dc value is 0.6V. From this simulation result, if the reference voltage is set at 0.66V, the BER of recovered data is only gauranteed to achieve lower than 10−8. However, adjust the reference voltage to 0.68V, the recovered data with BER lower than 10−12 can be attained.
Sampling Clocks
Phase No. 3 5 6 701 2 3 4 5 6 701 2 3 4 5 6 7
Selected Phase 4 4
REF,H
Figure 3.20: The relation between window size and selected sampling phase.
30 Chapter 3: Clock and Data Recovery
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−14
−12
−10
−8
−6
−4
−2 0
BER = 10−12 VREF,H = 0.64
VREF,H = 0.66
VREF,H = 0.68
Ts(UI) log10BER
f−3dB/datarate = 0.7, N0= 3*10−3[V2/Hz],σj = 0.025 (UI)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0 0.5 1
Ts(UI) Position of Sampling Clock (V
REF,H = 0.68)
Figure 3.21: The relation between reference voltage and BER, and sampling position.
In high speed serial-link receiver, an equalizer is demanded to compensate the chan-nel attenuation. The chanchan-nel used here is FR4 trace. The compensating ability of equalizer limits the transmission length. The equalizer ordinarily boosts the gain, and the combined bandwidth of channel and equalizer should be at least 0.7 of data rate.
Only when the bandwidth is 0.7 of data rate, the optimal sampling position is at 0.5Tb which is the premise of designing typical CDR circuit. However, if use the EOM CDR, the sampling position is not fixed and varies with received data, and the bandwidth of channel and equalizer need not to achieve 0.7 data rate.
The requirement of equalizer in using conventional CDR and EOM CDR is illustrated with AC response in Fig 3.22. From this figure, the bandwidth of equalizer used with EOM CDR is only demanded to compensate to 0.5 data rate instead of 0.7 data rate in using traditional CDR. The restriction of equalizer in employing EOM CDR is rougher.
Section 3.3 Proposed Eye-Opening Monitor CDR 31
(linear scale) (linear scale)
Using Traditional CDR Using Proposed EOM CDR
Figure 3.22: Responses of FR4 and equalizer using various CDR circuits.
3.3.3 Extended Application
Since the EOM CDR is based on the blind oversampling architecture, it has the advantage such as quick settling time. This is because blind oversampling CDR does not require feedback loop to decide the position of sampling clock like that in traditional CDR. Because of the fast settling time, EOM CDR can also be used in burst-mode CDR which is employed in optical communication system such as EPON. In addition, it eliminates the obstacles of traditional burst-mode CDR circuits.
The block diagram of traditional CDR using gated-VCO is depicted in Fig. 3.23 [9].
The circuit consists of two matched gated oscillators(GVCOA and GVCOB), a NOR gate, a D latch and a phase-locked loop.
GVCOA and GVCOB are respectively started and stopped oscillating by Data and Data. The schematic circuit of GVCO is shown in Fig. 3.24. The operating frequency of these oscillators is controlled by the voltage, VCTRL, determined by the PLL. This PLL locks at the rate of transmission data, and uses a duplicate GVCOC to acquire VCTRL. If these three oscillators are matched, they all operate at the frequency that equals to the data rate. Finally, combine the outputs of GVCOA and GVCOB with a NOR gate, and obtain the recovered clock to sample data using D-Latch at the positioin which is in middle of one data interval if the clock generated by GVCO has 50% duty cycle.
Fig. 3.25 demonstrates the timing diagram of this circuit.
Though, this circuit has advantages such as simple architecture and elimination of phase error, it has some drawbacks. The operating frequency of GVCOA and GVCOBis
32 Chapter 3: Clock and Data Recovery
Figure 3.23: Block diagram of GVCO CDR.
Frequency VCTRL Start - Stop Gate
Out
M1
Figure 3.24: Schematic of gated voltage-controlled oscillator (GVCO).
Data
Figure 3.25: Operation of GVCO CDR.
Section 3.4 Behavior Simulation 33
merely controlled by VCTRLinstead of a PLL, and it may exist deviations with data rate.
Therefore, the phase error will accumulate when consecutive identical digits (CIDs) are received. Moreover, the mismatch between various oscillators can also cause external phase error. These appearances may incur undesired jitter to increase the bit error rate of the recovered data, and also diminish the tolerance to CIDs. In addition to the drawbacks illustrated above, the switched action of the GVCO causes variation on the recovered data and deteriorates the jitter as well.
Compared with traditional CDR, the recovered clock of EOM CDR is the output of multiphase oscillator. However, the recovered clock of typical CDR is regenerated with logic gates controlled by input data. As a result, the recovered data of conventional CDR circuit may be influenced by the jitter of input signal, but that of EOM CDR does not be impacted. In addition, no matter how the received data is impacted by noise, ISI and jitter, this EOM CDR can recover data at more proper position.
3.4 Behavior Simulation
In this section, implement this EOM CDR with MATLAB and verify the function.
The diagram is demonstrated in Fig. 3.26. In order to conform to actual situation, this behavior simulation adds extra noise and the influence of ISI on the received data instead of ideal input signal. The input signal is shown in Fig. 3.27.
From the MATLAB simulation, the EOM CDR can select one phase clock to recover data. In order to justify whether the selected clock conforms to the result of analysis mentioned in previous sections, measure the BER of recovered data. Calculate the bit
R a n d o m D a ta
R a n d o m N o is e
G a in L P F
D F F E O M
R e c o v e re d D a ta A
B R e c e ive d D a ta
R e c o v e re d C lo c k
Figure 3.26: The architecture of EOM CDR implemented by MATLAB.
34 Chapter 3: Clock and Data Recovery
Figure 3.27: The noise and ISI added on the received data.
Transport err
Figure 3.28: Block diagram to calculate the BER of the EOM CDR.
error rate of this implemented EOM CDR using the block diagram in Fig. 3.28.
Firstly, use eight phase clocks to recover data individually and plot the BER curve of various clocks. Then, compare the result of simulation in Fig. 3.30 with that of BER analysis in Fig. 3.29. The trades of these curves are consistent. Finally, to evidence the relation between reference voltage and the selected sampling clock. From the simulation result of Fig. 3.26, this EOM CDR selects Phase6 when the high reference voltage is 0.65V, and Phase7 when the high reference voltage is set at 0.67V. These are identical to the analysis result.
Firstly, use eight phase clocks to recover data individually and plot the BER curve of various clocks. Then, compare the result of simulation in Fig. 3.30 with that of BER analysis in Fig. 3.29. The trades of these curves are consistent. Finally, to evidence the relation between reference voltage and the selected sampling clock. From the simulation result of Fig. 3.26, this EOM CDR selects Phase6 when the high reference voltage is 0.65V, and Phase7 when the high reference voltage is set at 0.67V. These are identical to the analysis result.