採用眼圖監測技術之8Gb/s時脈資料回復電路

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୯ҥᆵ᡼εᏢႝᐒၗૻᏢଣႝηπำᏢࣴز܌

ᅺγፕЎ

Graduate Institute of Electronics Engineering College of Electrical Engineering & Computer Science

National Taiwan University Master Thesis

௦Ҕ౳კᅱෳמೌϐ 8Gb/s ਔેၗ਑ӣൺႝၡ An 8Gb/s Clock and Data Recovery

Using Eye-Opening Monitor Technique

ࢫች໥

Hui-Wen Hung

ࡰᏤ௲௤Ǻ؋ख़Ӏ റγ

Advisor : Chorng-Kuang Wang, Ph.D.

ύ๮҇୯ 99 ԃ 12 Д December, 2010

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ᇞ ᇞᖴ

ಖܭाᚆ໒ѠεΑǴ೭ঁךࡑΑஒ߈ΖԃޑӦБǶ೭΋ၡǴӧձΓ౳ύ࣮ё

ૈوளၸܭ጗ᄌǴՠךᕴᆉࢂҔךޑೲࡋǴ΋؁؁ޑوၸٰΑǶ࣮๱Ћ΢೭ҁፕ ЎǴԖᅈᅈޑག୏Ǵ೭ࢂҔӳӭ౳ఽᗋԖВрඤٰޑǶᗨฅᅺγ੤ޑғఱǴᆉࢂ

وډΑ΋ঁѡᗺǴՠךޕၰाᏢޑܿՋᗋࡐӭǴόᆅࢂႝၡޑ೛ीǵس಍ޑԵໆǵ ໆෳޑ࿶ᡍǴᗋࢂӵՖஒࣴزޑԋ݀ቪԋ֎ЇΓޑፕЎǴ೭٤ޕ᛽೿ᗋाᏢಞǶ ೭ѝࢂ΋ঁ໘ࢤ܄ޑѡᗺǴ߻य़ᗋԖ׳ߏޑၡाوǴ׆ఈךૈ୲࡭ޑ۳ΠوǶ

२ӃाᖴᖴךޑࡰᏤ௲௤؋ख़ӀറγǴ஥๏ჴᡍ࠻೭ሶӭޑၗྍǴྣ៝๱ך ॺεৎǴ٠ЪႴᓰ๱ךाр୯ۺਜǴӧ੮Ꮲు೷Бय़๏ך೚ӭࡌ᝼Ƕௗ๱ᖴᖴα ၂ہ঩ॺኘϧୖуךޑα၂Ǵ๏Α೚ӭᝊ຦ޑཀـǴᡣךޑፕЎϣ৒ૈ୼׳к ჴǵ׳ֹഢǶ

ࣴز܌೭ΟԃӭǴӧ 333 ჴᡍ࠻ғࢲ੿ޑࡐ໒ЈǶᖴᖴྣᏌᏢߏǴाόࢂᏢ ߏ΋ၡࡐऐЈޑගٮךࣴزޑБӛǵӣเך༿ಁޑୢᚒǴଽᅟᗋाႴᓰᅱ࿎ךǴ ךёૈ࡛ሶ೿౥όΑ཰Ƕᖴᖴ๮ᒸᏢߏǴନΑѳத཮ࡐᇡ੿๏ךႝၡ΢ޑཀـǴ ӧໆෳٗӳ൳ঁДǴ೿ࢂᏢߏᄌᄌ௲཮ךࡐӭໆෳाݙཀޑ٣ǴᗋԖᔅךှ،ࡐ ӭໆෳ΢ޑୢᚒǶᖴᖴ൤ᖰᏢߏǴ྽ךၶډόޕၰ࡛ሶှ،ޑΓғୢᚒਔǴᖴᖴ Ꮲߏᕴࢂಃ΋ਔ໔൩཮๏ךཀـǶᗋԖ྽ךԖҺՖሡाձΓঅׯޑЎҹਔǴᏢߏ Ψᕴࢂ཮ಒЈ࣮ၸǴගрࡐӭࡐᝊ຦ޑࡌ᝼Ƕᖴᖴדঢ়ᏢߏǴᕴࢂ཮ගٮس಍ࣴ

ز΢ޑགྷݤၟБӛǴᗋ཮פၗ਑๏ך࣮Ǵᔅշךှ،ୢᚒǶᖴᖴ႖Ꮫჴᡍ࠻ޑۑ

ܵᏢۆǴᕴࢂ཮ഉךಠܿಠՋǴฅࡕΨ཮ႴᓰךǶӧ೭ঁ൳ЯࢂتғޑӦБǴԖ

΋ঁёаፋЈᇥ၉ޑیӧǴך੿ޑ᝺ளࡐ໒ЈǶᖴᖴϐ߻౥཰ޑᏢߏॺ : ݊ᑣǵ דᏦǵڷၲǵЎᓒǵە፣ǵޱҥᗋԖ࢙மǴᕴࢂ๏ჴᡍ࠻஥ٰࡐӭ៿ઢǴΨගٮ

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ךࡐӭႝၡ΢ޑཀـǶᖴᖴךӕۛޑӕᏢၰ൏ǴவঅፐډࣴزޑܿՋǴᕴࢂόս

༑ޑගٮךࡐӭࡐӭޑᔅշၟགྷݤǴᖴᖴգ೭൳ԃޑᔅԆǶᖴᖴλך΋ۛӳઢΞ ёངຠЈޑᏢ׌ॺ : ܴ཰ǵܷᑣǵےᐛᗋԖەֻǴԖգॺуΕࡕǴჴᡍ࠻Ξᡂ ளӳ዗ᎵǴٰჴᡍ࠻೿ࡐ໒ЈԖΓёаಠϺǶᖴᖴځдޑᏢ׌ॺ : ஜӑǵਜጎǵ ઽျᗋԖٍঅǴ೿཮ၟךᖱ၉ǴฅࡕךԖࣗሶ֚ᜤΨ೿཮ᔅԆǶךࡐགᖴ຾Α 333೭ঁჴᡍ࠻!!

ќѦӧ೭ᅐߏޑࣴز܌ΟԃӭǴёа௨ှךፐ཰ᓸΚޑ൩ࢂ௨ౚ೭ၮ୏Ǵᖴ ᖴךس௨܌ԖёངޑᏢۆᏢۂॺǴᕴࢂഉךѺౚഉךӞ໭ഉךಠϺǶᖴᖴεۆ ᓐǴӧךפόډΓޑਔংഉךӞ໭ވऑǶᖴᖴךᒃངޑᏢۂλဣǴᕴࢂӧךന໾

Јޑਔং܎ך΋עǴᗋӧך൳ЯזኖόΠѐޑനࡕ೭൳ঁД΋ޔഉ๱ךǶᖴᖴࡇ ೭΋ၡ΋ޔהڙך೭ঁಁೈǴόᆅՖਔՖӦǴѝाךԖሡाǴգ೿཮р౜௱ךǴ ᖴᖴգǴ੿ޑǶᖴᖴεᐋǴᗨฅی΋ޔ೿ؒԖӧךڬᎁғࢲǴՠࢂᖴᖴی΋ޔа

ٰޑᜢЈᗋԖഉՔǶ

നࡕനགᖴޑࢂךᒃངޑৎΓॺǶᖴᖴݿݿ༰༰ᡣךֹӄคࡕ៝ϐኁǴѝሡ

ा஑ݙޑ྽ঁז኷ޑᏢғǶգॺவٰό๏ךᓸΚǴᗋᕴࢂᏼЈךۺਜό໒Ј܈ޣ

ؒԖӳӳݙཀيᡏǶᖴᖴۆۆǴᕴࢂόჇځྠޑ᠋ךᇥ၉Ǵᗋाᡣך྽ၟ־ᙝǶ ᖴᖴ׌׌ǴଽᅟाᡣךୢୢᚒǴᗋा஥ךډೀѐވǶᖴᖴգॺǴךངգॺ : ]

ךಖܭ౥཰ΑǶᖴᖴךيᜐޑ܌ԖΓǴԖգॺωԖ౜ӧޑ೭ঁךǶ

ࢫች໥

2011.02.13

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ᄔ ᄔा

ҁጇፕЎஒ௖૸ᔈҔܭଯೲԖጕس಍ϐਔેၗ਑ӣൺႝၡ೛ीǶ२ӃǴ໺಍

ޑਔેၗ਑ӣൺႝၡǴਥᏵѬޑࢎᄬ୷ҁ΢ёаϩ଺ٿᜪǶ΋ᅿࢂᙹ࣬଑ၡᄬԋ ޑਔેၗ਑ӣൺႝၡǶ೭ࢎᄬЬाࢂճҔ࣬ՏୀෳᏔǴᄌᄌޑᡣਔેჹྗၗ਑ޑ

҅ύѧٰ଺ڗኬޑ୏բǶќ΋ᅿࢎᄬࢂຬڗኬᄬԋޑਔેၗ਑ӣൺႝၡǶ೭ႝၡ

ࢂճҔόӕ࣬ՏޑਔેǴӕਔჹᒡΕޑૻဦ଺ڗኬǴӆவ೭΋୴ၗ਑္य़Ǵפр നӳޑૻဦǶόᆅࢂব΋ᅿࢎᄬǴ೿Ԗ΋ঁӅ೯ޑୢᚒၟલᗺǴ൩ࢂਔેڗኬޑ Տ࿼Ǵࣣڰۓӧၗ਑ޑ҅ύѧǶՠਥᏵᇤዸ౗ (BER) ޑϩ݋Ǵҗܭߞဦӧ೯ၰ

໺ଌၸำύ཮ڙډᚇૻ (noise)ǵ಄ϡυᘋ (Intersymbol Interference, ISI) Ϸਔ໔

ືޑם୏ (timing jitter) ฻ӢનޑቹៜǴߞဦᇤዸ౗ (BER) നեޑՏ࿼٠όࢂၗ

਑ޑ҅ύѧǴԶࢂၟ๱ѦӧӢનቹៜԶᡂ୏ǶӢԜ໺಍ޑਔેၗ਑ӣൺႝၡ٠ό

፾ҔܭҺՖޑ௃ݩǶ

ӢԜǴҁጇፕЎගр΋ঁ٬Ҕ౳კᅱෳᐒڋޑਔેၗ਑ӣൺႝၡǶ໺಍ޑ౳

კᅱෳᐒڋЬाࢂᅱෳᒡΕߞဦޑࠔ፦Ǵฅࡕፓ᏾฻ϯᏔ (equalizer) ޑ߯ኧǴ

ٰ׳ׯ฻ϯᏔሡाံᓭޑቚ੻Ƕ೭္ஒ౳კᅱෳᐒڋᔈҔӧਔેၗ਑ӣൺႝၡǶ όᆅߞဦӧ೯ၰ໺ᒡਔڙډࣗሶߚ౛གྷਏᔈޑቹៜǴ௦Ҕ౳კᅱෳᐒڋޑਔેၗ

਑ӣൺႝၡ೿ёаפрࢌঁਔેՏܭߞဦᇤዸ౗ (BER) ၨեޑՏ࿼ѐ଺ڗኬǴ ӢԶளډၨӳޑӣൺߞဦǶ

നࡕǴךॺӧ 90 ڼԯ CMOS ኧՏᇙำ္ჴ౜೭ঁ௦Ҕ౳კᅱෳᐒڋϐ

8Gb/sޑਔેၗ਑ӣൺႝၡǶ೭ঁႝၡޑਡЈय़ᑈࣁ 0.7כ0.8mm²Ƕӧ 1 ҷ੝ޑ

ႝᓸٮᔈރᄊΠǴ྽౳კᅱෳᐒڋӧղᘐবঁਔેՏܭߞဦᇤዸ౗ (BER) ၨե ޑՏ࿼ਔǴ᏾ঁႝၡ੃઻ 254mWǶ྽଺ֹղᘐࡕǴࣁΑ࿯࣪ૈໆ੃઻Ǵ౳კᅱ

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ෳᐒڋஒ೏ᜢ௞ǴԜਔ᏾ঁႝၡѝ੃઻ 61mWǶӧؒԖҺՖ฻ϯᏔޑ௃ݩΠǴᒡ

Ε 2³¹-1 PRBSߞဦǴԶЪߞဦ࿶ၸߏࡋ 30cm FR-4 ׷਑ޑ೯ၰޑ௃ݩΠǴ೭ঁ

௦Ҕ౳კᅱෳᐒڋϐ 8Gb/s ޑਔેၗ਑ӣൺႝၡ٩ฅёаஒӣൺၗ਑ޑᇤዸ౗

(BER) फ़եډλܭ 10^-12Ƕ

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Abstract

Traditional CDR circuits can be categorized as PLL-based CDR and oversampling CDR based on its architecture. The sampling position of these CDR circuits is always fixed in the middle of the received data. However, when data is transmitted in channel, it is distorted by some non-ideal factors such as noise, ISI and timing jitter. Therefore, the best sampling position is not at the middle of the received data by BER analysis. In order to apply in different channel conditions and reduce the complexity of the front equalizer, an eye-opening monitor (EOM) CDR circuit is proposed based on the oversampling architecture. In different channel conditions, the EOM CDR circuit can select one clock phase to recover data at the position where has low BER. Furthermore, the EOM is turned off after having selected the most appropriate sampling clock to save the power consumption of CDR circuit.

This EOM CDR circuit is implemented with 90nm CMOS technology, and the core is occupied an area of 0.7^∗0.8mm². Moreover, this circuit consumes 254mW from 1.0V supply when the EOM turns on, and only costs 61mW after having selected one appropriate sampling clock. Without any pre-equalizer or pre-emphasis circuit, this proposed EOM CDR circuit can recover the 8Gb/s data, which is passing through 30cm FR-4 channel with BER < 10⁻¹².

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List of Tables

4.1 Performance summary of ring oscillator . . . 57

4.2 Power consumption of this EOM CDR. . . 59

5.1 Performance summary of this multiphase generator. . . 69

5.2 Performance summary of measurement. . . 72

5.3 Comparison of this EOM CDR circuit with others. . . 73

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iv LIST OF TABLES

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List of Figures

2.1 (a)Parallel link and (b)serial link. . . 4

2.2 Front-end of a high-speed serial link. . . 5

2.3 Cross-sections of various transmission lines. . . 5

2.4 Line model (a)without loss (b)with loss. . . 6

2.5 Skin eﬀect of microstrip line. . . 7

2.6 Skin eﬀect and dielectric loss of microstrip line. . . 8

2.7 Line model for a 1-in FR4 trace. . . 9

2.8 Comparison of actual channel loss (dashed line) and line model (solid line). 9 3.1 Operating principle of CDR circuit. . . 11

3.2 Architecture of PLL-based CDR. . . 12

3.3 Operation of PLL-based CDR. . . 13

3.4 Block diagram of traditional blind oversampling CDR. . . 14

3.5 Operating principle of traditional blind oversampling CDR. . . 14

3.6 The relation between BER and noise. . . 16

3.7 Inﬂuence of ISI on (a)periodic data and (b)random data. . . 16

3.8 Amplitude distribution from noise and ISI. . . 18

3.9 The BER with various sampling time. . . 19

3.10 The BER with various bandwidth at T_s= T_b. . . 20

3.11 The BER with various bandwidth at T_s= 0.5T_b. . . 21

3.12 (a)The timing jitter and (b)sampling window of received data. . . 22

3.13 The BER caused by the data jitter. . . 22

3.14 The simulation result of BER with various the data jitter. . . 23

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vi LIST OF FIGURES

3.15 The PDF of data jitter in (a)typical CDR, and (b)oversampling CDR. . . 24

3.16 The relation between BER and T_s with various N₀. . . 25

3.17 The relation between BER and T_s with various jitter. . . 26

3.18 (a)Ideal received data, and (b)received data in reality. . . 27

3.19 The block diagram of the EOM CDR. . . 29

3.20 The relation between window size and selected sampling phase. . . 29

3.21 The relation between reference voltage and BER, and sampling position. 30 3.22 Responses of FR4 and equalizer using various CDR circuits. . . 31

3.23 Block diagram of GVCO CDR. . . 32

3.24 Schematic of gated voltage-controlled oscillator (GVCO). . . 32

3.25 Operation of GVCO CDR. . . 32

3.26 The architecture of EOM CDR implemented by MATLAB. . . 33

3.27 The noise and ISI added on the received data. . . 34

3.28 Block diagram to calculate the BER of the EOM CDR. . . 34

3.29 The simulation results of analysis. . . 36

3.30 The simulation results of behavior simulation. . . 36

4.1 The block diagram of the EOM CDR. . . 38

4.2 Block diagram of the proposed eye-opening monitor. . . 38

4.3 Timing diagram of the EOM. . . 39

4.4 Ideal data and received data. . . 40

4.5 Operation of the data sampler. . . 40

4.6 (a) Comparator for signal ONE, (b) Comparator for signal ZERO. . . . 41

4.7 Diagram of resistors’ placement to avoid mismatch. . . 41

4.8 Schematic circuit of sample and latch. . . 42

4.9 Operation diagram of EOM logic. . . 43

4.10 Schematics of current-mode logic circuits used. . . 44

4.11 Diﬀerential to single circuit . . . 44

4.12 The relation between correct rate and the times of majority voting. . . . 47

4.13 The relation between p and the times of majority voting. . . . 47

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LIST OF FIGURES vii

4.14 Block diagram of optimal decision circuit. . . 48

4.15 Schematic circuit of D ﬂip-ﬂop in counter. . . 48

4.16 (a)Diﬀerential ring oscillator, (b)Relation of output phases. . . 50

4.17 Block diagram of the diﬀerential ring oscillator . . . 50

4.18 (a)First-order model of the injection-locked oscillator,(b)Phasor represen- tation of the currents . . . 51

4.19 (a)General block diagram of sub-feedback ring oscillator, (b)Single stage equivalent circuit. . . 53

4.20 Buﬀer of the ring oscillator. . . 54

4.21 Block diagram of delay dummy and D ﬂip-ﬂop. . . 55

4.22 Schematics of the delay dummy and D ﬂip-ﬂop. . . 55

4.23 (a)External controller and (b)phase detector for testing. . . 56

4.24 Spectrum of oscillator in free-running and injection-locked situation. . . . 57

4.25 Eight phase clocks in time domain. . . 58

4.26 Recovered clock and data. . . 60

4.27 Eye diagram of the EOM CDR. . . 60

4.28 Eye diagram of the received data and recovered data. . . 61

4.29 Layout of the EOM CDR. . . 62

5.1 Die micrograph. . . 64

5.2 Testing setup. . . 64

5.3 Block diagram of the EOM CDR. . . 65

5.4 Spectra of free running and injection locking clock at 8GHz and 9GHz. . 66

5.5 Phase noise of free running and injection locking clock at 8GHz and 9GHz. 67 5.6 Timing diagram of the recovered data. . . 68

5.7 Eye diagram and BER of received data. . . 68

5.8 Characteristics of various length channels. . . 69

5.9 BER of the data recovered by various sampling clocks in diﬀerent channels. 70 5.10 Eye diagram of received data and recovered data at 8Gb/s. . . 71

5.11 Eye diagram of received data and recovered data at 9Gb/s. . . 72

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viii LIST OF FIGURES

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Chapter 1 Introduction

1.1 Motivation

Clock and data recovery (CDR) is a critical component in the receiver end of wired communication system. Because the clock is not transmitted directly, the timing information should be acquired from the received data to allow synchronous operations.

Moreover, the data received in the receiver is noisy, so the data should be sampled again to eliminate the noise. Hence, CDR is demanded to recover data and clock, and the received data can be read precisely.

Traditional CDR circuits can be categorized as PLL-based CDR and oversampling CDR hinging on its architecture. There are some limitations in typical CDR circuits.

The presupposition of designing CDR circuits is that the optimal sampling position is at the middle of input signal and all CDR circuits attempt to recover data at this position.

Nevertheless, this premise only occurs when data is transmitted in the front circuits with bandwidth of 0.7 data rate according to the analysis of bit error rate(BER). Due to the channel loss such as ISI and noise, an equalizer in the receiver is demanded to compensate the received data. If utilize conventional CDR circuit, the equalizer should extend the bandwidth to 0.7 data rate at least. This is because the sampling position is ﬁxed at the middle of received data in typical CDR circuits. This thesis proposes an eye-opening monitor(EOM) CDR based on oversampling CDR architecture to eliminate this drawback. The EOM CDR circuit can adjust sampling position according to various input data and recover data at position with low BER. Hence, the requirement of

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2 Chapter 1: Introduction

equalizer is relaxed and not so strict as that in employing conventional CDR.

1.2 Thesis Overview

This thesis presents the design and implementation of an eye-opening monitor (EOM) clock and data recovery (CDR). Because this proposed EOM CDR circuit is applied to high speed serial-link, the basic concepts of this system is introduced in Chapter 2. In Chapter 3, traditional clock and data recovery circuits are classiﬁed and illustrated ﬁrst.

Then according to the bit error rate analysis of recovered data, interpret the obstacles of typical CDR and propose an EOM CDR which can elevate the drawbacks and reduce the requirements of the equalizer. The architecture and analysis of the proposed EOM CDR are also illustrated in Chapter 3. Moreover, the detailed implementation and simulation results are shown in Chapter 4. Chapter 5 demonstrates the testing environments and the measured results. Finally, the conclusion is given in Chapter 6.

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Chapter 2 High Speed Serial-Link Receiver

2.1 Introduction of High Speed Links

High speed links operating at multi-Gb/s are demanded not only in standard computer systems like the memory, storage or component interfaces, but also in specialized applications such as Internet routers or large multi-process systems. Since that devices operate at high speed in standard IC processes is diﬃcult, the high speed links and chip-to-chip interfaces are considered as a design challenge.

Traditionally, high speed links use single link. However, when the semiconductor technology progresses, the on-chip speed is increased enormously and much greater than off-chip bandwidth. Hence, the single link whose speed is restricted to the on- chip bandwidth is inadequate, and the employment of parallel links is required. High speed link with parallel-link technology for input-output (I/O) interface is depicted in Fig. 2.1(a) [1]. As the data rates increase much quickly, some issues in parallel links become significant. One is that the processing in the front transceiver to multiplex various channels is increased. Another is the channel mismatches cause signal skewing, and the synchronization between clock and data becomes much difficult. Because of these obstacles, the requirement at circuit level to implement parallel links changes into tight. After all, the cost of parallel links increases greatly as the data rates reach Gb/s range.

While the parallel transmission becomes expensive, serial high-speed links are demanded to replace parallel links. Fig. 2.1(b) [1] shows the block diagram of this tech-

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4 Chapter 2: High Speed Serial-Link Receiver

I / O I / O

D a ta

C lo c k D a ta

C lo c k

D a ta

C lo c k

T X R X

I / O ^{D a ta} I / O

+ C lo c k D a ta

C lo c k

D a ta

C lo c k

T X R X

(a ) (b )

Figure 2.1: (a)Parallel link and (b)serial link.

nology. In the serial link transmission, the clock information is embedded in the data and carried with data. Additionally, serial links applied in chip-to-chip and inter-board communications can operate at high speed with lower I/O counts and greater ﬂexibility of the kind of used material. This trend is clearly illustrated in the development of the personal component interconnect (PCI), gigabit ethernet and the gigabit backplane interconnect. Therefore, this thesis focuses on the serial high-speed links, and this chapter mainly references to [1].

2.2 Serial High-Speed Links

Fig. 2.2 illustrates the block diagram of a typical front-end in the serial link which is also called serializer-deserializer system (SERDES). In the transmitter, the multiplexer converts the parallel data into serial data, and then the driver processes these serial data. In various application or standard, the design of driver is diﬀerent, and there is generally pre-emphasis to compensate the loss which is going to be generated as passing the channel. Furthermore, the phase-locked loop (PLL) supplies high frequency clock using a reference clock with lower operating frequency. This clock synchronizes the data in the serialization and transmission processes.

As the data is transmitted in channel, it is distorted by the frequency-dependent loss of channel. Hence, an equalizer is required to compensate the non-ideal phenomena, such as ISI and noise caused by the channel in the receiver. When the output of equalizer is accurate enough for the clock and data recovery (CDR) circuit, the CDR circuit recovers the data and clock. Finally, the demultiplexer deserializes the recovered data back to the original data in parallel style.

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Section 2.3 Channel Characteristics 5

MUX

Driver &

Pre - Emphasis

Data

Equalizer

Clock & Data

Recovery DEMUX

CLK

Data

Tx PLL CLK

Electrical or Optical Channel

Figure 2.2: Front-end of a high-speed serial link.

Because the data transmitted in the high-speed serial links covers a large range of frequency, one of the design issues in this system is whether this electrical channel has uniform frequency response. The non-uniform frequency response of the channel seriously inﬂuences the integrity of signal transmitted in the high-speed serial links, and can increase the bit error rate of the recovered data. This undesirable phenomenon primarily comes from the channel’s physical characteristics such as skin eﬀect, dielectric loss and radiation loss which will be introduced in the next section.

2.3 Channel Characteristics

The electrical channel used in serial high-speed links is implemented by transmission line for the reason of less distortion. Microstrip line and stripline are two of the most popular planar transmission line categories, since they can be easily fabricated on printed circuit board (PCB) and integrated with other active or passive devices. Fig. 2.3 shows the cross-sections of these lines. In this thesis, the microstrip line is used as the electrical channel in the experiment. Therefore, following discussions mainly concentrate on this type of transmission line.

Conductor

GND Plane

W

Conductor GND Plane

W

GND Plane Dielectric

Microstrip Line Stripline

Figure 2.3: Cross-sections of various transmission lines.

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L

C

(a )

L

C

(b ) G R

Figure 2.4: Line model (a)without loss (b)with loss.

If the channel is an ideal transmission line, it can propagate signal without any distortion. Fig. 2.4(a) illustrates the per-unit length model of this ideal transmission line. The signal in this ﬁgure is transmitted from one LC unit to the next without any loss. If the ideal transmission line is terminated properly, it can be written as

Z_o=

L

C. (2.1)

However, real transmission line has undesirable physical characteristics such as skin effect, dielectric loss and radiation loss, and its per-unit length model should be modified as Fig. 2.4(b). Only skin effect and dielectric loss are considered in this model, and the radiation loss is neglected. This is because the radiation loss is comparatively smaller than that from skin effect and dielectric loss. In this figure, the resistance R represents the skin effect, and the conductance G models the dielectric loss. Hence, the characteristic impedance of this transmission line is

Z_o =

jωL + R

jωC + G. (2.2)

If the frequency is high enough, the impedance can be rewritten as

Z_o=

L

C, (2.3)

which is identical with Eq.(2.1).

The physical characteristics (i.e.skin eﬀect and dielectric loss) of the channel are par- ticularly interpreted in the following subsections, because these factors play important roles in the high speed data transmission.

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C o n d u c to r D ie le c tr ic G N D P la n e

GS

A r e a o f C u r r e n t F lo w

G N D P la n e I (x )2

x

I (x )1

B o tto m o f S tr ip

T o p o f S tr ip x

W

Figure 2.5: Skin eﬀect of microstrip line.

2.3.1 Skin Eﬀect

The skin eﬀect is caused by the distribution of current and magnetic ﬁeld in a conductor altering with various frequency. When the signal is DC, the current density is uniform across the conductor. However, if the frequency of signal becomes higher, the current tends to concentrate on the conductor surface. The approximate distributions of current at high frequency in the microstrip line is depicted in the Fig. 2.5 [2].

W and δ_s in Fig. 2.5 respectively represent the width and the skin depth of the transmission line. The skin depth is the eﬀective depth of signal current which conducts on the conductor surface. This skin depth can be written as

δ_s =

ρ

πμf, (2.4)

where μ is magnetic permeability of the conducting material and expressed in Henries per unit length. Additionally, ρ represents the resistivity of the conducting material and its unit is ohms per length. The surface resistivity R_s of the conductor is

R_s = ρ δ_s =

πρμf , (2.5)

and the attenuation caused by the skin eﬀect is written as α_skin= R_s

Z_oW =

√πρμ Z_oW

f . (2.6)

From this equation, α_skin increases when the frequency becomes higher. Moreover, this result can be explained in intuitive. Since the current of higher frequency ﬂows through a smaller cross-section than that with lower frequency, the resistance increases when the frequency becomes higher and the loss does as well.

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C o n d u c to r D ie le c tr ic G N D P la n e

G_S

F in ite C o n d u c ta n c e o f D ie le c tr ic

W A r e a o f C u r r e n t F lo w

Figure 2.6: Skin eﬀect and dielectric loss of microstrip line.

2.3.2 Dielectric Loss

When atoms and molecules move or rotate for being subjected to the changing electric ﬁeld, the electric energy is dissipated as heat. Fig. 2.6 respectively shows the skin eﬀect and dielectric loss of the microstrip line.

The property of material that quantiﬁes the dielectric loss is known as the dielectric loss tangent or tan δ. The parameter, tan δ, varies with diﬀerent dielectric material and is typically constant with frequency, at least up to 10GHz. α_d is the attenuation constant due to dielectric loss, and is written as

α_d = π√

_rtan δ

c f, (2.7)

where c is the speed of light and _r represents the relative permittivity of the dielectric.

From Eq.(2.7), the dielectric loss also increases with the frequency. Furthermore, the channel is preferable to use low loss dielectric material for minimizing loss. The most common material used in today’s backplanes is FR-4 board whose loss tangent is less than 0.02.

The total loss of the channel comprising both the eﬀects caused by skin eﬀect and dielectric loss is

α =

√πρμ Z_oW

f + π√

_rtan δ

c f

l, (2.8)

where l is the length of the channel. Because the dielectric loss linearly increases with frequency, it dominates the overall channel loss at high frequency.

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2.3.3 FR-4 Board Simulation

The channel employed in this work is FR-4 microstrip line which is extensively used in high speed serial-link. In order to comprehend the characteristics of FR-4 microstrip line, utilize software to simulate FR-4 traces of various lengths.

While consider both the skin eﬀect and dielectric loss, the conventional model in Fig. 2.4(b) is not suﬃcient for broadband design. [2] proposes a broadband model depicted in Fig. 2.7 for a 1-in FR-4 trace. The characteristics of required channel length can be obtained by cascading this model. Fig. 2.8 shows the comparison of the results of this broadband model and the software simulation.

:

1 5 0 m 1 7 5 p H

: 5 .5

: 2 2 0 0

1 8 0 fF

: 1 0 0

6 0 fF 8 0 p H

3 0 fF

1 - in F R 4 tra c e

Figure 2.7: Line model for a 1-in FR4 trace.

2 3 4 5 6 7 8 9

1 10

-6 -4 -2

-8 0

F re q u e n c y(G H z )

Gain(dB)

2 0 c m

: L in e - M o d e l

F re q u e n c y(G H z )

Gain(dB)

3 0 c m

2 3 4 5 6 7 8 9

1 10

-8 -6 -4 -2

-10 0

: L in e

- M o d e l

Figure 2.8: Comparison of actual channel loss (dashed line) and line model (solid line).

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Chapter 3 Clock and Data Recovery

When the receiver in serial link receives data stream that is noisy and asynchronous, it should first process the data with equalizer to compensate the loss caused by channel, and then use clock and data recovery (CDR) circuit to extract clock embedded in the received data. After all, a decision circuit composed of d flip-flop retimes the received data and generates recovered data which is synchronous with the recovered clock. Moreover, the jitter and noise of data accumulating during transmission can also be eliminated after data being recovered. The operating principle of CDR circuit is depicted in Fig. 3.1.

The input signal is non-return to zero (NRZ) random bit stream.

Since CDR circuit is a critical component in the receiver end of wired communication system, here focus on this component. First, introduce the traditional CDR circuits.

Secondly, illustrate the obstacles of traditional CDR circuits according to the analysis of the bit error rate (BER). Finally, propose an eye-opening monitor (EOM) CDR which can not only select one phase clock to sample data where the received data has low BER, but also relax the bandwidth and group delay requirements of the receiver front-end in

D Q

Decision Circuit

Received NRZ Data

Recovered Data

Recovered Clock Clock Recovery

Circuit

Figure 3.1: Operating principle of CDR circuit.

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12 Chapter 3: Clock and Data Recovery

the high-speed links.

3.1 Traditional Clock and Data Recovery

In this section, various traditional clock and data recovery circuits are introduced.

Moreover, these circuits are categorized by their architectures and characteristics roughly.

3.1.1 Phase-Locked Loop Based CDR

The block diagram of traditional CDR based on phase-locked loop is demonstrated in Fig. 3.2. This circuit consists of phase detector, charge pump, low-pass ﬁlter, VCO and decision circuit. PLL-based CDR circuits can be categorized by many types depending on the rate of recovered clock, or various kinds of phase detector, or if the reference clock exists or not. Here only discuss a full rate CDR circuit with a reference clock.

In the PLL-based CDR, the phase detector is used to detect the phase difference between input data and the output of the VCO. This phase detector can be simply implemented by an XOR and a d flip-flop, and its operation is illustrated in Fig. 3.3.

If there is phase diﬀerence, the average voltage of node Y will alter, and modify the operating frequency of the VCO. Finally, the recovered clock that comes from the output of VCO can exactly sample the received data at the center position.

In traditional CDR circuits, the optimal sampling position is always considered at the middle of input data where the data is thought to have low bit error rate. Hence, most designs of CDR circuits follow this premise. However, from the bit error rate

D Q

Decision Circuit

Received Data

Recovered Data Recovered

Clock Charge

Pump LPF VCO

Phase Detector

Figure 3.2: Architecture of PLL-based CDR.

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Section 3.1 Traditional Clock and Data Recovery 13

Data

D Q

CLK A

Y

Y A CLK Data

t Phase Detector

Figure 3.3: Operation of PLL-based CDR.

analysis discussed in Section 3.2, the optimal sampling position is not always at the middle of input data, but varies according to the bandwidth of or noise from the front circuits. Therefore, traditional CDR circuit is not suitable in every situation.

3.1.2 Blind Oversampling CDR

Unlike the PLL-based CDR which always recovers data at the half of one bit period (T_b/2), this CDR circuit blindly samples the received signal with M clocks simultane- ously and selects one clock which is approaching the position , T_b/2, the most to recover data. Block diagram of a blind oversampling CDR circuit [3] is depicted in Fig. 3.4.

The principle of traditional blind oversampling CDR circuit is to detect bit boundary and choose one of the sampling clocks that is farthest from the bit boundary. In other words, select the sampling clock which approaches middle of the input data. Fig 3.5 shows the operation.

Because of the premise that sampling data at center of one bit interval can acquire low bit error rate, the worst case is two sampling clocks straddle the center position of one bit period, and result in the maximum sampling time oﬀset (T_os,max) which is

T_os,max =

⎧⎪

⎪⎪

⎨

⎪⎪

⎪⎩ T_b

2M if M is odd integer T_b

M if M is even integer

, (3.1)

where T_b represents each bit period. From this equation, the sampling time oﬀset is smaller when the number of clocks M is odd. Hence, M is normally odd integer in place

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M u ltip le P h a s e C lo c k G e n e r a to r

S a m p le S to r a g e

B it B o u n d a r y D e te c tio n

Data

Selection

P a r a lle l S a m p le s P h a s e D e te c tio n L o g ic

R e c o v e r e d D a ta D a ta

Figure 3.4: Block diagram of traditional blind oversampling CDR.

Data

Sampled Data 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 Transitions 1 0 0 1 0 0 1 0 1 0 0 0 1 0 0 1 0 0 Sampling Clocks

C2C₃

C1 C₁C₂ C₃C₁ C₂C₃ C₁ C₂ C₃C₁ C₂C₃C₁ C₂C₃C₁ C₂

Clock Selection

C1 C₁ C₁ C₁ C₁ C₁ C₁

Recovered Data

Figure 3.5: Operating principle of traditional blind oversampling CDR.

of even one. When M is larger, the sampling position is closer to the center of data, and the recovered data has less jitter. Nevertheless, it consumes more power than the traditional CDR circuits stated in 3.1.1.

One advantage of this architecture is that it is a feed-forward system without feedback loop like that in the PLL-based CDR circuit. Therefore, this CDR circuit is much appropriate in some wireline system such as EPON system which requires short settling time. Although the architecture of blind oversampling CDR circuit has this advantage, it can not recover data just at the middle of input data and has sampling time oﬀset which causes jitter. Hence, the jitter of recovered data in this architecture is more serious than that in the PLL-based CDR circuit.

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Section 3.2 Bit Error Rate Analysis 15

3.2 Bit Error Rate Analysis

The criteria to determine the quality of received data is to detect its amplitude noise, inter-symbol interference or jitter. These properties all impact the bit error rate (BER) of recovered data. BER is a general performance to describe a CDR circuit.

The BER is deﬁned as the ratio of the number of errors to the total number of received data, and can be written as

BER = P (0)· P (1|0) + P (1) · P (0|1). (3.2)

P(0) and P(1) are the probabilities of transmitted bit being ZERO and ONE respectively.

Here assume the probabilities are equal (i.e.P(0)=P(1)=0.5). P(1|0) represents the probability which the bit is sampled as ONE but it is actually ZERO in transmission.

On the other hand, P(0|1) is the probability that the bit is read as ZERO but it is ONE being delivered. In the following sections, various elements causing BER will be illustrated.

In this section, analyze the relations between the characteristics and the BER. This BER analysis mainly references to the Chapter 2 in the thesis [4].

3.2.1 Noise

Noise is one of the primary causes that results in the BER. When data transmits through channel to receiver, it can be inﬂuenced by the noise. The noise leads to amplitude ﬂuctuations at the sampling point and bring errors in detecting the signal.

Fig. 3.6 shows BER calculation from the area of noise distribution. Assume the noise is Gaussian distribution with standard deviation of σ_n. From Fig. 3.6 and Eq. (3.2), if the BER is just inﬂuenced by noise, it can be written as

BER = 1 2· Q

V_{T H} − 0 σ_n

+ 1

2· Q

1− VT H

σ_n

, (3.3)

where Q(·) represents the cumulative distribution function.

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V

TH

V

TH

0 1

Probability

area = BER

Figure 3.6: The relation between BER and noise.

VIN

t t

Vo

2

(a) (b)

VOUT

VIN

VOUT

ISI

Figure 3.7: Inﬂuence of ISI on (a)periodic data and (b)random data.

3.2.2 Inter-Symbol Interference (ISI)

In reality, the noise is not the only cause of amplitude ﬂuctuation to increase the BER. Before reaching the CDR circuit, the received data passes through other circuits with limited bandwidth. If the received data is NRZ signal, it can be seen as being consisted of various pulses. In other words, every bit of the data is a pulse. Because of the bandwidth restriction, the tail of each bit can last longer than a bit period (T_b), and hence impacts on the amplitude of its neighboring bits. This inﬂuence is called

”inter-symbol interference”(ISI) and is depicted in Fig. 3.7.

An ideal NRZ signal, x(t), composed of pulses can be written as

x(t) = ∞ k=−∞

a_k· pi(t− kTb) (a_k∈ {0, 1} ) (3.4)

where p_i(t) represents the function of unit pulse and is deﬁned as

p_i(t) =

⎧⎪

⎨

⎪⎩

1 0≤ t ≤ Tb

0 otherwise

. (3.5)

Furthermore, the the kth bit of the NRZ signal decides the coeﬃcient a_k.

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From Eq. (3.4), the received data, r(t), inﬂuenced by ISI can be modiﬁed as

r(t) = ∞ k=−∞

a_k· po(t− kTb) + n(t) (a_k∈ {0, 1} ). (3.6)

p_o(t) represents the received pulse shape, and n(t) is the noise produced in transmission.

If r(t) is sampled at t = T_s+ mT_b to recover data, the received data at this time is

r(T_s+ mT_b) = a_mp_o(T_s) +

∞ k=−∞,k=m

a_k· po(T_s+ (m− k)Tb)

ISI term

+n(T_s+ mT_b), (3.7)

where m is an integer, and T_s is the sampling time oﬀset from 0 and 0 < T_s < T_b. Owing to this equation, the ISI term impacts on the decision of recovered data.

Assume the system is ﬁrst-order linear time invariant (LTI) with time constant τ , and the received pulse shape can be written as

p_o(t) =

⎧⎪

⎪⎪

⎨

⎪⎪

⎪⎩

0 t≤ 0

1− e^{− t}^τ 0≤ t ≤ Tb

1 α − 1

· e^{− t}^τ T_b ≤ t

(3.8)

in which deﬁne α≡ e^−T^b^/τ.

Replace p_o(t) of the ISI term in Eq.(3.7) with Eq.(3.8). In this system, suppose the received data is only inﬂuenced by front data. The ISI term at m = 0 can be written as

ISI = −1 k=−∞

a_k· po(T_s− kTb) = α^T^T^sb

−1 k=−∞

a_k· (1 − α) · α^−k−1. (3.9)

The sum is just accumulated to k = −1. When the impact of the prior one bit (a−1) is signiﬁcant, the ISI term is concentrated around two value, ISI₀ and ISI₁. These values are calculated from the expected value of ISI in Eq. (3.9) and illustrated below.

ISI₀ = E{ISI|a−1 = 0} = 1

2α^T^T^sb + 1

. (3.10)

ISI₁ = E{ISI|a−1 = 1} = α^T^T^s^b 1− α

2

. (3.11)

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0ISI 1ISI os0p(T)+ISI os1p(T)+ISI

ISI Distribution

* =

Noise Distribution

Total Distribution

V

TH

Figure 3.8: Amplitude distribution from noise and ISI.

These ISI terms impact on the amplitude of received data at sampling time, and repre- sented by two delta functions whose values are ISI₀ and ISI₁, respectively with prob- ability p and (1− p). p is the probability of a₋₁ = 0 and (1− p) is the probability of a₋₁ = 1. In order to simplify the calculation, let p = (1− p) = 0.5.

The total amplitude distribution including the eﬀects from noise and ISI is shown in Fig. 3.8. It is obtained by the convolution of noise and ISI distribution. The valuse of ISI and p_o(T_s) in this ﬁgure are acquired above, and then calculate the parameter of noise distribution.

The frequency response of a ﬁrst-order LTI system is H(f ) = 1

1 + τ s = 1

1 + j(2πτ f ). (3.12)

Moreover, the relation between the power spectral densities of input and output in the frequency domain can be expressed as

S_out(f ) =|H(f)|²S_in(f ) = 1

1 + (2πτ f )²S_in(f ). (3.13) If the additive white noise of the input in receiver has double-sided power spectral density N₀

2 , the total noise power can be calculated from Eq.(3.13) and written as

P_total= σ²· Tb =

_∞

−∞

N₀ 2

1 + (2πτ f )²df = N₀

4τ (3.14)

where σ is the noise variance.

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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

−12

−10

−8

−6

−4

−2 0

Ts(UI) log 10BER

f−3dB/data rate = 0.7

N0 = 5*10⁻³ N0 = 6*10⁻³ N₀ = 7*10⁻³ N₀ = 8*10⁻³

Figure 3.9: The BER with various sampling time.

Total BER shown in Fig. 3.8 is

BER = 1 4

Q

0.5− ISI₀ σ_n

+ Q

0.5− ISI₁ σ_n

+ Q

p_o(T_s) + ISI₀− 0.5 σ_n

+ Q

p_o(T_s) + ISI₁− 0.5 σ_n

.

(3.15)

From this equation, it can be comprehended that BER is related to sampling point (T_s), bandwidth of the system (τ ) and noise power spectral density (N₀).

Use MATLAB to simulate the BER with various parameters. Fig. 3.9 shows the relation of BER and sampling point in a ﬁrst-order LTI system with equal N₀ and bandwidth. According to Fig. 3.9, this system obtains lower BER when the sampling point (T_s) is closer to T_b. This conclusion also can be explained based on the formula of received data. From Eq. (3.8), the amplitude of received data at sampling time can be written as

p(T_s) = 1− α^Ts^Tb. (3.16)

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0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

−14

−13

−12

−11

−10

−9

−8

−7

−6

−5

−4

f−3dB/data rate log 10BER

Ts = T

b

N0 = 5*10⁻³

N0 = 6*10⁻³

N0 = 7*10⁻³

N0 = 8*10⁻³

Figure 3.10: The BER with various bandwidth at T_s = T_b.

The amplitude reaches maximum at T_s = T_b and the BER in Eq. (3.15) is going to be minimum if N₀ and bandwidth are identical.

From Fig. 3.9, the optimal sampling point in the LTI system is at T_s= T_b. In order to find the bandwidth with lower BER, simulate the BER with various bandwidth at T_s = T_b, and the result is demonstrated in Fig. 3.10. From this figure, it depicts there is a trade-off between the noise and the ISI influence. When the bandwidth becomes boarder, the noise injects into the receiver and causes higher BER. However, if the bandwidth is excessively small, the impact of ISI is significant and limits the BER. At T_s = T_b, it exists an optimal bandwidth to acquire minimum BER and the value is 40%

of the data rate.

Although the optimal sampling point is at T_s= T_b based on above simulation results, the typical sampling point is in the middle of the received data (i.e.T_s = 0.5T_b) in traditional CDR circuits. The simulation result is in Fig. 3.11. Therefore, the bandwidth is designed to about 70% of the data rate in the receiver with traditional CDR circuits.

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0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

−8

−7

−6

−5

−4

−3

−2

−1

f−3dB/data rate log 10BER

Ts = 0.5T

b

N₀ = 5*10⁻³

N0 = 6*10⁻³

N0 = 7*10⁻³

N₀ = 8*10⁻³

Figure 3.11: The BER with various bandwidth at T_s = 0.5T_b.

3.2.3 Timing Jitter

Timing jitter is also one of the factors inﬂuencing the BER, and is mainly caused by two sources. One is data jitter and the other is the uncertainty of the sampling clock.

These two causes will be respectively illustrated later.

In previous sections, assume the data transitions defined as the time of the data crossing the decision threshold (V_{T H}) occur at mT_b (m ∈ integer), and the amplitude fluctuation dominates the BER. However, the actual time of data transition deviates from the expected value thanks to the non-ideal effects mentioned before, e.g. noise and ISI. This phenomenon is called data jitter and leads to timing jitter depicted in Fig. 3.12(a). The data jitter reduces the eye diagram of received data on the horizontal direction. Fig. 3.12(b) shows this appearance. When the data jitter alters larger, the sampling window where the BER can achieve the target becomes smaller. Furthermore,

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V

TH

Jitter

T

b Original Sampling Window

Sampling Window Impacted by Jitter

(a) (b)

Figure 3.12: (a)The timing jitter and (b)sampling window of received data.

VT H

Tb

(a ) (b )

R e a l D a ta S a m p le d D a ta

t

t S a m p lin g C lo c k

0 1 0 0 1 1 0 1 0

0 1 0 0 1 1 1 1 0 S a m p lin g C lo c k

d a ta

P D F (t)

Tb

Figure 3.13: The BER caused by the data jitter.

if the sampling point is ﬁxed, the BER increases due to the error detection caused by the data jitter. Fig. 3.13 shows the BER from jitter which is the area under the tail of P DF_data(t). P DF_data(t) is the probability distribution of total jitter, and σ_d represents the variance of the data jitter. If there are no noise and ISI, and sampling clock is ideal, the BER only inﬂuenced by data jitter is written as

BER(T_s) = 1 2

_∞

Ts

P DF_data(t) dt

+ 1

2

_−T_b_+T_s

−∞

P DF_data(t) dt

. (3.17) Additionally,

P DF_data(t) = 1

√2πσ_d · e−^(t−T_2σ2^s⁾²

d . (3.18)

The errors induced by data jitter are independent of those from amplitude fluctuations that come from noise and ISI. Use MATLAB to simulate the BER caused by data jitter and demonstrate the result in Fig. 3.14. Based on this figure, if the received data is only influenced by the data jitter, the optimal sampling point is in the middle of the data.

Therefore, the traditional CDR circuits can acquire recovered data precisely.

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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

−14

−12

−10

−8

−6

−4

−2 0

Ts (UI) log10BER

σ_d= 0.04 (UI) σ_d = 0.05 (UI) σ_d = 0.06 (UI) σ_d = 0.07 (UI)

Figure 3.14: The simulation result of BER with various the data jitter.

Another source to impact on the BER is clock jitter. The probability distribution function of clock jitter, P DF_clk(t), in various CDR is distinct. In the traditional CDR, the P DF_clk(t) is related to not only the jitter from clock generator, but also the data jitter. Because the clock of these architectures is regenerated by some logic gates which received data control, the data jitter impacts on the clock jitter as well. σ_c represents the variance of the clock jitter, and the P DF_clk(t) is written as

P DF_clk(t) = 1

√2πσ_c · e−^(t−T^s⁾

2

2σ²_c . (3.19)

Because the clock is not regenerated in the blind oversampling CDR, the clock jitter does not relate to data jitter. The sampling time is not at 0.5T_b similar to that in the typical CDR, but has an oﬀset from the middle of one bit period. Therefore, the P DF_clk(t) of oversampling CDR is consisted of the jitter generated from clock generator and the sampling time oﬀset. The probability distribution function of the sampling time

(40)

(a ) (b )

S a m p lin g C lo c k P D Fc lk(t)

Tb

S a m p lin g C lo c k P D Fc lk(t)

Tb

O ffs e t

Figure 3.15: The PDF of data jitter in (a)typical CDR, and (b)oversampling CDR.

oﬀset is

P DF_os(t) =

⎧⎪

⎨

⎪⎩

M −1

2M < t < 1

2M (M ∈ odd integer)

0 otherwise

(3.20)

where M is the number of clocks to sample data and has been mentioned in Section 3.1.2. Finally, combine the original clock jitter from the oscillator and this sampling time oﬀset, and the P DF_clk(t) is written as

P DF_clk(t) =

⎧⎪

⎪⎨

⎪⎪

⎩

√M

2πσ_c · e−^(t−T^s⁾

2

2σ²_c −1

2M < (t− Ts) < 1 2M

0 otherwise

. (3.21)

Fig. 3.15(a) and (b) separately demonstrate the probability distribution function of clock jitter in traditional CDR and blind oversampling CDR.

3.2.4 Overall BER and Comparison

From previous sections, the noise, jitter and ISI all impact on the BER independently.

Combine all the causes to discuss the BER in this section. The BER related to noise and ISI terms has been illustrated in Eq.(3.15). Now add the timing jitter into this equation and temporarily assume that the sampling clock is ideal. According to [4], the

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BER without clock jitter at sampling time (T_s) is

BER(T_s) = 1 4

Q

0.5− ISI0(T_s) σ_n

·

1 + Q

T_s− Tb

σ_d

+

_T_s

−∞

P DF_data(t)· Q

0.5− ISI1(T_s− t) σ_n

dt

·

1 + Q

T_s− Tb

σ_d

+ Q

T_s σ_d

+ Q

T_b− Ts

σ_d

.

(3.22)

The simulation result of MATLAB is depicted in Fig. 3.16. Here supposes the band- width of previous circuit is 70% of data rate and vary N₀ to demonstrate the relation between BER and the sampling point. It can be seen from this figure that the finally optimal sampling point is not in the middle of the received data. If the data influenced more seriously by noise and ISI, the optimal sampling point is closer to T_b in the LTI system. Otherwise, if the data impacted more critically by timing jitter, the optimal sampling point is closer to middle of the data (0.5T_b).

0 0.2 0.4 0.6 0.8 1

10⁻¹⁵ 10⁻¹⁰ 10⁻⁵ 10⁰

Ts(UI)

BER

f−3dB/datarate = 0.7, σ_j = 0.05 (UI)

N0= 3e−3[V²/Hz]

N0= 4e−3[V²/Hz]

N0= 5e−3[V²/Hz]

N₀= 6e−3[V²/Hz]

Figure 3.16: The relation between BER and T_s with various N₀.

採用眼圖監測技術之8Gb/s時脈資料回復電路

Graduate Institute of Electronics Engineering College of Electrical Engineering & Computer Science

National Taiwan University Master Thesis

ᇞ ᇞᖴ

ᄔ ᄔा

Abstract

Contents

List of Tables

List of Figures

Chapter 1 Introduction

1.1 Motivation

1.2 Thesis Overview

Chapter 2

High Speed Serial-Link Receiver

2.1 Introduction of High Speed Links

2.2 Serial High-Speed Links

2.3 Channel Characteristics

2.3.1 Skin Eﬀect

2.3.2 Dielectric Loss

2.3.3 FR-4 Board Simulation

Chapter 3

Clock and Data Recovery

3.1 Traditional Clock and Data Recovery

3.1.1 Phase-Locked Loop Based CDR

3.1.2 Blind Oversampling CDR

3.2 Bit Error Rate Analysis

3.2.1 Noise

V

V

0 1

0 1

area = BER

3.2.2 Inter-Symbol Interference (ISI)

ISI Distribution

* =

Noise Distribution

Total Distribution

V

3.2.3 Timing Jitter

V

Jitter

T

(a) (b)

3.2.4 Overall BER and Comparison