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After understanding the effects of materials properties and the behavior in FC environment, this section will focus on total losses in the transmission of microwave frequency through CPW line in FC structure. Generally, a total loss in microwave signal follows Equation (2):

Insertion/ Total loss, S21 = Reflection/ Return loss, S11 + Real loss Equation (2) The two losses of greatest concern are losses caused by signal reflection, due to

impedance mismatch and the loss of signal energy into the dielectric of the material.

Reflection loss is a result from impedance mismatching of the CPW line in FC environment, including: impedance at substrate (Zs), impedance at chip (Zc) and impedance at the bump transition (Zb). This loss can be improved by parameter modification at substrate side. Wolfgang et al. reported, by introducing parameter modification such as compensation at signal width (Cw) , pad overlap (lob) and ground pad shrinkage (SL), S11 can be significantly been improved [15][Figure 2.8].

On the other hand, when the under-fill is applied between the chip and substrate, the total impedance of the system changes effectively. It is because MMICs are usually designed for air with a permittivity of єr = 1 as the medium above the circuit. If the permittivity of the surrounding medium is increased due to encapsulation material, reflection effect becomes more pronounced since the dielectric material is in direct contact with the chip surface. One can tackle this problem by including the detuning in chip design a priori or by having a relatively thick dielectric layer (ex epoxy encapsulant) on top of the chip so that the influence of the under-fill is more or less negligible.

Meanwhile, the second pronounced loss which contributes to total loss is called real loss. This loss can be defined in Equation (3).

Real loss = Metal loss + Dielectric loss + Radiation loss Equation (3) Radiation loss is the attenuation that has very small effect, which usually can be neglected. In this case, metal loss and dielectric loss become dominant in microwave transmission line real loss.

Metal loss is the attenuation due to resistivity loss and skin effect. Voltage drop along the PCB trace, due to resistance in the trace is unavoidable. All metals

carry its own bulk resistivity (Cu = 1.673 μΩ-cm, Au = 2.44 μΩ-cm & Sn = 11.55 μΩ-cm). Higher bulk resistivity results in higher resistivity loss. However, from the DC through frequencies up to a few MHz, the current moves through the entire cross sectional area of the trace. At these frequencies resistance is extremely small, hence resistive losses are extremely small.

As frequencies increases (up to GHz), the energy moving in the trace is forced to the outer perimeter by the large magnetic fields present in higher frequency signals. This is known as skin effect because the majority of the energy is forced to the outer skin of the trace. From the equation R = ρ.L/A (R = resistance, ρ = Bulk resistivity, L = trace length, A = Cross sectional area of the trace), the reduced in cross sectional area of the trace will cause the resistance of conductor to be increased. This case is not favored in microwave frequency.

Dielectric loss is defined as the resonance losses for the ionic and electronic oscillation in the dielectric material. In short, this loss is due to movement or rotation of the atoms or molecules in an alternating electric field. This loss is contributed by chip loss, substrate loss and encapsulant loss [Equation 4] [Figure 2.9].

Dielectric loss = Chip Loss + Substrate Loss + Encapsulant Loss Equation (4)

Chip loss and substrate loss is induced from chip and substrate separately when microwave signal is propagating along the trace line. Choosing a low loss tangent in materials guarantees a low dielectric loss. With the higher loss tangent of the substrate in use in this research (RO3210 = 0.0027), the microwave performance is expected to be more severe compare to conventional microwave substrate (Al2O3 = 0.0002). As a result, the dielectric loss will be more pronounced in this organic

substrate.

Besides, the application of encapsulant in this flip chip structure will cause the permittivity of the surrounding medium to be increased. Few researches have been carried out to test the applicable of underfill [2][14] and glob top [21] in microwave packaging, and yet the mechanism, effect and reliability performance of encapsulant in microwave application is not well explained and studied through these papers.

Table 2.1 Microwave frequency band Microwave Frequency Bands

Designation Frequency range Designation Frequency range

L band 1 to 2 GHz Q band 30 to 50 GHz

Table 2. 2 Material properties of conventional microwave packaging Chip :

Thermal Conductivity 0.55 18-35 0.23

Cost USD (2‖X2‖) 88.9 23.0 2.02

Table 2.3 Comparisons of material properties of ceramic and polymer resin Resin Tg/ °C CTE

Figure 2.1 Hierarchy of electronic device packaging Resource: www.aciusa.org

(a)

(b)

Figure 2.2 (a) Wire Bonding technique 2.2(b) Flip Chip bonding

Resource: http://upload.wikipedia.org/wikipedia

First Level Interconnect

Second Level Interconnect

Third Level Interconnect

Figure 2.3 Chip on Board (COB) – Wire-bond type Resource: http://encyclopedia2.thefreedictionary.com/chip+on+board

2.4 (a)

2.4 (b)

Figure 2.4 (a) Under-fill between chip and substrate 2.4 (b) Cross section view Resource: http://www.namics.co.jp/e/product/01/06.html

Chip Under-fill

substrate Bump

Under-fill

substrate Chip

Bump

(a)

(b)

Figure 2.5(a) Glob top on a bare chip 2.5(b) Cross section view Resource: http://www.somar.co.jp/english/products/03_somatect.html

Figure 2.6 The FC interconnect and relevant parameters: Bump Height, h and Pad Overlap, Lp

Resource: IEEE Microwave Magazine

Chip Glob Top

substrate Wire Bond

Glob Top Chip

Wire Bond

substrate

Figure 2.7 Material parameters: Dk, tan δ, Dielectric thickness (H) &CPW line width

(a)

(b) (c) (d) Figure 2.8 (a) Effective impedance of FC system and parameter modification (b) Pad

Overlap, lob (c) Signal Width Compensation, Cw and (d) Ground Pad Shrinkage, SL

Figure 2.9 Chip loss, underfill loss and substrate loss in dielectric loss

G S G

substrate

CPW

H

Dk

tan δ

Z

c

Z

b

Z

s

Chip Loss Underfill Loss

Substrate Loss

Chapter 3

Experiment and Process Flow

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