Chapter 2 Overview of Related Works
2.7 A Time-to-Digital-Converter-Based CMOS Smart
This work is the completely all-CMOS-based version of smart temperature sensor without any lateral or vertical bipolar transistor. It is featured with extremely small chip area and low power consumption. In order to eliminate the burden of the curvature calibration for the BJT-based temperature sensing circuits, an innovative architecture for smart temperature sensors is presented in this paper. First, a temperature-to-pulse generator is used to generate a pulse with a width proportional to the measured temperature. Then, the output pulse is
fed to the input of a cyclic TDC to generate the corresponding digital output. A very important modification of this proposed smart temperature sensor is the replacement of the conventional ADC by a cyclic TDC. Accordingly, a temperature-to-pulse generator rather than the bandgap reference is utilized to generate the thermal sensitive output pulse required by the cyclic TDC. Without any curvature correction or dynamic offset cancellation, the effective resolution is better than 0.16℃, the power consumption is about 10μW at a sample rate of 2 samples/s and 0.49mW at a measurement rate as high as 1 kHz is feasible.
2.8 A summery of the related works
The following is a table to highlight the unique features and approaches of every related works.
Table.2 A summery of the related works
Sensor Resolution
[11] 0.015 429µW 2.5 0.125~30 Integrated Integrated Yes
[12] 0.16 10µW 0.175 2 No No No
Chapter 3 Proposed Architecture and Algorithm
3.1 Proposed Architecture 3.1.1 Design basis
Fig.3 The architecture of the proposed temperature sensor
Figure 3 clearly shows the entire idea of the proposed architecture which is basically derived from [12]. Its features of the simple structure and low cost are adapted to the proposed sensor but its method of the pulse-manipulating is implemented in a different way as the following depicts.
3.1.2 Three points of distinction
First of all, the input going into the circle is merely a pulse generated from a reset signal through a short delay line and XOR-ing its original one out of an exclusive-OR gate. It doesn’t matter whether the pulse is linearly proportional to temperature or not as long as it’s longer than at least 3-ns delay time. Because any pulse shorter than 3-ns would vanish through the long thermal delay line.
Nevertheless that means it is more flexible and less constrained. Second, there is a multiplexer, before the pulse enters the circulating loop, to block noise or jitters from getting into the loop after the pulse in case of any signal ambiguity.
Third and the most importantly, the pulse expands instead of shrinking in the circling loop. It is the pulse-expanding delay line that makes gradual growth more constant and stable in the loop such that the linearity with temperature sustains.
3.1.3 Design concept
The best way for monitoring operation temperature on an IC device is to integrate the sensor onto the IC chip itself so as to get it close to the heat source.
However, the temperature sensor itself must not take up too much area and
generate too much heat on the IC chip, or it will nullify its original usage. In other words, the sensor has to be as low-cost as possible. There is certainly a trade-off between accuracy and cost. Therefore, the proposed temperature sensor is targeted on low-cost version with a little penalty of less accuracy.
3.1.4 Signal flow
First, a regular pulse generator generates a pulse with a width greater than 3 nano second independent of the environment temperature. Next, the output pulse feeds into the input of a circulating Time-to-Digital Converter to generate the appropriate digital output. In the following sections, the implemented circuit and the operation principle of each block will be discussed in detail.
Fig.4 The Signal flow of the proposed temperature sensor
Figure 4 plots the block diagram of the proposed sensor. An innovative circuit composed of a simple pulse generator and a circulating TDC converts the measured temperature into corresponding digital output. The pulse generator without any lateral or vertical bipolar transistor generates a pulse with a width which has nothing to do with the ambient temperature. Since no voltage or current signal generates, conventional voltage/current ADC are irrelevant to
output coding. Instead, the generated pulse with zero thermal coefficients feeds into a circulating TDC to produce the corresponding digital output.
There is only one input and that is the reset signal. Once reset starts, the 3-ns pulse quickly forms and the counting is ready to commence. Subsequently, after entering the circulating loop, the pulse propagates through the thermal delay line and the pulse expanding delay line. The sequence going through these two delay lines is irrelevant since they function separately and differently and don’t interfere with each other as illustrated in Figure 5.
Fig.5 The principles of the operation in the circulating loop
The purpose of the thermal delay line is to generate a clock-like signal established by a series of pulses separated by the thermal time delay. The
interval, which is the delay time determined by the thermal delay line, between pulses is very linearly proportional to temperature. The following is the equation of the relation between the delay time and the temperature in the thermal delay line.
The purpose of the pulse-expanding delay line is to gradually widen every pulse at every round every time passing thru it in the loop until the edge of every pulse touches one another back to back. It will appear like that the signal becomes unity within the entire circulation as the final loop shown in Figure 5.
The expanding width by a specific amount that grows in every round is exactly the effective resolution of this thermal sensor. The following is the equation of the relation between the changing pulse width and the length ratio of delay elements.
From the equation above, in order to obtain finer resolution that is the changing pulse width, the length ratio should be just a little greater than unity and be as close to unity as possible at the same time.
For different degrees of temperature, the delay time of the thermal delay line gets longer at higher degree since it is linearly proportional to temperature.
And it leads to wider intermittent space between pulses and as a result, higher number of digital code because it takes more loops for the pulse to expand until the signal reaches unity. Therefore, the number of digital code increases proportionally with the degree of temperature. For the same degree of temperature, the finer pulse-width the expanding can attain, the higher number of digital code the counter can reach, and the better resolution the sensor can achieve because the equivalent spanning of degree can be resolved by a greater number of digit code.
3.1.4.1 A simple pulse generator
Figure 6 shows a simple circuit utilizing gate delays to generate the non-thermally-sensitive pulse. The reset signal is delayed a certain amount of time by the delay line composed of even number of NOT gates, then XORed with itself to generate the propagation delay ( > 3 ns) of the delay line as the required output pulse.
Fig.6 A simple pulse generator
3.1.4.2 A Time-to-Digital Converter
The very distinct modification from the predecessor is moving the thermal sensitive delay line from the pulse generator to the time-to-digital converter.
Another important modification of the proposed smart temperature sensor like the predecessor is the replacement of the conventional ADC by a cycling TDC with block diagram shown in Figure 7. The delay line is composed of even number of NOT gates. After reset, the input pulse circulates in the cyclic delay line and is expanded by a specific amount of pulse width per cycle until unity dominates thoroughly in the loop. The counter is used to count the number of circulation times of the input pulse in the delay line and generates the corresponding digital output.
Fig.7 A Time-to-Digital Converter
3.2 Algorithm
As can be seen from the simple structure of the proposed sensor, there are
only two major components that can be clearly expressed by mathematical methods. One is the thermal-sensitive delay line; the other is the pulse-expanding delay line. The equation derivations and simulation results are quoted here for references.
3.2.1 The thermal-sensitive delay line [13]
The delay of an inverter is the sum of the charging and discharging time to load capacitor. When temperature varies, the values of charging and discharging currents will also vary and the delay will change accordingly. Therefore, it is straightforward to control the current in the delay line to achieve a delay that has linearity to temperature. The existence of a zero to temperature coefficient (ZTC) point in transconductance characteristics of a MOS device by mutual compensation of mobility and threshold voltage has been investigated [11].
Based on this characteristic of a MOS transistor at the vicinity of ZTC point, a current inversely proportional to temperature can be created.
The transconductance characteristics of an NMOS transistor are described by the following equation
In this equation, mobility and threshold voltage change with temperature and have mutual compensation effects. It is usually assumed that threshold voltage depends on temperature which is described as
range of value. On the other hand, the mobility depends on temperature as0 compensate each other and the characteristics of a MOS device will have a common intercept point (VGSZ, IDZ), which is given
0
Figure. 8 shows, as an example, the simulation result of transconductance characteristics for a NMOS transistor with temperature in a 0.18μm CMOS technology. One can see that the characteristics have a common intercept point (0.88V, 2.064μA). If a NMOS transistor is biased at this point by a voltage VGSZ, the drain current will not change against temperature. This is the ZTC point for this device.
If (VGSZ, IDZ) exists, at an arbitrary temperature T, and for VGS1 = VGSZ +ΔVGS, the drain current is determined by [11]:
Fig.8 Transconductance characteristics of NMOS with W/L=1μm/10μm
To produce an inversely proportional to absolute temperature current, we use two diode connected NMOS transistors with the same dimension biased at two different voltages VGS1 and VGS2. The difference between the two drain currents is calculated as below
2 2 inversely proportional to temperature. This amount of current will be used to bias for an inverter based delay line to obtain delay proportional to temperature.
The propagation delay of an inverter is the sum of charging and discharging time to load capacitor which is determined by [15]
L DD transition time, k is a constant, and CL is load capacitor. Substituting (8) into (9) results in
From this equation, we can see that the delay time is absolutely linear to temperature and has positive temperature coefficient.
In fact, ΔVGS1 and ΔVGS2 vary with temperature and is assumed that changes of ΔVGS1 and ΔVGS2 are small enough and compensate each other i.e.
ξ1(T) ≈ -ξ2(T), equation (10) will be still valid in a temperature range of interest.
Fig.9 The schematic of the thermal delay line
Figure 9 shows the schematic of the bias current source circuit that generates a current inversely proportional to temperature. All NMOS transistors have the same dimensions and operate in saturation region. The ZTC point in the simulation is (0.88V, 2.064μA). In this circuit, we bias two transistors M1 and M5 at gate voltages VGS1 = 0.72V and VGS2 = 1.08V at room temperature, respectively such as ΔVGS1 ≈ -ΔVGS2 by using two simple circuits.
Transistors M3, M4, M7 and M8 serve as current mirrors. The bias current IBIAS is formed by the larger current I1 through M5 minus the smaller current I2 through M1 and driven into a diode-connected M9. This current then will be
mirrored to the transistors M10 and M11 to generate two bias voltages VN and VP for the delay line.
The delay line is a chain of even number of current starved inverters. When an input pulse goes into the line, it propagates through inverters and is delayed with time determined by current sources in inverters.
The simulations of the delay line were performed by using a 0.18μm process with a supply voltage of 1.8V. The device sizes for delay line are 1μm/2μm for NMOS and 3.5μm/2μm for PMOS. Figure 9 shows a plot of the output delay of the delay line versus temperature from -40°C to 120°C. The simulation results possess excellent linearity and a good agreement with predicted one. An offset delay appearing in the measurement range can be reduced by subtracting to a constant amount of delay with a XOR gate.
Fig.10 The Delay versus temperature of the thermal delay line
The corresponding non-linearity error is plotted in Figure 11. The error is within 0.24 °C in a range of temperature from -40 °C to 120 °C. This error is mainly due to the variation to temperature of the gate voltages of two diode connected transistors and α is not exactly equal to -2. This result translates to the non-linearity error of 0.15% with a curvature correction.
Fig.11 The Non-linearity error with supply voltage = 1.8V
Another version of the delay line without current source used in [12] also is designed and simulated for comparison. The dimensions of devices in this delay line are the same with those in the thermal delay line. The non-linearity error is unacceptably high 4.4°C within the same temperature range. The performances
of the two temperature sensors are summarized in Table 3 for easy comparison.
Table.3 The performances of the two temperature sensors
Sensor Inaccuracy Temperature range Power supply CMOS technology
[12] 0.9 °C 0 °C - 100 °C 3.3V 0.35µ
Thermal 0.24 °C -40 °C - 120 °C 1.8V 0.18µ
This delay line presents a highly linear dependence of delay on temperature.
Based on the characteristic of a CMOS device at ZTC point, a bias current circuit has been designed to control the delay of the delay cell. The simulated result has a good agreement with predicted one. Non-linearity is around 0.24°C without any subtle curvature correction in the temperature range from -40°C to 120°C. The proposed delay line can be used as a temperature sensor block for smart sensor or built-in temperature sensors in VLSI chips.
3.2.2 The pulse-expanding delay line
Time-to-Digital Converters have been implemented digitally using either the inverter chain method or Vernier delay line method [16].
3.2.2.1 Inverter chain method
If the end application does not require a very high resolution, time digitization can be carried out using a chain of inverters [17]. The
implementation is shown in Figure 12. The resolution achieved using such an implementation is one inverter delay (tinv) and is about 40ps in deep-submicron CMOS process. This resolution can be further improved by time-averaging [17].
This implementation is very compact but the resolution achievable is limited to one inverter delay. Even though tinv is decreasing with scaling of technology, any finer time digitization is impossible. The number of inverters required in the inverter chain to cover a dynamic range of Tp is {Tp /tinv}
Fig.12 TDC built with chain of inverters
The TDC output is typically a thermometer or pseudo-thermometer code that provides a digital representation of the phase difference between CLKA and CLKB.
3.2.2.2 Vernier Delay Chain method
Vernier delay lines can be used to achieve time digitization with a very high resolution [18]. In the Vernier delay line method illustrated in Figure 13, two
buffer lines with delays of t1 and t2 are used in each stage. The resolution achieved is of the order of (t1-t2). Since resolution is determined by the differential delay, this method enables us to digitize time with a very high resolution [18][19]. Time resolutions of the order of 30ps have been reported using this method [19].
Fig.13 TDC built with Vernier Delay Line
The number of Vernier stages required to cover a dynamic range of Tp is circuitry grows linearly requiring long chains of delay elements. Since layout of such an implementation can span a large area, process variations introduced may nullify the resolution gain achieved using the Vernier line method.
The pulse-expanding delay line of the proposed temperature sensor invokes the use of the Vernier line method.
Fig.14 The effect of the gates' non-homogeneity on pulse width
The pulse-expanding mechanism is controlled by the non-homogeneity of the gates in the cyclic delay line as shown in Figure 14 [20]. Assuming all of the NOT gates have the same dimension except for the (n)th inverter whose width is the β times of those of the others. To simplify the derivation of the pulse-expanding mechanism, the input pulse is assumed to be stepwise at each stage for the first-order approximation. When the pulse goes from the (n-1)th stage to the (n)th stage, the falling time and the rising time can be derived as follows[21]:
1 1
where kNn-1, kPn-1 are the transconductance parameters of the (n-1)th NOT gate, and CLn is the effective input capacitance of the (n)th NOT gate. Assuming VTN
= -VTP, the amount of the pulse expanding from (n-1)th stage to (n)th stage can be analyzed as tPLH1 - tPHL1 to yield βCLn-1. The total amount of pulse expanding from (n-1)th stage to (n+1)th stage can be found by adding (16) and (17) to yield:
1
is a proportional factor which is approximately layout-independent. Similar to the propagation delay in a NOT gate with equivalent NMOS and PMOS, the transconductance parameters and threshold voltage in ΔW are still affected by temperature variation. To reduce the thermal sensitivity of ΔW, the thermal compensation scheme of the current-mirror and diode-connected configuration in the Vernier delay line is applied to all of the gates in the pulse-expanding delay line. The pulse-expanding mechanism will be controlled dominantly by the aspect ratio difference of adjacent gates. If the delay line is homogeneous with β = 1, the amount of the pulse expanding per cycle will be zero, quite reasonably, from (18). Otherwise, the input pulse will be expanded or shrunk for β > 1or β < 1, respectively.
The amount of the pulse-expanding per cycle relative to pulse width is designed to be small enough to get a satisfactory resolution for the smart temperature sensor. At the end of the pulse-expanding process, pulses will become all connected and too fully span the entire voltage range to trigger output counter correctly. To overcome the runt pulse phenomenon, a buffer with stage-by-stage signal amplification is inserted between cyclic TDC and output counter in practical implementation. The buffered pulses with full voltage swing
can make the succeeding counter operate correctly without any ambiguity.
The dead zone Toffset and the amount of pulse expanding per cycle, or the effective resolution equivalently, can be calibrated before each measurement with reference pulses Tref and 2Tref as the following [20]:
'
where N and N’ are the measured output codes of Tref and 2Tref, respectively.
With TC and Toffset, the measured width of an input pulse Tin with output code n
The timing for measuring the input signal is shown in Figure 15. The calibration technique above can also be used to compensate the error caused by any physical variation.
Fig.15 The timing of the input signal measurement
Chapter 4 Circuit Design and Performance Comparison
4.1 Circuit Design
4.1.1 The pulse generator
As Figure 6 shows in 3.1.4.1, there are only two components in this generator circuit. They are the buffer-chain delay line that causes the reset signal pause for about 3 nano second and a standard exclusive-OR gate. Figure 16
As Figure 6 shows in 3.1.4.1, there are only two components in this generator circuit. They are the buffer-chain delay line that causes the reset signal pause for about 3 nano second and a standard exclusive-OR gate. Figure 16