2.4 Active circuit
2.4.3 Active circuit operate theory
We can depart the circuit into three stages: driver stage, switching stage, and load stage.
M1 (and M4) is the first stage. In this stage, like normally amplifier, provide voltage gain to RF signal.
...(1)
RF out
gm V r
2
Chapter 3
Down-Conversion Mixer Circuit Design 3.1 Introduction
In normal, the mixer designer used Gilbert cell mixer to be the basic structure,
because it have higher isolation (including Lo-RF and Lo-IF), lower noise factor.
Although the benefits are so obvious, the Gilbert cell circuit is not such perfect. Its circuit is just like a differential pair, so if we want the circuit to have the same gain with single-balance circuit, it takes twice large of current than single-balance circuit.
But single-balance structures isolation is so poor that we cannot ignore them,
especially LO-IF isolation.
In this chapter, we are using a single-balance structure to achieve low power issue, and have some change of circuit to enhance Lo-IF isolation.
The circuit is design in TSMC 0.18m. RF frequency is 5.8GHz, Lo frequency is 5.81GHz, and IF frequency is expected 10MHz.
3.2 First stage
First stage is the most important stage of the mixer design. It can decide the total circuit power, almost can decide gain, and also has large effect on linearity and noise factor.
Because of NMOS’s characteristic - the higher frequency has the lower gain, choose appropriate current is getting hard. We cannot have too much current for low power circuit, but we also need a current for circuit characteristic.
Fig 3.1 First stage
In Fig 3.1, after we decide the current and gain of circuit, we finally can choose appropriate NMOS size for M1. And because M1 should active in saturation mode, we can easily design the VRF. Finally, M1’s width is 6m, finger is 6, and with 0.18m length. VRF is 0.7V and cause the current become about 1mA.
Because we choose 1.8V for VDD, we can almost sure our circuit consume about 2mW.
3.3 Second stage
This stage is using Lo signal to down-conversion the RF signal to IF frequency.
In this stage, Icircuit in Fig 3.1 be divide by two parts. Because we need the both side have the same gain and just opposite phase, the currents must be just the same. So we can easily design the M2’s and M3’s size in Fig 3.2.
Fig 3.2 Second stage
In Fig 3.2, I1 and I2 is about 0.5mA, is just half of Icircuit, so we can easily choose M2’s and M3’s size as half of M1’s. Width is still 6m but fingers become 3, and length is 0.18m.
0.2 0.4 0.6 0.8 1.0 1.2 1.4
0.0 1.6
-15 -10 -5 0 5
-20 10
Vg1
conversion_gain1
Fig 3.3 Simulation of VLO
Then we need to design VLo. As show in Fig 3.3, we simulate sweep VLo from 0V to 1.5V, and we can find out if VLo is between 0.7V to 1V have the maximum gain, and we check every point in this section, VLo at 1V get the most linearity, so we
choose VLo=1V for design.
3.4 Third stage
This stage is translating current gain become the voltage gain. Not like
up-conversion system, IF frequency is very low, in this case is 10MHz, so we cannot use inductances as impedance, it would need a very large inductance(Z=jL).
Although inductances have no DC power consumption, is the best choice of low power design, but the size will become too large to put it in the chip. So we have to use resistance to replace them.
Fig 3.4 Third stage
If we choose a too big resistance, there will have lots of voltage dropped on it, case the MOS below them in liner section, gets the bad gain and bad linearity. But what if we choose too small, there will still have not enough gain.
200 400 600 800 1000 1200 1400
0 1600
-30 -20 -10 0
-40 10
Rload
conversion_gain1
Fig 3.5 Simulation of Rload
In Fig 3.5, we use ADS to simulate what appropriate number it should be. We sweep from 10Ω to 1.5KΩ . We can find out when the resistance below 800Ω or larger than 1400Ω , gain will degrade. In this area, after simulate every point, we choose the best linearity point - 1220Ω for this circuit.
3.5 Cross signal feed-through
As we mention in Chpater2.4, single-balance circuit has a big disadvantage that it has a poor isolation on Lo-IF port. Although they are in different frequency, but what if the next circuit of mixer output is an amplifier, the big Lo signal will cause the MOS saturation. So we do not want large Lo signal feed-through to IF port.
Fig 3.6 Small-signal model of M2
As Fig 3.6, we can find out why the single-balance circuit has poor Lo-IF
the Vgs is the same as Vlo. So we can find Loout term in the function (2).
As we can see in Fig 3.6, the two phases are different, so they would not be cancelled by each others.
Fig 3.7 Gilbert-cell Structure
That’s check why double-balance mixer has such a good isolation of LO-IF.
That’s plot the small signal of M2 and M5.
Fig 3.8 Small-signal model of M2 and M5
Because of M2 and M5 have complete different input phase of Lo signal,
Gilbert-cell mixer can easily enhance isolation. The Lo+ signal causes 180 degree and 270 degree of phase of Lo, and the Lo- signal causes 360 degree (0 degree) and 90 degree of phase of Lo. Although because M2 and M5 is totally the same, not only size but also bias situation, so the signal’s amplitude they cause are the same, too. So as the reason, the feed-through signals are almost perfectly cancelled.
After we analyze the structure, we find out one part of Lo feed-through signals is cancelled by the opposite signal feed-through by the other MOS’s Cgd. So we design the following structure.
Fig 3.9 Second stage after design
Shows in Fig 3.8, we use C1and C2 to replace M5’s and M6’s Cgd. So we can cancel a part of Lo signal that feed-through to the IF port.
Fig 3.10 Small-signal model of M2
In Fig 3.9, the C2 is just like M5’s Cgd in Fig 3.7. We can cancel the Lo+ signal feed-through by Cgd. Having the structure like this, then we need to design the
appropriate number of C2 and C1. First we used ADS to simulate what level the Cgd is.
We floated the Source of a the-same-size MOS, and put two terms on gate and drain.
After we plot the S-parameter plan, than find a capacitance level can cause similar
23
S-parameter plan. Now we find the level is fF, what we need to do is only to optimize the number. In this level, the impedance which IF signal saw is so large, that we can consider there is an open circuit, and with out loss.
1 2 3 4 5 6 7 8 9 what if over 300fF, the isolation is stable. When we choose the number is not just “big is best”, if the C1 and C2 is too big, IF signal will pass through from them to the Lo port, cause the gain depressed. Finally we choose a 200fF capacitance as C1 and C2. This number we can have a good isolation and not to influence any other
characteristic.
To prove the capacitance is work on enhance isolation, we simulate the same circuit but one have capacitance but the others not.
The result is in following plot.
24
Fig 3.12 Simulation with capacitance
1 2 3 4 5 6 7 8 9
Fig 3.13 Simulation without capacitance
In Fig 3.11 and Fig 3.12, we can find out with the cross capacitance, Lo-IF isolation can be enhance by almost 6dB.
Back to the Fig 3.9, we can still see a 180 degree phase Lo signal appearing in IF port. We have no way to cancelling it, otherwise we use another MOS. But what if we do this way, the current will become the same level as Gilbert cell mixer, and loss our main purpose – low power.
3.6 Output buffer
Because of needing to measure all the frequency point on output port, we must have a broad band matching at output port.
The RF signal is 5.8GHz, Lo signal is 5.81GHz, and IF signal is 10MHz. In this case, we have two ways to do the matching job. First way is using traditional RF matching technology – LC matching. But because the IF frequency is so low and the three frequency is so apart, we need a very large size inductance and capacitance and also many of them. According to the chip size limit, we can only design a circuit that littler than 1.4*1.4 mm*mm. So we absolutely cannot use LC matching.
So the only way we can use is Source follower buffer.
Fig 3.14 Source follower buffer
27
Fig 3.15 Small-signal model of M7
In Fig 3.14, we can find that Rout almost equal 1/gm, because L1 is big enough that parallel connection equal to 1/gm. We can choose appropriate size that 1/gm equal to 50Ω .
freq (10.00MHz to 10.00GHz)
S(3,3) m2
m2freq=
S(3,3)=0.078 / 178.007
impedance = Z0 * (0.855 + j0.005) 27.00MHz
Fig 3.16 Simulation of S33
As Fig 3.15, we can find every frequency point is around 50Ω .
3.7 Total circuit
Finally we can have the complete circuit.
Fig 3.17 Total circuit
In Fig 3.16, all the DC_feeds or DC_blocks we can use RF bias tee to achieve their functions.
Fig 3.18 Circuit Layout
For measure convenient, we plot some pads that we can bound wires them.
Using this pad we can measure some DC data, without use any RF probe or any RF instrument.
Table 3.1 Voltage and Current
VDD VRF VLo Icircuit Power Itotal
1.8V 0.7V 1V 0.98mA 1.7mW 27.3mA
Fig 3.19 Implementation
31
Chapter 4
Simulation and Measurement Result 4.1 Simulation
We simulated both with and without the cross capacitance data. But with
capacitance, we simulated post-layout circuit. Without capacitance simulated pre-layout data.
m1freq=
conversion_gain=5.89610.00MHz
10.0000000 10.0000000 10.0000000 10.0000000 10.0000000 10.0000000 10.0000000
10.0000000 10.0000000
5.8958152
10.0000000 10.0000000 10.0000000 10.0000000 10.0000000 10.0000000 10.0000000
10.0000000 10.0000000
32
33
-25 -20 -15 -10 -5 0 5
35
Table 4.1 Compare with C and without C
4.2 Measurement
In this section, we show two conditions of voltage. First is the origin voltage’s
situation. The other is we tune a little VDD voltage to make the results close to our simulation data.
Gain = ( measure_data – RF_port_loss ) – ( RF_input + IF_loss )
Isolation_Lo-IF = ( measure_data – IF_port_loss ) – ( Lo_input + Lo_loss ) Isolation_Lo-RF = ( measure_data – RF_port_loss ) – ( Lo_input + Lo_loss )
(a) Condition 1
(b) Condition 2 Fig 4.6 Gain
(a) Condition1
(a) Condition1
(b) Condition 2 Fig 4.8 Isolation Lo-IF
-30 -20 -10 0 10
4.3 Specification
simulation data, but condition 2’s other data are more likely simulation. So finally we choose condition 2’s data as our final data.Chapter 5 Design Flow 5.1 Design flow
The simulation software ADS designer is used to design the circuit. ADS momentum is used to do EM simulation. After the layout of circuit is finished, DRC
& LVS & LPE is done to check the correction for the design.
Chapter 6
Conclusion and Improvement 6.1 Conclusion
Although low power and good characteristics cannot take both, but we still can improve them to be better. We design a single-balance structure mixer, with 2.72mW of power consumption, 6.04dB of gain, -8.45dB of Lo-IF isolation, -61.88dB of Lo-RF isolation, 2dBm of IIP3, and 17.76dB of noise figure. In our measurement and simulation, noise figure is measure or simulate by single side band. So we need to minus 3dB as double side band measure. Now we compare our design to other reference.
As we can see on table 6.1, the power of our design is the best in the table, and also twice less than others. That’s because the other reference always using
double-balance structure to implement their idea circuit. Our performance in this table is almost the best design, but not in Lo-IF isolation. Born defect of single-balance structure is really cannot be totally cured. But we still improve a lot from origin 0dB to -8.45dB.
Table 6.1 Comparison of Mixer performance
*2SSB measurement, minus 3dB as DSB data.
6.2 Improvement
The most important thing we need to improvement is Lo-IF isolation. After the project, we can find out two ways to improve it.
The first way is that we can change the layout. In fig 3.17, we can see lots of DC pad for bound wires. So many metal overlapping and close to each others may cause huge capacitance. Lo signal is 5.81GHz frequency, so the capacitance effect would more seriously. So if we cancel the pads and bias the voltages by bias tee, it can make the effect weaker.
As we mention before, Lo signal in IF port has two phases, and our design can only cancel one of it. But using Lo input is not the only way to cancel the signal, we can also find that in IF+ and IF- port, they have complete opposite phases of Lo feed-through. So we can use this situation and try another way to cancel them by each others.
Although our power is lower than others, but there still has chance to improve it.
If we add body bias to change Vth of MOS, the current can be achieved by smaller VDD. By this way, we can make the DC power lower.
Reference
[1] B. Razavi, “RF Microelectronics,“ 1st ed. NJ, USA: Prentice-Hall PTR, 1998.
[2] Soul-Yu Chao, Ching-Yuan Yang, “A 2.4-GHz 0.18-μm CMOS Doubly Balanced Mixer with High Linearity,” International Symposium on VLSI Design,
Automation and Test (VLSI-DAT), Taiwan, pp.247-250, April 2008.
[3] Ming-Feng Huang, C. J. Kuo, and Shuenn-Yuh Lee, “A 5.25-GHz CMOS Folded-Cascode Even-Harmonic Mixer for Low-Voltage Application,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 2, pp. 660-669, February 2006.
[4] Shaikh K. Alam,” A 2 GHz Low Power Down-conversion Quadrature Mixer in 0.18-μm CMOS”. 20th International Conference on VLSI Design, 2007.
[5] V.Vidojkovic, et al.,” Mixer topology selection for a 1.8-2.5 GHz multi-standard frount-end in 0.18 m CMOS” Proc. IEEE International Symposium on Circuits and Systems, vol. 5, pp. 300-303, May 2003.
[6] Jong-Ha Kim, Hee-Woo An, Tae-Yeoul Yun,” A Low-Noise WLAN Mixer Using Switched Biasing Technique,” IEEE Microwave and Wireless Components Letters, vol. 19,pp. 650-652,October 2009.
[7] Dukju Ahn, Dong-Wook Kim, and Songcheol Hong, “A K-Band High-Gain Down-Conversion Mixer in 0.18 m CMOS Technology,” IEEE Microwave and Wireless Components Letters, vol.19, pp.227-229, April 2009.
[8] Chang-Wan Kim, Hae-Won Son, and Bong-Soon Kang, ” A 2.4 GHz Current-Reused CMOS Balun-Mixer,” IEEE Microwave and Wireless
[10] J.C. Guo, C. H. Huang, K. T. Chan, W. Y. Lien, C. M. Wu, and Y. C. Sun, “0.13 μm low voltage logic base RF CMOS technology with 115GHz T f and 80GHz Max f ,” 33rd European Microwave Conference, pp. 682-686, 2003.
[11] N. Talwalkar, C. Yue, and S. wong, “An integrated 5.2GHz CMOS T/R switch with LC-tuned substrate bias,”Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International Page(s):362 - 499 vol.1 [12]M. Ahn, B. S. Kim, C. H. Lee, J. Laskar, “A high power CMOS switch using
substrate body switching in multistaqck structure,” IEEE Microwave and Wireless Components Letters, vol.17, NO.9. pp. 682-684, September 2007 [13] Yalin Jin and Cam Nguyen, “Ultra-compact high-linearity high-power fully
integrated DC-20-GHz 0.18μm CMOS T/R switch, ”IEEE Transactions on Microwave Theory and Techniques, vol. 55, no.1, Jan. 2007
[14] Feng-jung Huang and Kenneth K. O, “Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p-silicon substrates, ”IEEE J.
Solid-State Circuits, vol. 39, no. 1, pp. 35-41, Jan. 2004
[15] M.-C.Yeh, Z.-M. Tsai, R.-C. Liu, K.-Y. Lin, Y.-T. Chang, and H.Wang, “Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance, ”IEEE Trans. Microw. Theory Tech., vol. 54, no.
1, pp. 31-39, Jan. 2006
[16] Q. Li and Y. P. Zhang, “CMOS T/R Switch Design: Towards Ultra-Wideband and High Frequency,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp.563-570, Mar. 2007