Chapter 4 Implementation
4.6 Summary
We have fully implemented the ALU Cluster architecture design by utilizing the current developed CAD tools and cell-based design flow. The maximal clock rate, physical core size, and power dissipation are 100 MHz, 2.16 mm2, and 312 mW, respectively. After having completed the execution of selected benchmark simulation, FIR filter system, the code utilization is 63.4%, and the clock cycles per executed result output is 3.96. The memory capacity of IRF units and SPRF unit are sufficient to provide during the simulation execution, and the ratio of data reference times of on-cluster memory and off-cluster memory is 989 : 91. The higher ratio to the on-cluster memory means that the limited global memory bandwidth is not wasted on the arithmetic units where the ample local memory bandwidth is easy to utilize.
Compare to current related reported works, this work could perform a quite competitive performance while being compared with the application-specific architectures. Besides, this work has better performance compared with the reconfigurable architectures and the FPGA architectures.
Furthermore, the implementation of multiple ALU Clusters design combined with power saving techniques has been developed by several members of SoC Laboratory, and another developed architecture simulator could depend on the required performance to determine the number of ALU Clusters to be executed after the application simulation has been finished. Therefore, the performance of execution time and power dissipation would be scalable depended on requirement.
CHAPTER 5
CONCLUSION
An ALU Cluster design for the media streaming processors architecture has been designed in this thesis. In the meantime, this work has also demonstrated the consideration of implementation feasibility of each component. The back-end simulation results based on the process technology and standard cell library have decided the optimized number and performance of each component. This streaming architecture combined with memory bandwidth hierarchy architecture has efficiently dealt with the selected test bench without wasting too much expensive and communication limited global memory bandwidth on the function units. Additionally, the analysis results of performance evaluation for this work confirm to have the competitiveness and advantages compared with recent relative reported works. Finally, the prototype of this work has been fabricated in UMC 0.18 um 1P6M standard CMOS process technology.
To integrated the developed ALU Cluster with power saving techniques as shown in Figure 4.5.1. The results show that the power dissipation and energy consumption of selected benchmark for the multimedia applications and baseband communication systems could be reduced significantly. Both power dissipation and energy consumption become scalable by dynamic selecting the number of utilized ALU Clusters. The instant performance and energy consumption of an entire work could be optimized for mobile systems. Thus, this design has provided a breakthrough in the operating time and power dissipation in limited battery life for similar architectures. From the above-mentioned results, therefore, the combination of streaming architectures and power saving techniques have been the main stream for the design of next generation portable multimedia and communication systems as depicted in Figure 4.5.5.
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APPENDIX A
SUMMARY OF THE DEFINED MICROCODE IN INSTRUCTION SET
I. The part of “SOURCE” in instruction set format
Source Register Binary Code [1:0]
None operation 00 b
Off-chip data memory (DM) 11 b
SPRF (SP) 10 b
IRF (RF) 11 b
II. The part of “DESTINATION” in instruction set format
Destination Register Binary Code [3:0]
None operation 0000 b
Off-chip data memory (DM) 0001 b
SPRF (SP) 0010 b
Left IRF of ALU_0 (I9) 0011 b
Right IRF of ALU_0 (I8) 0100 b
Left IRF of ALU_1 (I7) 0101 b
Right IRF of ALU_1 (I6) 0110 b
Left IRF of MUL_0 (I5) 0111 b
Right IRF of MUL_0 (I4) 1000 b
Left IRF of MUL_1 (I3) 1001 b
Right IRF of MUL_1 (I2) 1010 b
Left IRF of DIV_0 (I1) 1011 b
Right IRF of DIV_0 (I0) 1100 b
III. The part of “OPERATION CODE” in instruction set format
Function Unit Operation OP code
None 0000 b
ADD 0001 b
SUB 0010 b
ABS 0011 b
AND 0100 b
OR 0101 b
XOR 0110 b
NOT 0111 b
SLL 1000 b
SRL 1001 b
SRA 1010 b
LT 1011 b
GT 1100 b
ALU
EQ 1101 b
None 0 b
MUL MUL 1 b
None 00 b
DIV 01 b
REM 10 b
DIV
SQR 11 b
APPENDIX B
9 RF_00_RF_00_DM_00_ADD DM_12_DM_02_I6_05_MUL DM_13_DM_03_I7_06_MUL
10 RF_00_RF_00_SP_00_ADD DM_14_DM_04_I6_06_MUL DM_15_DM_05_I7_07_MUL
11 RF_01_RF_01_I9_02_ADD DM_16_DM_06_I6_07_MUL DM_10_DM_01_I7_08_MUL
12 RF_02_RF_02_I8_02_ADD DM_11_DM_02_I6_08_MUL DM_12_DM_03_I7_09_MUL
13 RF_03_RF_03_I9_03_ADD DM_13_DM_04_I6_09_MUL DM_14_DM_05_I7_10_MUL
14 RF_04_RF_04_I8_00_ADD DM_15_DM_06_I6_10_MUL DM_16_DM_07_I9_00_MUL
15 RF_01_SP_00_DM_01_ADD DM_09_DM_01_I7_00_MUL DM_10_DM_02_I6_00_MUL
16 RF_05_RF_05_I8_03_ADD DM_11_DM_03_I7_01_MUL DM_12_DM_04_I6_01_MUL
17 RF_02_RF_02_DM_02_ADD RF_06_RF_06_I9_04_ADD DM_13_DM_05_I7_02_MUL DM_14_DM_06_I6_02_MUL
18 RF_03_RF_01_I9_05_ADD RF_07_RF_07_I8_04_ADD DM_15_DM_07_I7_03_MUL DM_16_DM_08_I6_03_MUL
19 RF_08_RF_08_I8_05_ADD DM_08_DM_01_I7_04_MUL DM_09_DM_02_I6_04_MUL
20 RF_09_RF_09_I9_01_ADD DM_10_DM_03_I7_11_MUL DM_11_DM_04_I6_11_MUL
21 RF_10_RF_10_I8_06_ADD DM_12_DM_05_I7_05_MUL DM_13_DM_06_I6_05_MUL
22 RF_04_RF_03_I9_06_ADD RF_00_RF_00_I8_07_ADD DM_14_DM_07_I7_06_MUL DM_15_DM_08_I6_06_MUL
23 RF_05_RF_00_DM_03_ADD RF_01_RF_01_I9_02_ADD DM_16_DM_09_I8_01_MUL DM_07_DM_01_I7_07_MUL
24 RF_00_RF_05_I9_03_ADD RF_02_RF_02_I8_02_ADD DM_08_DM_02_I6_07_MUL DM_09_DM_03_I7_08_MUL
25 RF_03_RF_03_I9_07_ADD DM_10_DM_04_I6_08_MUL DM_11_DM_05_I7_09_MUL
26 RF_01_RF_06_I8_08_ADD RF_04_RF_04_I9_08_ADD DM_12_DM_06_I6_09_MUL DM_13_DM_07_I7_10_MUL
27 RF_06_RF_04_DM_04_ADD RF_11_RF_11_I8_03_ADD DM_14_DM_08_I6_10_MUL DM_15_DM_09_I7_00_MUL
28 RF_02_RF_07_I8_00_ADD RF_05_RF_05_I9_04_ADD DM_16_DM_10_I6_00_MUL DM_06_DM_01_I7_01_MUL
29 RF_06_RF_06_I8_05_ADD DM_07_DM_02_I6_01_MUL DM_08_DM_03_I7_02_MUL
30 RF_07_RF_02_I9_00_ADD DM_09_DM_04_I6_02_MUL DM_10_DM_05_I7_03_MUL
31 RF_08_RF_01_I9_01_ADD RF_07_RF_07_I8_06_ADD DM_11_DM_06_I6_03_MUL DM_12_DM_07_I7_04_MUL
32 RF_03_RF_08_DM_05_ADD RF_08_RF_08_I9_05_ADD DM_13_DM_08_I6_04_MUL DM_14_DM_09_I7_11_MUL
33 RF_04_RF_03_I9_02_ADD RF_09_RF_09_I8_04_ADD DM_15_DM_10_I6_11_MUL DM_05_DM_01_I7_05_MUL
34 RF_10_RF_10_I9_06_ADD DM_06_DM_02_I6_05_MUL DM_07_DM_03_I7_06_MUL
35 RF_00_RF_00_DM_06_ADD RF_00_RF_00_I8_02_ADD DM_08_DM_04_I6_06_MUL DM_09_DM_05_I7_12_MUL
36 RF_01_RF_05_I8_01_ADD RF_01_RF_01_I9_07_ADD DM_10_DM_06_I6_12_MUL DM_11_DM_07_I7_07_MUL
37 RF_05_RF_06_I9_03_ADD RF_02_RF_02_I8_07_ADD DM_12_DM_08_I6_07_MUL DM_13_DM_09_I7_08_MUL
38 RF_03_RF_03_I9_04_ADD DM_14_DM_10_I6_08_MUL DM_04_DM_01_I7_09_MUL
39 RF_06_RF_04_I9_08_ADD RF_04_RF_04_I8_03_ADD DM_05_DM_02_I6_09_MUL DM_06_DM_03_I7_10_MUL
40 RF_11_RF_11_I8_00_ADD DM_07_DM_04_I6_10_MUL DM_08_DM_05_I7_00_MUL
41 RF_02_RF_01_DM_07_ADD RF_05_RF_05_I9_00_ADD DM_09_DM_06_I6_00_MUL DM_10_DM_07_I7_01_MUL
42 RF_03_RF_02_SP_00_ADD RF_06_RF_06_I8_05_ADD DM_11_DM_08_I6_01_MUL DM_12_DM_09_I7_02_MUL
43 RF_07_RF_07_I9_01_ADD RF_12_RF_12_I8_06_ADD DM_13_DM_10_I6_02_MUL DM_03_DM_01_I7_03_MUL
44 RF_04_RF_03_I8_04_ADD RF_07_RF_07_I9_05_ADD DM_04_DM_02_I6_03_MUL DM_05_DM_03_I7_04_MUL
45 RF_08_RF_08_I9_06_ADD DM_06_DM_04_I6_04_MUL DM_07_DM_05_I7_11_MUL
46 RF_09_RF_09_I9_02_ADD DM_08_DM_06_I6_11_MUL DM_09_DM_07_I7_05_MUL
47 RF_08_SP_00_DM_08_ADD RF_10_RF_10_I8_01_ADD DM_10_DM_08_I6_05_MUL DM_11_DM_09_I7_06_MUL
48 RF_01_RF_00_I9_03_ADD RF_00_RF_00_I8_02_ADD DM_12_DM_10_I6_06_MUL DM_02_DM_01_I7_12_MUL
49 RF_00_RF_05_I8_03_ADD RF_01_RF_01_I9_04_ADD DM_03_DM_02_I6_12_MUL DM_04_DM_03_I7_07_MUL
50 RF_05_RF_06_I8_07_ADD RF_02_RF_02_I9_07_ADD DM_05_DM_04_I6_07_MUL DM_06_DM_05_I7_08_MUL
51 RF_03_RF_03_I9_09_ADD DM_07_DM_06_I6_08_MUL DM_08_DM_07_I7_09_MUL
52 RF_02_RF_01_I9_08_ADD RF_04_RF_04_I8_08_ADD DM_09_DM_08_I6_09_MUL DM_10_DM_09_I7_10_MUL
53 RF_03_RF_04_DM_09_ADD RF_11_RF_11_I9_01_ADD DM_11_DM_10_I6_10_MUL DM_01_DM_01_I7_00_MUL
54 RF_06_RF_03_I9_00_ADD RF_05_RF_05_I8_00_ADD DM_02_DM_02_I6_00_MUL DM_03_DM_03_I7_01_MUL
55 RF_04_RF_02_I8_05_ADD RF_06_RF_06_I9_05_ADD DM_04_DM_04_I6_01_MUL DM_05_DM_05_I7_02_MUL
56 RF_12_RF_12_I8_06_ADD DM_06_DM_06_I6_02_MUL DM_07_DM_07_I7_03_MUL
57 RF_09_RF_08_I8_01_ADD RF_07_RF_07_I9_02_ADD DM_08_DM_08_I6_03_MUL DM_09_DM_09_I7_04_MUL
58 RF_08_RF_08_I8_04_ADD DM_10_DM_10_I6_04_MUL DM_01_DM_02_I7_11_MUL
59 RF_00_RF_07_DM_10_ADD RF_09_RF_09_I9_03_ADD DM_02_DM_03_I6_11_MUL DM_03_DM_04_I7_05_MUL
60 RF_07_RF_05_I8_02_ADD RF_10_RF_10_I9_04_ADD DM_04_DM_05_I6_05_MUL DM_05_DM_06_I7_06_MUL
61 RF_01_RF_00_I8_03_ADD RF_00_RF_00_I9_06_ADD DM_06_DM_07_I6_06_MUL DM_07_DM_08_I7_12_MUL
62 RF_05_RF_01_I9_09_ADD RF_01_RF_01_I8_09_ADD DM_08_DM_09_I6_12_MUL DM_09_DM_10_I8_08_MUL
63 RF_02_RF_06_I8_10_ADD RF_02_RF_02_I9_10_ADD DM_01_DM_03_I7_07_MUL DM_02_DM_04_I6_07_MUL
64 RF_03_RF_04_I9_00_ADD RF_03_RF_03_SP_00_ADD DM_03_DM_05_I7_08_MUL DM_04_DM_06_I6_08_MUL
65 RF_08_RF_02_DM_11_ADD RF_04_RF_04_I9_07_ADD DM_05_DM_07_I7_09_MUL DM_06_DM_08_I6_09_MUL
66 RF_11_RF_11_I8_00_ADD DM_01_DM_04_I7_10_MUL DM_02_DM_05_I6_10_MUL
67 RF_09_RF_03_DM_12_ADD RF_05_RF_05_I9_01_ADD DM_03_DM_06_I7_00_MUL DM_04_DM_07_I6_00_MUL
68 RF_04_RF_10_I8_01_ADD RF_06_RF_06_I9_02_ADD DM_05_DM_08_I7_01_MUL DM_06_DM_09_I6_01_MUL
69 RF_06_RF_09_I8_04_ADD RF_12_RF_12_SP_01_ADD DM_07_DM_10_I9_03_MUL DM_01_DM_05_I7_02_MUL
70 RF_10_SP_00_I9_05_ADD RF_07_RF_07_I8_02_ADD DM_02_DM_06_I6_02_MUL DM_03_DM_07_I7_03_MUL
71 RF_08_RF_08_SP_02_ADD DM_04_DM_08_I6_03_MUL DM_05_DM_09_I7_04_MUL
72 RF_01_RF_00_I9_08_ADD RF_09_RF_09_I8_03_ADD DM_06_DM_10_I6_04_MUL DM_01_DM_06_I7_05_MUL
73 RF_00_RF_01_DM_13_ADD RF_10_RF_10_I8_05_ADD DM_02_DM_07_I6_05_MUL DM_03_DM_08_I7_06_MUL
74 RF_07_RF_04_I8_07_ADD RF_00_RF_00_I9_04_ADD DM_04_DM_09_I6_06_MUL DM_05_DM_10_I8_06_MUL
75 RF_02_SP_01_I9_06_ADD RF_01_RF_01_I8_09_ADD DM_01_DM_07_I7_07_MUL DM_02_DM_08_I6_07_MUL
76 SP_02_RF_02_I9_09_ADD DM_03_DM_09_I7_08_MUL DM_04_DM_10_I6_08_MUL
77 RF_02_RF_02_I8_00_ADD DM_01_DM_08_I7_09_MUL DM_02_DM_09_I6_09_MUL
78 RF_03_RF_05_I8_01_ADD RF_03_RF_03_I9_01_ADD DM_03_DM_10_I6_11_MUL DM_01_DM_09_I7_10_MUL
79 RF_05_RF_07_DM_14_ADD RF_04_RF_04_I8_04_ADD DM_02_DM_10_I6_10_MUL DM_01_DM_10_DM_20_MUL
80 RF_08_RF_08_I8_10_ADD RF_05_RF_05_SP_00_ADD DM_07_DM_09_I7_30_MUL DM_08_DM_10_I6_30_MUL
81 RF_04_RF_09_I9_02_ADD RF_06_RF_06_I8_02_ADD
82 RF_09_RF_03_SP_63_ADD RF_07_RF_07_I9_07_ADD
83 RF_01_RF_00_I9_03_ADD RF_08_RF_08_I8_05_ADD
84 RF_09_RF_09_I7_00_ADD
85 RF_06_RF_10_DM_15_ADD
86 SP_00_RF_06_I9_00_ADD
87 RF_10_RF_10_DM_01_ADD
88 RF_03_RF_04_DM_18_ADD RF_30_RF_30_I8_31_ADD
89 RF_07_RF_05_DM_20_ADD RF_00_RF_11_DM_00_ADD
90 RF_02_RF_01_DM_17_ADD
91 RF_00_RF_02_DM_19_ADD
92
93 SP_63_RF_31_DM_16_ADD