ALU, MUL, DIV

In this section, how to design the functional unit shall be depicted. Since the main spirits for designing ALU, MUL, and DIV are basically the same, we shall focus on ALU to illustrate how to design functional unit. The only difference between these three components is the bit of “Opcode” needed for expressing the operation in the instruction format.

ALU

ALU is a two stage pipeline computation unit. Figure 3.5 shows the instruction format of ALU. The shadowed part in figure is Opcode field, which expresses the executing operation for instruction. Opcode also makes the biggest difference between these three functional units: ALU, MUL, and DIV. Please note that ALU requires more diverse operations. It demands 4-bits to express.

Figure 3.5 ALU instruction format

Figure 3.6 is the detail view of the functional unit and its associated register files.

Roughly, it could be cataloged into three parts: data read, calculate, and write back.

READ

Figure 3.6 Detail of the functional unit

Data Read As shown in Figure 3.6, the two MUXs in data input will judge the source data from the field, ”LRF0 Source”, in the instruction format. Table 3.1 shows binary code and the corresponding source data. The origins of source data are SRF, SP, and LRF, respectively. The desired data1 can be found in the memory location represented by ”LRF0 RD ADDR”. The way to find data2 is basically the same as data1. The only difference is their reference fields. Acquiring data2 needs to take references of the information of ”LRF1 Source” and ”LRF1 RD ADDR”.

Figure3.7 illustrates the program flow of how ALU in the simulator obtains two data resources, data1 and data2, according to the information of instruction.

LRF 0

allocation ”K” according to the

“LRF0 RD ADDR” field }

Find_data1(int K, int clusterx, int FUx) {

according to the “LRF0 Source” field 00 do nothing

allocation ”K” according to the

“LRF1 RD ADDR” field }

Find_data2(int K, int clusterx, int FUx) {

according to the “LRF1 Source” field 00 do nothing

Figure 3.7 Finding source data of ALU

Table 3.1 Lookup table of the data source

Calculate The information describing what kind of operations is required to be execute by every instruction will be implicitly included in the final field “Opcode” of instruction. Different binary codes represent distinct operations. Table 3.3 shows the lookup table for opcodes and corresponding operations. Matching the instruction with those bits of opcode filed in the instruction format would know what kind of operation is required for specific instruction.

Table 3.3 Kernel ISA of ALU unit

EQ

Write Back The computation results of the functional unit will determine the destination of write back through one MUX, including SRF, SP, and LRF. Write back to LRF is classified into two kinds. If the results have to write back to the same LRF of functional unit, it should be written back to LRF-0 (LRF0_FU-1). On the other hand, if the result have to write to other LRFs of functional unit, it should be written to LRF-1 (LRF1_FU-2, LRF1_FU-3, LRF1_FU-4, LRF1_FU-5). MUX determines the destination of write back according to the information in the field

“DEST” of the instruction, and finds out the memory location of the write back from the field ”WB ADDR”. Table 3.2 shows the corresponding binary code and register of DEST. Figure 3.8 illustrates the write-back step of programming process, and Figure 3.9 illustrates the flow of programming process in ALU Unit.

Figure 3.8 Result write back of ALU

Table 3.2 Look up table of the data write back destination of FU-1

Find_WBDDR()

Writeback(int K, int clusterx, int FUx) {

according to the “DEST” field 000 do nothing to the “LRF0 RD ADDR”

field }

Find_data1(int K, int clusterx, int FUx) {

according to the “LRF0 Source” field 00 do nothing to the “LRF1 RD ADDR”

field }

Find_data2(int K, int clusterx, int FUx) {

according to the “LRF1 Source” field 00 do nothing

Figure 3.9 Block diagram of the ALU unit MUL

MUL is a four-stage pipeline computation unit. The way MUL Unit deal with instruction is the same as that of ALU. The only difference is that MUL Unit just deal with one operation “multiple”. Therefore, only one-bit is required for “Opcode”

filed in the instruction format and the instruction length of MUL Unit is three-bit less than that of ALU Unit. Please not that the processing flow of ALU Unit in Figure 3.9 can be also applied to MUL Unit. However, in the third step, calculate, the opcode must be referred to the corresponding operation shown in Table 3.4.

Table 3.4 Kernel ISA of MUL unit

MUL

DIV is a six stage pipeline computation unit. Again, the way DIV Unit treats instruction is the same as that of ALU. The only difference lies in the operations executed by DIV Unit and ALU Unit. The operations which DIV Unit deal with are ”division”, “remainder”, and “exponent”, respectively. Therefore, only two-bit are required for “Opcode” field in instruction format expressing these three distinct operations. It follows that the instruction length of DIV Unit is two bit less than that of ALU Unit. The programming flow of ALU Unit in Figure 3.9 can then be applied again to DIV Unit except that the reference opcode in the third step, calculate, must take the reference of Table 3.5 to see the corresponding operation.

Table 3.5 Kernel ISA of DIV unit

SQR