ECO for Changing Routing Layout
4.1 An Incremental Algorithm for Updating the Solution
Here we present an incremental algorithm which updating the solution of the redun-dant via insertion problem after a single via is added or removed. When a single via is added or removed, its feasible via should be added into the directed conflict graph or its feasible via should be removed from directed conflict graph. Hence, there may exist some single vias or feasible vias which are affected after adding(removing) single vias or feasible vias. We find the affected set in our directed conflict graph first and then update the maximum number of double-cut vias during this set later.
When a single via Vi is added (removed), we put the single via and its feasible via into the work set, which is for finding the affected vias. Then finding the affected single vias and feasible vias from the work set in our directed conflict graph, and also put the affected single vias and feasible vias into work set and affected set which contains all the affected vias. If there is no affected single vias and feasible vias, we chalk up the maximum number S1 of redundant via insertion problem among these affected single vias. Later, we update the directed conflict graph by adding(removing) the single via Vi and its related feasible vias, and use MCMF to get the new solution S2 of redundant via insertion problem among these affected vias. Therefore, the difference between S1 and S2is the update solution of redundant via insertion problem after ECO-design. The incremental algorithm is summarized in Figure 4.1.
Let us now analyze the complexity of finding the affected vias. The loop in lines 2-15 of our incremental algorithm performs exactly |AFFECTED| iterations.
The iteration corresponding to vertex x takes O|Find(x)| time in case of our in-cremental algorithm. Therefore, the running time of finding the affected vias are O(P
x∈AF F ECT ED | F ind(x) |).
Figure 4.1: Overview of the incremental algorithm for update the redundant via insertion porblem.
Chapter 5
Experimental Results
We implemented our approach in the C++ Programming language and the platform is on Linux based machine with two CPUs and 14GB memory.
The set of test cases we used is from [8]. Table 5.1 shows the detail information of the set of test cases; for each test case, the first column gives the test circuit name,
”Size(µm)” shows the layout dimension, ”#Nets” gives the number of nets, ”#I/Os”
shows the number of pins, ”#Vias” gives the total number of single vias, ”#D-Vias”
shows the number of single vias each of which has at least one feasible double-cut via, and ”#Layers” gives the number of metal layers used. Finally, ”#Objects”
gives the total number of layout objects including pins, vias, blockages and wire segments.
Table 5.1: The information of five test cases [8].
Case Size(µm) #Nets #I/Os #Vias #D-Vias #Layers #Objects
C1 350.000*350.000 4309 20 24594 17522 5 218215
C2 419.433*413.28 5252 211 41157 28591 5 268669
C3 799.124*776.16 18157 85 127059 91727 5 933852
C4 691.272*680.400 17692 415 151912 102347 5 943073
C5 1383.482*1375.92 44720 99 357386 255301 5 2851612
We used conflict graph [8] as our input file for each test case and the static about
the conflict graph are shown in Table 5.2. ”#Nodes” gives the number of nodes in the conflict graph (i.e., the number of feasible double-cut vias) and ”#Edges” shows the number of conflict edges.
Table 5.2: Statistics on conflict graphs.
Case #Nodes #Edges
We break the conflict graph into two sets: double vias set and conflict set. Then we constructed our directed conflict graph from conflict set of each case. Table 5.3 shows the related results. ”#D-CUT” shows the number of single vias each of which has at least one redundant via location without any conflict with oth-ers, ”#D Nodes” gives the number of the nodes in our directed conflict graph,
”#D Edges” shows the number of solid edges and green edges, and ”#Red Edges”
gives the number of red edges in out directed conflict graph. Finally, ”CPU1(s)”
shows the related execution time. We can find that the sizes including nodes and edges of our directed conflict graphs are very small; therefore, it is very good for the multi-core/parallel computation.
Table 5.3: Statistics on directed conflict graphs.
Case #D-CUT #D Nodes #D Edges #Red Edges CPU1(s)
C1 17396 256 382 2 0.88
C2 28414 361 541 4 1.61
C3 91152 1177 1775 16 6.10
C4 101108 2515 3787 53 14.36
C5 253440 3806 5747 45 16.92
We compare our directed conflict graph algorithm with H2K algorithm proposed
in [8]. The results are shown in Table 5.4. In the table, ”CPU2(s)” gives the execution time for running minimum cost maximum flow, ”#R-Vias” shows the number of double-cut vias found from directed conflict graph after running minimum cost maximum flow, ”#D-Total” gives the number of total double-cut vias from the original design, and ”Rate(O)” is equal to ”#D-Total” divided by ”#D-Vias”
shown in Table 5.1. ”H2K” shows the number of inserted double-cut vias by H2K,
”Rate(H2K)” is equal to ”H2K” divided by ”#D-Vias”.
Table 5.4: The experimental results on test cases: Comparison for post-routing redundant via insertion with H2K [8]. We insert more redundant vias than H2K on C4 circuit.
Case CPU2(s) #R-Vias #D-Total Rate(O) H2K Rate(H2K)
C1 0.02 65 17461 99.65% 17461 99.65%
C2 0.03 93 28507 98.13% 28507 98.13%
C3 0.05 309 91461 99.71% 91461 99.71%
C4 0.11 658 101766 99.43% 101765 99.43%
C5 0.42 988 254428 99.66% 254428 99.66%
From Table 5.4, we can see that our algorithm inserts more redundant vias than H2K on C4 circuit, and inserts the same number of redundant vias on the other circuits. So our algorithm is a better solution to find the optimal solution.
And From Table 5.5, our algorithm also works very fast. We also list the CPU time of H2K [8] including the time spent by graph construction for reference. [8]
implemented H2K in C++ language running on a Linux based machine with 2.4G processor and 2GB memory.
Table 5.6 shows the timing compare between full process and incremental al-gorithm after ECO-design on C5 circuit. ”#Changes” represents the number of changes after ECO-design, ”#E-Total” gives the number of total double-cut vias after ECO-design, ”CPUF(s)” represents the total runtime includes directed graph construction and MCMF after ECO-design to solve the redundant via insertion
prob-Table 5.5: CPU time of our algorithm and H2K [8] from different platform. Our input file is the conflict graph from [8] and their input file is the layout solution.
Case Total Run time: CPU1(s)+CPU2(s) CPU(s) H2K
C1 0.88 32
C2 1.64 43
C3 6.15 192
C4 14.47 203
C5 17.34 710
lem, and ”CPUI(s)” gives the runtime of incremental algorithm includes finding the affected set and MCMF to update the solution of the redundant via insertion after ECO-design. On average, our incremental algorithm obtains 24X runtime speedup.
Table 5.6: The timing comparison between full process and incremental algorithm after ECO-design on C5 circuit. CPUF(s) represents the total runtime includes directed graph construction and MCMF after ECO-design to solve the redundant via insertion problem. CPUI(s) gives the runtime of incremental algorithm includes finding the affected set and MCMF to update the solution of the redundant via insertion after ECO-design.
Chapter 6 Conclusion
In this thesis, we propose a graph construction algorithm to solve the redundant via insertion problem to reach a higher rate for improving the manufacturing yield. First we use our graph construction algorithm to construct the directed conflict graph from the given routing result to consider all the vias of a design simultaneously. Then we use minimum cost maximum flow to find the maximum number of redundant vias from the directed conflict graph. Experimental results show that our algorithm can get almost optimal solution for improving the redundant via insertion rate in polynomial time. In addition, after ECO for the whole design, we can efficiently update the solution by incremental algorithm. The experimental results show it is very efficient for updating the optimal solution.
Bibliography
[1] “Taiwan Semiconductor Manufacturing Company (TSMC)”. In Referecne Flow 5.0 and Reference Flow 6.0.
[2] D. Abercrombie. “Via Doubling Can Help to Stem Yield Loss”. In EE Times, Oct. 2005.
[3] G. A. Allan. “Targeted Layout Modifications for Semiconductor Yield/Reliability Enhancement”. In IEEE Transactions on Semiconductor Manufacturing, volume 17, pages 573–581, Nov. 2004.
[4] H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han. “Novel Full-Chip Gridless Routing Considering Double-Via Insertion”. In Proc. of Design Automation Conference, pages 755–760, 2006.
[5] C. Christiansen, B. Li, J. Gill, R. Filippi, and M. Angyal. “Via-Depletion Electromigration in Copper Interconnects”. In IEEE Transactions on Device and Materials Reliability, volume 6, pages 163–168, Jun. 2006.
[6] S. Kumra and P. Gupta. “An Incremental Algorithm for the Maximum Flow Problem”. In Proc. of Journal of Mathematical Modelling and Algorithms, volume 2, pages 1–16, 2003.
[7] K.-Y. Lee and T.-C. Wang. “Post-Routing Redundant Via Insertion and Line End Extension with Via Density Consideration”. In Proc. of ICCAD, pages 633–640, 2006.
[8] K.-Y. Lee and T.-C. Wang. “Post-Routing Redundant Via Insertion for Yield/Reliability Improvement”. In Proc. of ASPDAC, pages 303–308, 2006.
[9] F. Luo, Y. Jia, and W.-M. Dai. “Yield-Preferred Via Insertion Based on Novel Geotopological Technology”. In Proc. of ASPDAC, pages 730–735, 2006.
[10] T. Pompl, C. Schlunder, M. Hommel adn H. Nielen, and J. Schneider. “Practical Aspects of Reliability Analysis for IC Designs”. In Proc. of Design Automation Conference, pages 193–198, 2006.
[11] S. Raghvendra and P. Hurat. “DFM: Linking Design and Manufacturing”. In Proc. of the International Conference on VLSI Design, pages 705–708, 2005.
[12] L. K. Scheffer. “Physical CAD Changes to Incorporate Design for Lithography and Manufacturability”. In Proc. of ASPDAC, pages 768–773. Jan. 2004.
[13] J. G. Xi. “Improving Yield in RTL-to-GDSII Flows”. In EE Times, Jul. 2005.
[14] G. Xu, L.-D. Huang, D. Z. Pan, and M. D. F. Wong. “Redundant-Via Enhanced Maze Routing for Yield Improvement”. In Proc. of ASPDAC, volume 2, pages 1148–1151, Jan. 2005.
[15] H. Yao, Y. Cai, X. Hong, and Q. Zhou. “Improved Multilevel Routing with Redundant Via Placement for Yield and Reliability”. In Proc. of Great Lakes Symposium on VLSI, pages 143–146, 2005.
[16] Y. Zorian, D. Gizopoulos, C. Vandenberg, and P. Magarshack. “Guest Editors’
Introduction: Design for Yield and Reliability”. In IEEE Trans on Design &
Test of Computers, volume 21, pages 177–182, May. 2004.