The measurement presented in section 2-2.3 was used to extract lateral distribution of interface trap state. It should be noted that the local Vth and Vfb, across the MOSFET, are not uniform due to the lateral doping variation as shown in figure 3.18. In order to detect the interface states, the voltage pulses applied during measurements must
undergo alternate accumulation and inversion cycles. Therefore, there should be no Icp as the high-level voltage (Vh) is lower than the minimum Vth under the gate. Only after Vh starts to exceed the local Vth in the channel will Icp begin to grow. Before Vh reaches the maximum local Vth in the channel, only interface states residing near the drain side will contribute to Icp, as the needed electrons cannot yet flow to the drain side from the source.
We choose the control sample for an example. If we assume that the interface state density is spatially uniform along the channel, which can be written as
,max
cp it
I =q f N W L (3-1) where f is the gate pulse frequency, W is the channel width, and L is the channel length.
Because Vth is not uniformly distributed, when Vh reaches the maximum local Vth in the channel, only interface states residing near the drain side (i.e., the shadow region in figure 3.18) will contribute to Icp. In figure 3.19, the corresponding Icp (Vh) comes from the interface state distributed in the region between the gate edge and the position where its local Vth equals Vh, i.e.,
( )
cp h it
I V =q f N W x (3-2) where x represents the distance from the gate edge to the position where Vth (x) = Vh. Comparing (3-1) and (3-2), we can derive
( )
Figure 3.20 shows the local Vth versus distance x of the control sample. The local Vth
decreases sharply as x is smaller than 0.07 µm. We can presume that the drain junction is near x = 0.07 µm.
After subjecting to 10 second of hot carrier stress (VG@Isubmax and VDS = 4.5 V), the incremental charge pumping current (∆Icp), as shown in Fig. 3.21, at a given Vh, is
proportional to the number of generated interface traps from the gate edge to the point x. Therefore, the Nit(x) generated by the hot carrier stress can be expressed as follows:
( )
1 1The relationship of dVh
dx versus x can be derived from Vh versus x, so the lateral distribution, Nit (x), could be obtained from the procedure mentioned above.
By the same procedure, the derived lateral profiles of the interface states for all splits of devices could be extracted by Eq. (3-5), and the results are shown in figure 3.22.
From this figure we can directly calculate the damage region and the amount of interface states generated by the hot-carrier stress. We can see that the damage region is confined within the drain edge in all splits. This is reasonable since the hot-carrier effect is localized. It is obviously seen that interface state generation sharply increases in SiN-capped samples near the drain region, and the SiN-removal samples also show larger degradation than the control counterparts, even though the channel strain has been eliminated in these devices. These results are consistent with those mentioned above in section 3-2. In short, channel strain is responsible for the gravest hot carrier degradation observed in SiN-capped samples, while hydrogen species piled up at the source/drain edge during the SiN deposition is responsible for the slightly larger interface state generation in the SiN-removal devices over the control devices.
Chapter 4 Summary and Conclusion
In this thesis, the effects of LPCVD SiN process and the channel strain induced by the SiN-capping layer on the device characteristics and hot-electron degradation were investigated. Several important phenomena were observed and summarized as follows.
First, the channel strain induced by the SiN capping layer over the gate greatly boosts the drive current of short-channel devices. For example, enhancement ratio up to 20 % is achieved for the device with 300nm SiN-capping layer at a channel length of 0.4 µm. The SiN-removal devices show slightly higher Gm than the control sample owing to the passivation of the hydrogen species during the deposition process. Thermal budget associated with the deposition of the SiN capping layer could alleviate the reverse short-channel effect of the uncapped devices. Moreover, the bandgap narrowing effect due to the channel strain may result in further lowering in Vth as the channel length is shortened.
Secondly, hot-electron degradation is adversely affected when the SiN is deposited over the gate, even if the channel strain is relieved by subsequent SiN removal. The accompanying bandgap narrowing and the increased carrier mobility tend to worsen the hot-electron reliability in the SiN-capped devices. However, the hot carrier degradation of devices with SiN capping is independent of SiN thickness due to bandgap narrowing.
Finally, enhanced edge effect caused by the hot carrier stress is also observed in SiN-removal devices.
In this work, additional thermal budget and hydrogen species are the two prime culprits for aggravated reliabilities in strained devices. Optimization of both SiN deposition process and the film properties are thus essential for the implementation of the uniaxial strain in NMOS devices.
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Figures
Fig.1.1 Logical potential solution on International Technology Roadmap for Semiconductors. (a) From Process Integration, Devices, and Structure in 2003 [4]. (b) From Process Integration, Devices, and Structure in 2005 [5].