Analysis of Phase Noise by Linear Time Varying Method (A) Linear Time Varying Analysis on Phase Noise (A) Linear Time Varying Analysis on Phase Noise

Recently, another analysis on the phase noise prediction with linear time-varying is developed [34.35.45]. This method describes a input impulse current which is injected into the circuit. It will have a phase difference to form the phase noise, except for the peak point. Fig. 4.21 shows the process with block diagram of linear time-varying analysis. The unit inpulse response for excess phase can be expressed as

where qmax is the maximum charge displacement across the capacitor on the node and

∫

^t−∞ cos

_[

ω0t+φ

_{( )}

t

_]

Fig. 4.21 Blook diagram of linear time-varying analysis

u(t) is the unit step. Γ(x) is called the impulse sensitivity function (ISF). Γ(x) is a function of the periodic waveform; and represents the phase variation by ISF in time τ.

Given the ISF, the output excess phase Φ(t) can be calculated using superposition

where i(τ) represents the input noise current injected into the node of interest.

The phase variation may be viewed as signal by phase modulation which transforms phase to voltage in Fig.4.21. The output voltage can be expressed by

[ ( )^t ] ( ^t) [ ( )^t ] ( ^t) ( )^t

Cos ω₀+Φ =cos ω₀ cos Φ −sin ω₀ sinΦ

( ) ( ) ( )

0^{t t} sin 0^t

cosω −Φ ω

≈ (4.28)

For a single-tone phase modulation for output voltage, the sideband power relative to the carrier is given by

( )

²

The total single sideband phase noise spectral density in dB below the carrier per unit bandwidth due to the source on one node at an offset frequency of ∆ω is given by



(B) Flicker Noise of the Device

For the purpose of prediction on phase noise, the flicker noise of the devices has been measured by way of equipment BTA 9603 FET Noise Analyzer. Two NMOS and one PMOS devices were measured separatedly under bias voltage at |Vgs|=0.8, 1, 1.3V and |V_ds|=0.8, 1, 1.3V. The mean value of the MOS flicker noise can be process parameter and expressed by the following :

ox more difference under different voltage Vgs which is shown in Fig. 4.23. The flicker noise of PMOS is smaller than NMOS at the bias Vgs=Vds=1V, which also shown in the Fig. 4.24. Table4.3 shown the device size, bias voltage and extracted parameter with Kf and α. The value Kf of NMOS is larger than PMOS about six times. The value α of NMOS is about 0.87~0.94 and PMOS is 1~1.2, respectively[50].

Fig. 4.22 Measurement of NMOS flicker noise with different Vds under Vgs=1V

Fig. 4.23 Measurement of NMOS flicker noise with different Vgs under Vds=1V

Table 4.3 Extracted value of Kf and α of flicker noise

Size | Vgs | | Vds | Gm Kf α

0.8 1 26m 1.7e⁻²⁴ 0.88

1 1 37m 1.7e⁻²⁴ 0.88

NMOS1 L=0.35um W=5um

M=60 1.3 1 44m 1.5e⁻²⁴ 0.87

0.8 1 18m 2.2e⁻²⁴ 0.9

1 1 26m 1.9e⁻²⁴ 0.89

NMOS2 L=0.35um W=5um

M=40 1.3 1 31m 2.6e⁻²⁴ 0.94

0.8 1 7.8m 2.2e⁻²⁵ 0.98

1 1 19m 3.5e⁻²⁵ 1.19

PMOS1 L=0.35um W=5um

M=120 1.3 1 30m 4e⁻²⁵ 1.17

(C) Phase Noise Prediction of VCO

The excess noise multiplication factor F of the Leeson’s model is determined by

the experimental data fit. It gives no further information on the prediction of the phase noise for the circuit designer. The phase noise calculated by impulse sensitivity function (ISF) is a new method which proposed in Ref. [45.46.47]. This method is based on time-variant model makes explicit predictions of relationship between waveform shape and 1/f noise up-conversion. It also introduces a general method to calculated the phase noise with multiple noise source including the flicker noise induced by the nonlinear mixing mechanism with the simple relation the

sideband power due to an arbitrary source. The phase noise included the effect of account, the phase noise can be modified into the following :

{ }

sensitivity function (ISF) in time-variant model is periodic and can be expanded in a Fourier series:

The coefficients satisfy the relation:

∑

^∞₌ ⁼

∫

^Γ

( )

^{= Γ}

The corner frequency in oscillator is closely related to low corner frequency and is

Fig. 4.24 MOSFET flicker noise

4.24. The corner frequency fc is the intersection point between the

1f noise and thermal noise, which generally depends on device dimensions and bias current. The mean square 1/f MOSFET drain noise current per unit bandwidth is given by [4]:

f per unit bandwidth is given as [4]:

gm

K (NMOS)=4e-24. The results reveal that PMOS devices have less 1/f noise than fn

NMOS transistors. From thermal noise measurement with NF=1.5 for device gm=60m, frequency=300 MHz (not shown ) results in that γ is roughly equal to 1.6.

From the measurement of the device flicker noise in Fig. 4.24, the corner frequency is in the vicinity of 150 KHz for PMOS, and in the vicinity of 9 MHz for NMOS[50].

Fig. 4.25 Impulse sensitivity function (ISF) of MOS current noise.

To apply the prediction of equation in (4.35), the calculated ISF is first obtained as shown in Fig. 4.25. The ISF of cross-coupled pair is obtained by way of using differential current noise injection on the output of VCO. And ISF of bias is also obtained with the help of current noise injection from the node of bias to the node of output of VCO. The coefficients calculated are C0=0.07, Γ_rms² =0.52 for

cross-coupled MOS and C =0.13, ₀ Γ_b²_,rms=0.14 for tail current MOS. In our design,

, 9 . 0 ,

10 92 . 1 , 10 73 .

1 ^{12 12} _max

max = × ⁻ C = × ⁻ V =

q corner frequency 15 KHz. The

calculated phase noise by equation (4.35) is shown in Fig. 4.26. with = -98.0 dBc/Hz at offset 100kHz and -114.5 dBc/Hz at offset 600 KHz, respectively. The calculated data is very closed to the measurement data. The noise contribution percentage of each part under the condition of 2GHz oscillation frequency at offset 100 KHz is listed in Table 4.4. It reveals that the tail current source take a major part in phase noise performance. This fact should not be overlooked during the design.

Fig. 4.26 The calculated phase noise spectrum by linear time-varying model

Table 4.4 Phase noise contribution of each part in the VCO circuit

LC tank 4.5%

Cross-couple PMOS

12.2%

Cross-couple NMOS

31.6%

Current Source 51.7%

The VCO performance by means of a figure of merit is defined as [35]

( )

^P

(

^mW

)

f S f

dBc _diss

2

C offset

SSB ⋅





⋅

=

FOM (4.41)

where SSSB is the signal sideband noise at offset frequency foffset. The value of FOM from equation (4.41) is -173.2dBc/Hz. The comparison with some reported papers basing on the same structure and related technology is also listed in Table 4.5. The performance of our work can be compatible with some reported papers[35.51.52].

Though a less value of FOM, our VCO has large output power of signal than others.

Table 4.5 Comparison with some reported papers basing on the same structure and related technology

4.8 Conclusion

The 2GHz low phase noise VCO with complementary cross-couple pair structure is implemented by the 0.35um CMOS technology. The phase noise reduces by the quality factor of the inductor using the layout optimization firstly. From the effective method we proposed, the minimum noise number F degrades the phase noise directly. The determination of excess noise number F during the phase noise design is indicated. The measured phase noise with -115.5 dBc Hzis optimized by choosing the suitable sizes of the cross-coupled pairs to achieve a lower mixing factor. The prediction of phase noise which we proposed according the Leeson’s model is in good agreement with the measurement. This confirmation provides a simple rule for the low phase noise VCO design.

Reference This Work [35] [51] [52]

Technology CMOS

0.35μm

CMOS 0.35μm

CMOS 0.25μm

CMOS 0.18μm

fo (GHz) 2.06 2.03 2.45 12

Vdd (V) 3 2.5 2.5 1

Power Diss. (mw) 22.62 10 10.6 7.7

Phase Noise (dBc/Hz)

-116@

0.6MHz

-117@

0.6MHz

-115@

0.6MHz

-102@

0.6MHz

FOM(dBc) -173.2 -177.6 -176.8 -179.4

Tuning range 9.1% 26% 17.9% 3.33%

Output power(dBm) 2.33 0 NA NA

Chapter 5 Conclusion

In the thesis, we first show that noise property containing passive and active device. And how noise applied to the circuit design for LNA and VCO is described.

For LNA design, we focus on the noise property and parasitic effect of low noise amplifiers with source inductance feedback SIF in the C-band. The topology of LNA with SIF to improve that input and noise match can be achieve simultaneously by adding an inductor within the amplifier.

The feasibility of the technique of source inductive feedback(SIF) for low noise amplifier(LNA) design is examined in different frequency domains. The variations in noise and input impedance are obtained by two different approaches. One is from a noisy two-port analysis to observe the variation of Fmin and Rn, and the other is form equivalent circuit model to trace out the key element. Using SIF, the results with both good input return loss about –23 dB and low minimum noise figure about 1 dB at C band are demonstrated. Another circuit design of 2.4GHz CMOS LNA with 12.5 dB gain and 5.6 dB noise figure was fabricated by the process of UMC 0.5um DPDM technology. The circuit with using SIF topology, the noise and input matching can be easily obtained, the gain and isolation are examined to be improved. Owing to the gate sheet resistance 30Ω/□ is so high that it affects the input matching, noise figure and signal gain. Therefore, choosing lower sheet resistance of poly gate is necessary to RF design.

A fully integrated LC-tank VCO with cross coupled pair is designed for 2GHz wireless application. The fabrication of VCO is in term of TSMC 0.35 μm CMOS process. The oscillation frequency and tuning range of VCO are determined by LC-tank. Regarding to LC tank, the layout optimization of spiral inductor to increase quality factor and also to reduce the phase noise is used. The inversion mode MOS varactor is used at extend the tuning range with 9.1﹪under 2GHz. From our proposed method , the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculation data is about –115.5dBc/Hz at off set frequency 600kHz.

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