2-3-1 Basic Electrical Properties of Devices

The C-V curves in Fig. 2-3 indicate a slight increase of EOT in F-incorporated sample.

Fig. 2-4 (a) shows typical drain current and transconductance characteristics as a function of the gate voltage for the devices, both with and without F incorporation. The inset table shows the initial threshold voltage. Id-Vg and Gm-Vg characteristics are almost identical between two devices. Fig. 2-4 (b) shows the cumulative probability of the threshold voltage (Vth) for the

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fabricated devices. It can be found that the Vth distribution is not affected by the addition of F.

Drain current in the saturation region is shown in Fig. 2-5. Fig. 2-6 illustrates the initial interface state density and subthreshold swing (S.S) of two samples. Output characteristics and initial interface state density are almost identical between two devices. Fig. 2-7 compares the gate leakage currents of the pMOSFETs with HfO2/SiON gate stack under both inversion and accumulation modes. Gate leakage is similar between two devices. In short, it was found that all fundamental electrical properties, including the EOT, Vth, drive current, interface state density (Nit), swing, and gate leakage current are almost non-distinguishable between the two splits with and without F incorporation.

The carrier type involved in the leakage current through HfO2/SiON dielectric layers have also been investigated for unstressed pMOSFETs, using the carrier separation method [11]. The contributing carriers of the gate leakage current can be separated into holes and electrons. Fig. 2-8 shows carrier separation results under the inversion region, and Fig. 2-9 shows carrier separation results under the accumulation region for p⁺-gated pMOSFETs with HfO2/SiON gate stack, both with and without F-incorporation. It is found that the source/drain current ISD dominates the leakage current under inversion region, and the substrate current IB

dominates the leakage current under accumulation region. This indicates holes from S/D that tunnel through gate dielectric is the dominant component of conduction mechanism under inversion region, while electrons from gate electrode that tunnel through gate dielectric is the

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dominant component of conduction mechanism under accumulation region.

This could be explained by band-diagrams shown in Fig. 2-10 (a) and carrier separation experiment shown in Fig. 2-10 (b). The substrate current IB corresponds to the electron current form the gate, while the source/drain current ISD corresponds to the hole current from Si substrate under inversion region. Electrons supply from the gate conduction band in pMOSFETs is limited by the generation rate of minority electrons in p⁺ gate. On the other hand, the probability of carriers from S/D that tunnel through gate dielectric is strongly affected by tunneling distance and barrier height [12]. Due to the asymmetry of the HfO2/SiON band structure, it is more difficult for electrons to tunnel through gate dielectric, as compared to holes. Consequently, the current through the gate stack should be smaller for electrons, as compared to holes. In pMOSFETs, hole current from the channel is the predominant injection current under stressing. The leakage component under accumulation region could also be explained by band-diagrams shown in Fig. 2-11 (a), and the current component flow in carrier separation experiment is shown in Fig. 2-11 (b).

In Figs. 2-12 (a) and (b), the gate current Ig as a function of Vg for the HfO2/SiON layer is measured from room temperature up to 125 ^oC, both under inversion region and accumulation region for two samples. The current is temperature dependent that increases with increasing temperature. This implies that the conduction mechanism of gate current is trap-related, i.e., trap-assisted tunneling (TAT), Frenkel-Poole, etc.

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The gate leakage current for devices with HfO2/SiON gate stack is composed of two types of carriers, i.e., hole current and electron current. To determine the conduction process in the HfO2/SiON dielectric, Frenkel-Poole (F-P) plots are fitted for hole current and electron current, respectively, for both samples.

The current from Frenkel-Poole emission is of the form:

where B is a constant in terms of the trapping density in the HfO2 film, φB is the barrier height, Eox is the electric field in HfO2 film, ε0 is the free space permittivity, εins is HfO2

dielectric constant, kB is Boltzmann constant, and T is the temperature measured in Kelvin.

As shown in Fig. 2-13 and Fig. 2-14, under inversion region, excellent linearity for each current characteristic has been observed for both samples. This tendency indicates that both samples exhibit the Frenkel-Poole conduction mechanism for the gate leakage current. Both the electron and hole conduction mechanisms are the same, and the result agrees well with the F-P conduction mechanism. Barrier height φB and dielectric constant εHfO2 of HfO2/SiON can be calculated. The εHfO2 value is found to be ～14.84 and ～14.7 for the control and F-incorporated samples, respectively.

0

Intercept gives the Barrier height ( )

B

The φB for the hole traps in the control sample and F-incorporated sample is about 0.98 eV and 1 eV, respectively. On the other hand, for electron traps, the φB of the control sample and F-incorporated sample are about 1.16 eV and 1.17 eV, respectively. The φB to be discussed in this chapter is the “effective” value that is representative of the HfO2/SiON gate stack [13]. We consider the case when the injected carriers flow across HfO2/SiON by hopping via the trap sites with energy barrier φB, whose value depends on the fabrication process [14]. These experimental results indicate that the energy level for traps in the control sample is similar to that of the F-incorporated sample, and the energy barrier φB for holes is clearly lower than that for electrons by about 0.2 eV in both samples.

For material analysis, transmission electron microscopy (TEM) was used to determine the exact thickness and identify the interface situation between HfO2 and Si substrate as well as interface between HfO2 and gate electrode. Fig. 2-15 shows HRTEM images of the device with HfO2/SiON gate stack. We can see that owing to RTA treatment, interfacial layer thickness becomes thicker by about 11.4Å, and must be carefully controlled to maintain a thin EOT. From the HRTEM, we can also found that the estimated value of dielectric constant for HfO2 is about 11.4.

2-3-2 Appropriate Measurement for Evaluating High-K Gate Dielectric

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samples, respectively. First, we measured Forward-1 (i.e., 0 V ~ －2 V) as the Step 1, then measured Reverse-1 (i.e., －2 V ~ 0 V) as the Step 2 of the first cycle, and repeated this sweeping cycle again. It can be seen that Vth shifts toward negative voltage after the first cycle, which indicates that net positive charges are trapped in the gate dielectric layer during

measurements, and also Vth recovers during the second cycle without applying a small stress.

Vth does not fully recover to its initial value, and some positive charges still remain in the gate

dielectric. These behaviors indicate that both fast trapping and de-trapping charges are occurring in the HfO2 during measurements.

There are two noticeable features for both samples when applying the additional small stress. First, the fact that Forwad-2 Id-Vg in Cycle 2 matches Forwad-1 Id-Vg in Cycle 1 reveals that the unstable fast charges are successfully eliminated by using a small stress. This allows

us to accurately estimate the result of the measurement. Secondly, the fact that Vth of Forward Id-Vg for both cycles maintains the same value implies that using a small stress does not cause

any extra damage to the gate stacks, nor does it affect device parameters. Fig. 2-18 shows a schematic illustration for the possible case of fast charging effects (FCE).

In order to reduce the unstable fast charge trapping and detrapping effects [15]-[19], a small positive voltage (e.g., 0.5 V) for several seconds was applied to detrap them before Id-Vg

and charge pumping measurements without causing any extra damage to the gate stacks. The purpose of this step is to more accurately estimate the density of slow traps without being

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affected by the variation of interval between the stress and measurement. In order words, we will just focus on the slow traps in the gate stacks in this work.