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氟摻雜對二氧化鉿堆疊式閘極P型金氧半場效電晶體其可靠性的影響

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(1)國 立 交 通 大 學 電子工程學系 電子研究所碩士班 碩 士 論 文. 氟摻雜對二氧化鉿堆疊式閘極 P 型金氧半 場效電晶體其可靠性的影響. Effects of Fluorine Incorporation on the Reliability Issues of pMOSFETs with HfO2/SiON Gate Stack. 研 究 生:藍文廷 指導教授:黃調元. 博士. 簡昭欣. 博士. 中 華 民 國 九 十 四 年 六 月.

(2) 氟摻雜對二氧化鉿堆疊式閘極 P 型金氧半 場效電晶體其可靠性的影響 Effects of Fluorine Incorporation on the Reliability Issues of pMOSFETs with HfO2/SiON Gate Stack 研 究 生:藍文廷. Student:Wen-Ting Lan. 指導教授:黃調元 博士. Advisor:Dr. Tiao-Yuan Huang. 簡昭欣 博士. Advisor:Dr. Chao-Hsin Chien. 國 立 交 通 大 學 電子工程學系 電子研究所碩士班 碩 士 論 文. A Thesis Submitted to Department of Electronics Engineering & Institute of Electronics Engineering and Computer Science National Chiao-Tung University in partial Fulfillment of the Requirements for the Degree of Master of Science in Electronics Engineering June 2005 Hsinchu, Taiwan, Republic of China. 中 華 民 國 九 十 四 年 六 月.

(3) 氟摻雜對二氧化鉿堆疊式閘極 P 型金氧半 場效電晶體其可靠性的影響. 研究生:藍文廷. 指導教授:黃調元 博士 簡昭欣 博士. 國立交通大學 電子工程學系. 電子研究所碩士班. 摘要. 本論文中,我們於源極/汲極摻雜前,先加入氟摻雜,使氟原子在後續 的高溫摻雜活化過程中,擴散至通道和閘極介電層,以形成氟併入。藉此, 我們深入探討氟對二氧化鉿/氮氧化矽閘極之 P 型金氧半場效電晶體可靠性 的影響。我們發現,導入氟對元件之基本特性,並無明顯改變;但於固定 電壓應力(CVS)和負偏壓-溫度應力(NBTS)量測時,有氟併入的元件具有較 低的界面狀態產生、和較少的電荷捕捉,而明顯改善元件的穩定性和可靠 性。 其次,我們探討電漿效應對二氧化鉿/氮氧化矽閘極之 P 型金氧半場效. I.

(4) 電晶體與負偏壓溫度不穩定效應的關連性、和氟併入對其影響。經由電荷 泵浦電流量測,可發現不論在負偏壓-溫度應力(NBTS)前後,界面狀態密度 均隨天線面積比而增加。因 NBTS 所導致的臨界電壓漂移,也因受到電漿 充電損傷,而更形惡化,並造成嚴重的電洞缺陷。更重要的,電漿充電效 應會使大天線面積比元件在二氧化鉿內的的電洞捕捉現象更為惡化,遠較 界面產生的缺陷更嚴重。這和傳統以二氧化矽為閘極之 P 型金氧半場效電 晶體,其惡化主因為電子捕捉,迥異其趣。利用氟併入,可有效增加對電 漿充電損傷的免疫,因而降低具有大天線面積比元件在 NBTS 時的嚴重電 洞捕捉現象。. II.

(5) Effects of Fluorine Incorporation on the Reliability Issues of pMOSFETs with HfO2/SiON Gate Stack. Student:Wen-Ting Lan. Advisors:Dr. Tiao-Yuan Huang. . Dr. Chao-Hsin Chien. Department of Electronics Engineering & Institute of Electronics National Chiao Tung University. Abstract. In this work, F was incorporated before the source/drain implant step, which was subsequently diffused into the gate stack during later dopant activation. Effects of fluorine (F) on the reliabilities of pMOSFETs with HfO2/SiON gate stack have been thoroughly studied. We found that F introduction only negligibly impacts the fundamental electrical properties of the fabricated transistors. In addition, under constant voltage stress (CVS) and negative bias temperature stress (NBTS), lower generation rates of interface states and charge trapping are observed for devices with F incorporation, thus enhances high-k devices’ stability and reliability.. III.

(6) Next, effects of plasma charging and fluorine incorporation on the NBTI of p-channel MOSFETs with HfO2/SiON gate stack were explored in this work. From charge pumping measurements, we confirm that the interface-state density is increased for devices with large antenna ratio, both before and after the BTS. It is clearly shown that the threshold voltage shift during negative bias-temperature stressing (NBTS) is deteriorated by plasma charging damage, causing severe hole traps. More importantly, we also found that hole trappings are aggravated in HfO2 film as compared to interface trap generation by plasma charging, even on virgin devices with large antenna area ratios prior to negative BTS. This result is different from that observed in traditional pMOSFETs with SiO2 gate dielectric where electron trapping is dominant. Fluorine incorporation would effectively improve plasma charging immunity, thus reducing the severe hole trapping under NBTS for devices with large antenna area ratios.. IV.

(7) 誌謝. 在大家的幫忙下,此篇碩士論文才能順利完成,在此我要感謝相當多 的人。首先,我要感謝我的指導教授黃調元博士和簡昭欣博士,在他們的 教導下,讓我學習到做研究的態度及方法和待人處世的道理。其次要感謝 實驗室的學長們,由衷感激實驗室的大師兄盧文泰學長,感謝學長不厭其 煩的教導與帶領。還有我也要感謝耀仁、冠麟、嘉裕、明賢、宏年、景森、 俊榮、柏青學長的幫忙照顧,以及與我同年的聰杰、伊鋒、賢達、新原、 彥廷、祐慈、雁雅、昶維同學在這兩年的碩士班研究中互相討論砥礪。另 外要感謝 NDL 裡面所有的研究員與工程師們,辛勤的維護實驗室的運作, 使得實驗能順利進行。最後要感謝我的家人,給我鼓勵和默默的支持,讓 我在沒後顧之憂下完成此論文。總之,要感謝的人很多,若沒有提到的在 此一起說聲謝謝,謝謝大家的幫忙!. V.

(8) Contents Abstract (Chinese).....................................................................................................................I Abstract (English)...................................................................................................................III Acknowledgement....................................................................................................................V Contents...................................................................................................................................VI Table Captions.....................................................................................................................VIII Figure Captions.......................................................................................................................IX. Chapter 1 Introduction...................................................................................................1 1-1 Backgrounds and Motivation......................................................................................1 1-2 Organization of the Thesis...........................................................................................3. Chapter 2 Impacts of Fluorine Incorporation on the Reliability of pMOSFETs with HfO2/SiON Gate Stack.............................................4 2-1 Introduction...................................................................................................................4 2-2 Experimental Procedure..............................................................................................5 2-3 Results and Discussion.................................................................................................7 2-3-1 Basic Electrical Properties of Devices................................................................7 2-3-2 Appropriate Measurement for Evaluating High-K Gate Dielectric.............11 2-3-3 NBTI of Control and Fluorine-Incorporated Devices....................................13 2-3-4 AC Stressing.......................................................................................................17 2-4 Summary......................................................................................................................19. Chapter 3 Improved Immunity against Plasma Charging Damage of. VI.

(9) pMOSFETs with HfO2/SiON Gate Stack by Fluorine Incorporation...............................................................................................21 3-1 Introduction.................................................................................................................21 3-2 Plasma Charging Damage in Control and Fluorine-Incorporated Samples.........22 3-3 Effects of Plasma Charging Damage on NBTI.........................................................24 3-4 Summary......................................................................................................................26. Chapter 4 Conclusions and Future Work...............................................................28 4-1 Conclusions..................................................................................................................28 4-2 Future Work................................................................................................................30. Reference...............................................................................................................................31. VII.

(10) Table Captions Table 1-1 2004 International Technology Roadmap for Semiconductors. The color shade means the solution known and unknown for physical limit.. VIII.

(11) Figure Captions Fig. 2-1. Process flow.. Fig. 2-2. Basic experimental setup of charge pumping measurement.. Fig. 2-3. C-V curves for pMOSFETs.. Fig. 2-4. (a) Pre-stress Id-Vg and Gm-Vg characteristics for fresh p-channel devices, (b) Cumulative probability of the threshold voltage (Vth).. Fig. 2-5. Pre-stress Id-Vd characteristics for fresh p-channel devices.. Fig. 2-6. Pre-stress interface trap density (Nit) characteristics for fresh p-channel devices.. Fig. 2-7. Gate leakage current versus gate bias for fresh p-channel devices at room temperature.. Fig. 2-8. Carrier separation under inversion region (a) w/o F sample, and (b) with F sample.. Fig. 2-9. Carrier separation under accumulation region (a) w/o F sample, and (b) with F sample.. Fig. 2-10 p+-gated pMOSFET with HfO2/SiON gate stack under inversion region (a) Band diagrams, and (b) Schematic illustration of carrier separation experiment. Fig. 2-11 p+-gated pMOSFET with HfO2/SiON gate stack under accumulation region (a) Band diagrams, and (b) Schematic illustration of carrier separation experiment. Fig. 2-12 Gate leakage current versus gate bias for fresh p-channel devices at various temperatures (a) w/o F sample, and (b) with F sample. Fig. 2-13 Conduction mechanism for source/drain current fitting under inversion region (a) w/o F sample, and (b) with F sample. Fig. 2-14 Conduction mechanism for substrate current fitting under inversion region (a) w/o F sample, and (b) with F sample. Fig. 2-15 HRTEM image of a device with HfO2/SiON gate stack.. IX.

(12) Fig. 2-16 Id-Vg characteristics for p+-gate pMOSFET without F incorporation (a) w/o small stress, and (b) with small stress. Fig. 2-17 Id-Vg characteristics for p+-gate pMOSFET with F incorporation (a) w/o small stress, and (b) with small stress. Fig. 2-18 Schematic illustrations for possible fast charging effects (FCE). Fig. 2-19 Configuration for NBTI stressing. Fig. 2-20 Id-Vg characteristics for p+-gate pMOSFETs before stress and after stress 1000 s at 25 oC (a) w/o F sample, and (b) with F sample. Fig. 2-21 Threshold voltage shift as a function of stress time, stressed at 25 oC, Vg =-3.5 V &-4 V with (a) linear scale, and (b) logarithm scale. Fig. 2-22 (a) Interface trap density shift, and (b) total trap density increase as a function of stress time. Devices were stressed at 25 oC, Vg =-3.5 V &-4 V. Fig. 2-23 Drain current degradation under saturation regime over stress time. Devices were stressed at 25 oC, Vg =-3.5 V &-4 V. Fig. 2-24 (a) Threshold voltage shift, and (b) interface trap density shift as a function of channel length. Devices were stressed at 25 oC, Vg =-4 V. Fig. 2-25 Id-Vg characteristics for p+-gate pMOSFETs before stress and after stress 1000 s at 125 oC (a) w/o F sample, and (b) with F sample. Fig. 2-26 Interface trap density shift as a function of stress time under BTS at different stress temperature, Vg =-3.5 V (a) w/o F sample, and (b)with F sample. Fig. 2-27 Threshold voltage shift as a function of stress time under BTS at different stress temperatures, Vg =-3.5 V, (a) linear scale, and (b) logarithm scale. Fig. 2-28 (a) Interface trap density shift, and (b) total trap density increase as a function of stress time under BTS at different stress temperatures, Vg =-3.5 V. Fig. 2-29 Drain current degradation under saturation over stress time. Devices were stressed at different stress temperatures, Vg =-3.5 V.. X.

(13) Fig. 2-30 Temperature dependence of (a) △Vth (b) △Nit. NBT stress was applied under Vg = -3.5 V. Fig. 2-31 Schematic setup and several parameters for measuring threshold voltage instability under AC dynamic stress. Fig. 2-32 Nit shift time evolution for pMOSFETs with HfO2/SiON gate stack, under static and dynamic stresses of different frequencies (a) w/o F sample, and (b) with F sample. Fig. 2-33 Nit shift time evolution for pMOSFETs with HfO2/SiON gate stack, under static and dynamic stresses of different duty cycles (a) w/o F sample, and (b) with F sample. Fig. 2-34 Vth shift time evolution for pMOSFETs with HfO2/SiON gate stack, under static and dynamic stresses of different frequencies (a) w/o F sample, and (b) with F sample. Fig. 2-35 Vth shift time evolution for pMOSFETs with HfO2/SiON gate stack, under static and dynamic stresses of different duty cycles (a) w/o F sample, and (b) with F sample. Fig. 2-36 (a) Frequency dependence of △Nit, stressed at 25 oC, Vg =-4 V, duty cycle = 50% (b) Duty Cycle dependence of △Nit, stressed at 25 oC, Vg =-4 V under unipolar 10KHz. Fig. 2-37 Frequency dependence of △Vth, stressed at 25 oC, Vg =-4 V, duty cycle = 50% (b) Duty Cycle dependence of △Vth, stressed at 25 oC, Vg =-4 V under unipolar 10KHz. Fig. 3-1. Schematic of a transistor with area antenna.. Fig. 3-2. Wafer mappings of (a) negative and (b) positive potential values recorded by CHARM-2 sensors.. Fig. 3-3. Nit of PMOS devices (a) before sintering, and (b) after sintering, both as a function. XI.

(14) of device location on the wafer. Fig. 3-4. Vth of PMOS devices (a) before sintering, and (b) after sintering, both as a function of device location on the wafer.. Fig. 3-5. Cumulative probability of the (a) threshold voltage (Vth), and (b) interface trap density (Nit).. Fig. 3-6. Output characteristics for fresh devices with AARs of 1K and 60K.. Fig. 3-7. Threshold voltage shift as a function of stress time, stressed at 25 oC, Vg =-4 V, plotted in (a) linear scale, and (b) logarithm scale.. Fig. 3-8. (a) Interface trap density shift, and (b) total trap density increase, as a function of stress time. Devices were stressed at 25 oC, Vg =-4 V.. Fig. 3-9. Drain current degradation under saturation regime over stress time. Devices were stressed at 25 oC, Vg =-4 V.. Fig. 3-10 Threshold voltage shift as a function of stress time, stressed at 125 oC, Vg =-3.5 V, plotted in (a) linear scale, and (b) logarithm scale. Fig. 3-11 (a) Interface trap density shift, and (b) total trap density shift as a function of stress time. Devices were stressed at 125 oC, Vg =-3.5 V. Fig. 3-12 Drain current degradation under saturation regime over stress time. Devices were stressed at 125 oC, Vg =-3.5 V. Fig. 3-13 Threshold voltage shift as a function of stress time under BTS at different stress temperatures, Vg =-3.5 V and AAR of 60K, plotted in (a) linear scale, and (b) logarithm scale. Fig. 3-14 (a) Interface trap density shift, and (b) total trap density shift as a function of stress time under BTS at different stress temperatures, Vg =-3.5 V. AAR is 60K.. XII.

(15) Chapter 1 Introduction. 1-1 Backgrounds and Motivation Aggressive gate insulator scaling in CMOS devices leads to excessive gate leakage and device reliability problems. Consequently, alternative gate insulators with higher permittivity than SiO2 are currently widely investigated for the future generation of MOS transistors. The use of dielectric layers with higher electrical permittivity should allow us to use physically thicker films with the same electrical capacitance than ultra-thin SiO2, and one would thus expect to reduce the leakage current and improve the reliability of the gate dielectric layer. The aggressive down scaling of the CMOS technology will require high-k gate dielectrics to meet the specifications in ITRS (see Table 1-1) [1] in terms of sufficiently low gate leakage coupled with thin enough (<1nm) equivalent oxide thickness. Among the high-k dielectrics being studied, HfO2 appears to be the most promising one due to its relatively high dielectric constant (~25) as compared to Si3N4 and Al2O3, its relatively high free energy of reaction with Si (47.6 Kcal/mol at 727 oC) as compared to TiO2 and Ta2O5, wide band gap (~ 5.8 eV), and suitable tunneling barrier heights for both electron and holes (>1 eV). Notwithstanding, there are still a number of pending issues, including channel mobility degradation, large number of fixed charges and charge traps, and threshold voltage instability. 1.

(16) that need to be tackled before its induction to mass production. For example, people are working diligently to effectively eliminate the threshold voltage instability by reducing the relatively high trap density presented in the bulk of high-k dielectric and high interface trap density at the interface of high-k/interfacial layer/Si stack structure. Numerous literatures have been published regarding methods to incorporate nitrogen [2-3] or Si [4-5] into Hf-based films/stack in order to improve the film quality. However, to the best of our knowledge, there are no related reports on the influence of fluorine incorporation on HfO2 gate dielectric. In this work, fluorine is incorporated into HfO2 gate stack by fluorine implantation into the source/drain regions, and its impacts on the pMOSFETs reliabilities are studied. It was clearly seen that the degradation is improved in the F-incorporated samples. Moreover, since few studies [6] have been done on the area of plasma effects on HfO2 gate stack, we have performed a systematic study, and found that higher area antenna ratio will result in more severe degradation. More importantly, we also found that charging damage in devices with HfO2/SiON can be effectively improved by fluorine implantation. We believe it has the potential to become an industrial standard if MOCVD HfO2 is the final choice of future dielectric for the ULSI industry.. 2.

(17) 1-2 Organization of the Thesis To fully understand the effects of fluorine incorporation on pMOSFETs with HfO2/SiON gate stack, systematic experiments and measurements were performed in this study. In addition to this chapter that is dedicated to a brief introduction and historical review, this thesis is organized as follows: In Chapter 2, we describe the process steps for fabricating test devices with HfO2/SiON gate stack. Some basic electrical properties such as the components in the gate leakage current and their mechanisms, and some reliability issues such as constant voltage stress (CVS), negative bias temperature stress (NBTS) and dynamic AC stress of the devices with and without fluorine are explored and discussed. In Chapter 3, we present the results on evaluating the plasma charging damage of the devices. We use the NBTI characterization as a sensitive method for characterizing the antenna effects in devices with HfO2/SiON, which is particularly attractive in light of the fact that conventional indicators are becoming inadequate as oxide is scaled down. The effect of fluorine incorporation on plasma charging damage is also investigated. Chapter 4 concludes this work by summarizing the major results and important findings we have obtained. Some suggestions for future work on this topic is also given.. 3.

(18) Chapter 2 Impacts of Fluorine Incorporation on the Reliability of pMOSFETs with HfO2/SiON Gate Stack. 2-1 Introduction Recently, negative-bias-temperature instability (NBTI) is recognized as a major reliability issue in scaled pMOSFETs [7]–[8]. During negative bias stress at elevated temperatures, defects can be generated in the device, which in turn cause threshold voltage shifts and drive current reductions. The device parameter degradations can lead to circuit failures, both for analog and digital applications. Unlike SiO2 films, high-k films are more susceptible to charge trapping. Charge trapping causes the threshold voltage to shift with stressing time, and is therefore an important transistor reliability issue. Two mechanisms: trapping effect and reaction-diffusion model compete in NBTI for pMOSFETs with high-k gate dielectric. Fluorine is known to worsen boron penetration in PMOS devices employing p+ polysilicon gate. As such, fluorine incorporation has been generally regarded as undesirable for PMOS device applications. Nevertheless, an appropriate fluorine implant will enhance oxide reliability. Huard et al. has demonstrated that the use of BF2 implants, in lieu of B implants, for the. 4.

(19) S/D and poly gate for the traditional p+-gated pMOSFETs with SiO2 dielectric results in lower device degradation. Fluorine was found to improve the gate oxide reliability. This result has been confirmed by deliberate fluorine implantation, in addition to BF2 doping, which also shows alleviated NBTI degradation [9]. In this thesis, effects of fluorine (F) on the reliabilities of pMOSFETs with HfO2/SiON gate stack have been studied. Boron atoms, required to achieve p+-doped gate layers, have raised some concerns about their possible roles in the NBTI degradation. In this work, F was incorporated during the source/drain implant step, which was subsequently diffused into the gate stack during later dopant activation. Charge pumping measurements were extensively used to investigate the rootcause of the BTI degradation. It will be shown that all reliabilities such as CVS, NBTI and AC dynamic stress are improved by fluorine incorporation.. 2-2 Experimental Procedure In this thesis, local oxidation of silicon (LOCOS) process was used for device isolation. MOS transistors was fabricated on 6-inch p-type Si with (1 0 0)-oriention. After removing the 300Å sacrificial oxide, RCA clean was performed with HF-dip last, and immediately followed by a conventional RTA at 700 oC in N2O ambient to form about 0.7nm interfacial oxynitride layer (SiON). Afterwards, HfO2 film of approximately 3nm was deposited by atomic vapor deposition (AVDTM) in an AIXTRON Tricent® system at a substrate temperature of 500 oC,. 5.

(20) followed by 700 oC N2 RTA for 20 sec in order to improve the film quality. The MOCVD system was designed for 8-inch wafers, so a 6-inch quartz was used as wafer carrier for film deposition. The physical thickness of the SiON and HfO2 films was measured by optical n&k analyzer. A 200nm undoped polycrystalline silicon (poly-Si) layer was directly deposited by low pressure chemical vapor deposition (LPCVD) on top of the HfO2 films. After the gate electrode was patterned by lithography and etching processing, some samples received the fluorine (F, 2×1015 cm-2) ion implantation into source/drain region without removing the photoresist on the gate electrode. This was deliberately done in order to avoid the complication of enhanced boron penetration by F. All samples were then processed to form source/drain regions by B implantation, with the dopants activated at 950 oC by rapid thermal annealing (RTA) for 20 sec in an N2 atmosphere. It should be noted that the activation thermal budget also served to diffuse the F spices into the gate stack and channel region. After passivation, contact holes formation, Al metallization and patterning were performed. Finally, all devices received the forming gas annealing at 400 oC for 30 minutes. Current-voltage (I-V) and capacitance-voltage (C-V) characteristics were evaluated by an HP4156A precision semiconductor parameter analyzer and an HP4284 LCR meter, respectively. The equivalent oxide thickness (EOT) of the gate dielectric was obtained from high frequency (100 KHz) capacitance-voltage (C-V) curve at strong inversion without considering quantum effect. The key process flow is summarized in Fig. 2-1.. 6.

(21) In this thesis, the interface trap density (Nit) was analyzed using the charging pumping technique [10]. Square-wave waveforms (f = 1MHz) were applied to the gate, and the base voltage was varied from inversion to accumulation, while keeping the pulse amplitude at 1.2 V. Fig. 2-2 shows the configuration of measurement setup used in our charge pumping experiment. A MOSFET with gate area AG gives the charge pumping current as: Icp = qAG f Nit,. (2-1). Interface trap density could be extracted from the above equation. The total trap density increase, △Ntot, which includes the increase of interface trap density and bulk trap density, was calculated from △Vth by assuming that the charge was trapped at the interface between the dielectric and the substrate. △Ntot = C△Vth /qAG. (2-2). 2-3 Results and Discussion 2-3-1 Basic Electrical Properties of Devices The C-V curves in Fig. 2-3 indicate a slight increase of EOT in F-incorporated sample. Fig. 2-4 (a) shows typical drain current and transconductance characteristics as a function of the gate voltage for the devices, both with and without F incorporation. The inset table shows the initial threshold voltage. Id-Vg and Gm-Vg characteristics are almost identical between two devices. Fig. 2-4 (b) shows the cumulative probability of the threshold voltage (Vth) for the. 7.

(22) fabricated devices. It can be found that the Vth distribution is not affected by the addition of F. Drain current in the saturation region is shown in Fig. 2-5. Fig. 2-6 illustrates the initial interface state density and subthreshold swing (S.S) of two samples. Output characteristics and initial interface state density are almost identical between two devices. Fig. 2-7 compares the gate leakage currents of the pMOSFETs with HfO2/SiON gate stack under both inversion and accumulation modes. Gate leakage is similar between two devices. In short, it was found that all fundamental electrical properties, including the EOT, Vth, drive current, interface state density (Nit), swing, and gate leakage current are almost non-distinguishable between the two splits with and without F incorporation. The carrier type involved in the leakage current through HfO2/SiON dielectric layers have also been investigated for unstressed pMOSFETs, using the carrier separation method [11]. The contributing carriers of the gate leakage current can be separated into holes and electrons. Fig. 2-8 shows carrier separation results under the inversion region, and Fig. 2-9 shows carrier separation results under the accumulation region for p+-gated pMOSFETs with HfO2/SiON gate stack, both with and without F-incorporation. It is found that the source/drain current ISD dominates the leakage current under inversion region, and the substrate current IB dominates the leakage current under accumulation region. This indicates holes from S/D that tunnel through gate dielectric is the dominant component of conduction mechanism under inversion region, while electrons from gate electrode that tunnel through gate dielectric is the. 8.

(23) dominant component of conduction mechanism under accumulation region. This could be explained by band-diagrams shown in Fig. 2-10 (a) and carrier separation experiment shown in Fig. 2-10 (b). The substrate current IB corresponds to the electron current form the gate, while the source/drain current ISD corresponds to the hole current from Si substrate under inversion region. Electrons supply from the gate conduction band in pMOSFETs is limited by the generation rate of minority electrons in p+ gate. On the other hand, the probability of carriers from S/D that tunnel through gate dielectric is strongly affected by tunneling distance and barrier height [12]. Due to the asymmetry of the HfO2/SiON band structure, it is more difficult for electrons to tunnel through gate dielectric, as compared to holes. Consequently, the current through the gate stack should be smaller for electrons, as compared to holes. In pMOSFETs, hole current from the channel is the predominant injection current under stressing. The leakage component under accumulation region could also be explained by band-diagrams shown in Fig. 2-11 (a), and the current component flow in carrier separation experiment is shown in Fig. 2-11 (b). In Figs. 2-12 (a) and (b), the gate current Ig as a function of Vg for the HfO2/SiON layer is measured from room temperature up to 125 oC, both under inversion region and accumulation region for two samples. The current is temperature dependent that increases with increasing temperature. This implies that the conduction mechanism of gate current is trap-related, i.e., trap-assisted tunneling (TAT), Frenkel-Poole, etc.. 9.

(24) The gate leakage current for devices with HfO2/SiON gate stack is composed of two types of carriers, i.e., hole current and electron current. To determine the conduction process in the HfO2/SiON dielectric, Frenkel-Poole (F-P) plots are fitted for hole current and electron current, respectively, for both samples. The current from Frenkel-Poole emission is of the form:. I ∝ V exp(. 2a V qφB ) − T k BT. J = B * Eox exp( ln(. (2-3). − q (φB − qEox / πε insε 0 ) ) k BT. q q / πε insε 0 J )= Eox k BT. Eox −. (2-4). qφB k BT. ⇒ Intercept gives the Barrier height ( −. (2-5). qφB ) k BT. where B is a constant in terms of the trapping density in the HfO2 film, φB is the barrier height, Eox is the electric field in HfO2 film, ε0 is the free space permittivity, εins is HfO2 dielectric constant, kB is Boltzmann constant, and T is the temperature measured in Kelvin. As shown in Fig. 2-13 and Fig. 2-14, under inversion region, excellent linearity for each current characteristic has been observed for both samples. This tendency indicates that both samples exhibit the Frenkel-Poole conduction mechanism for the gate leakage current. Both the electron and hole conduction mechanisms are the same, and the result agrees well with the F-P conduction mechanism. Barrier height φB and dielectric constant εHfO2 of HfO2/SiON can be calculated. The εHfO2 value is found to be ~14.84 and ~14.7 for the control and F-incorporated samples, respectively.. 10.

(25) The φB for the hole traps in the control sample and F-incorporated sample is about 0.98 eV and 1 eV, respectively. On the other hand, for electron traps, the φB of the control sample and F-incorporated sample are about 1.16 eV and 1.17 eV, respectively. The φB to be discussed in this chapter is the “effective” value that is representative of the HfO2/SiON gate stack [13]. We consider the case when the injected carriers flow across HfO2/SiON by hopping via the trap sites with energy barrier φB, whose value depends on the fabrication process [14]. These experimental results indicate that the energy level for traps in the control sample is similar to that of the F-incorporated sample, and the energy barrier φB for holes is clearly lower than that for electrons by about 0.2 eV in both samples. For material analysis, transmission electron microscopy (TEM) was used to determine the exact thickness and identify the interface situation between HfO2 and Si substrate as well as interface between HfO2 and gate electrode. Fig. 2-15 shows HRTEM images of the device with HfO2/SiON gate stack. We can see that owing to RTA treatment, interfacial layer thickness becomes thicker by about 11.4Å, and must be carefully controlled to maintain a thin EOT. From the HRTEM, we can also found that the estimated value of dielectric constant for HfO2 is about 11.4.. 2-3-2 Appropriate Measurement for Evaluating High-K Gate Dielectric Fig. 2-16 and Fig. 2-17 illustrate Id-Vg characteristics for the control and F-incorporated. 11.

(26) samples, respectively. First, we measured Forward-1 (i.e., 0 V ~ -2 V) as the Step 1, then measured Reverse-1 (i.e., -2 V ~ 0 V) as the Step 2 of the first cycle, and repeated this sweeping cycle again. It can be seen that Vth shifts toward negative voltage after the first cycle, which indicates that net positive charges are trapped in the gate dielectric layer during measurements, and also Vth recovers during the second cycle without applying a small stress. Vth does not fully recover to its initial value, and some positive charges still remain in the gate dielectric. These behaviors indicate that both fast trapping and de-trapping charges are occurring in the HfO2 during measurements. There are two noticeable features for both samples when applying the additional small stress. First, the fact that Forwad-2 Id-Vg in Cycle 2 matches Forwad-1 Id-Vg in Cycle 1 reveals that the unstable fast charges are successfully eliminated by using a small stress. This allows us to accurately estimate the result of the measurement. Secondly, the fact that Vth of Forward Id-Vg for both cycles maintains the same value implies that using a small stress does not cause any extra damage to the gate stacks, nor does it affect device parameters. Fig. 2-18 shows a schematic illustration for the possible case of fast charging effects (FCE). In order to reduce the unstable fast charge trapping and detrapping effects [15]-[19], a small positive voltage (e.g., 0.5 V) for several seconds was applied to detrap them before Id-Vg and charge pumping measurements without causing any extra damage to the gate stacks. The purpose of this step is to more accurately estimate the density of slow traps without being. 12.

(27) affected by the variation of interval between the stress and measurement. In order words, we will just focus on the slow traps in the gate stacks in this work.. 2-3-3 NBTI of Control and Fluorine-Incorporated Devices Negative bias temperature instability (NBTI) is an important reliability issue as it causes the threshold voltage to shift with electrical stressing. To evaluate device degradations due to the bias temperature (BT) stress, the gate electrode of the device was subjected to stress condition with negative bias (-3.5 V) varying from 25 oC to 125 oC, while the drain/source and substrate were all grounded, as shown in Fig. 2-19. The dependences of threshold voltage, interface trap density, bulk trap density, and drain current on stress time are investigated at various temperatures. For both control and fluorine-incorporated devices, negligible change in S.S is observed under constant voltage stress at room temperature, as shown in Figs. 2-20 (a) and (b). This indicates that interface state generation plays no significant role, rather, charge trapping in the bulk dielectric is the primary mechanism leading to CVS issues in high-k dielectrics. Vth shift of the control sample is found to be slightly larger. The threshold voltage shift (△Vth) is measured with respect to the Id-Vg curves shown in Fig. 2-21 (a) in linear scale and (b) in logarithm scale. The threshold voltage shifts toward negative gate voltage (△Vth < 0), thus implying that net positive charges are trapped in the. 13.

(28) gate dielectric layer as the device is stressed. It is clear that the F-incorporated sample always shows smaller △Vth than the control sample under different stress voltages. Fig. 2-21 (b) shows that Vth degradation obeys the power law [20]-[21],. △Vth (t) = Atb. (2-6). and the exponential values of both samples at Vg =-4V (~0.12) are much larger than those of the devices at Vg =-3.5 V (about 0.03~0.04). This indicates that Vth degradation is more severe for the devices under larger constant voltage stressing. The exponential value is voltage dependent relative to bulk trap generation. To further gain insights into the degradation mechanism during voltage stressing, the interface state generation, △Nit,, and the increase of effective total trap density, △Ntot, are plotted as a function of the stress time in Fig. 2-22 (a) and (b), respectively. Apparently, △Ntot ( = △Nit +△Not ) is significantly larger than △Nit, suggesting that the degradation under CVS is dominated by the charge trapping in the bulk of HfO2 film, rather than the generation of interface states, irrespective of whether F is added or not. The instability of HfO2/SiON gate stack is mainly determined by the bulk charge traps, contrast to that in the SiON gate stacks. In addition, the improvement in charge trapping is larger than that in interface generation for F-incorporated samples. The degradation in drain current after CVS for the devices are shown and compared in Fig. 2-23. Due to larger Vth shift and interface state generation (△Nit) of the control sample,. 14.

(29) more severe drain current degradation is observed. Fig. 2-24 shows that the F-implanted sample depicts lower degradation of (a) threshold voltage shift (△Vth) and (b) interface trap density shift (△Nit), as compared to the control sample, with scaling channel length. This reduction is mainly due to the fact that more fluorine is incorporated into the gate dielectric during dopant activation as the channel length becomes smaller, leading to a reduction of bulk traps density and interface traps density. Therefore, it is interesting to find that the impact for △Vth and △Nit increases as the channel length decreases. Since the diffusion distance of F atoms is constant, the ratio of diffusion distance divided by the channel length would be higher as the channel length decreases, and more F could become trapped. This indicates that the method of using fluorine implant into S/D is feasible for future CMOS technology. The improvement may be due to fluorine atoms, similar to nitrogen atoms, form complexes at the interface and dielectric, which reduce the total number of available Si-H bonds, and passivate the bulk trap, leading to less CVS degradation. It can be seen that Id-Vg curves shift toward more negative voltage with increasing stress time at 125 oC for both the control and fluorine incorporated devices, as shown in Figs. 2-25 (a) and (b), respectively. Further, Vth shift of the control sample is slightly larger. There is observable change in S.S at high temperature, compared to that at room temperature, indicating that △Nit increases with increasing temperature. This phenomenon is consistent. 15.

(30) with our results as shown in Fig. 2-26 (a) and (b) for both samples. It can be seen that fluorine-incorporated devices always show smaller △Nit than the control devices at all temperatures. Fig. 2-27 (a) compares the NBT-stress-time dependence of threshold voltage shift for the HfO2/SiON gate stack with and without F incorporation. A significantly smaller Vth shift is observed for the F-incorporated sample under the BT stress, Vg =-3.5 V at 25 oC and 125 oC. Such phenomena can be attributed to fluorine incorporation into the gate dielectric. Fig. 2-27 (b) shows that the exponential values of both samples at 125 oC (about 0.13~0.14) are much larger than those of the devices at 25 oC (about 0.03~0.04). This indicates that the Vth degradation could be more severe for the devices under BT stress at high temperature [22]. The exponential value is temperature dependent relative to bulk trap generation. Figs. 2-28 (a) and (b) show △Nit and △Ntot as a function of time during NBTI for both devices measured at different temperatures. It is found that for both devices, Vth degradation during NBTI stressing is primarily caused by the charge trapping in bulk HfO2, rather than the interfacial degradation. Drain current degradation for F-incorporated device is shown in Fig. 2-29. All results are consistent with the effectiveness of fluorine incorporation in alleviating the BT instability. The major degradation of NBTI is caused by the positive charge trapping in the films rather than the interface generation, suggesting that the positive charge trapping is not completely caused by the H+ capturing. Hence, it can be concluded that, except for. 16.

(31) positive charge caused by H species, a large amount of extra trapping centers is also present in the HfO2/SiON gate stack. F atoms seem to effectively decorate these trapping centers, leading to less degradation. Note that the activation energies of NBT degradation for fluorine incorporated HfO2/SiON gate stack are identical with those without fluorine incorporation, as shown in Figs. 2-30 (a) and (b). Specifically, the activation energies of △Vth and △Nit are 0.08 eV and 0.14 eV, respectively, for both devices. Note that the activation energy of △Vth is lower than that of △Nit, indicating that Vth instability is not simply contributed by interface trap generation, but mainly comes from the more significant charge trapping in the bulk of high-k dielectric. Furthermore, it should be noted that both △Vth and △Nit are improved by fluorine incorporation, while maintaining almost identical activation energies.. 2-3-4 AC Stressing Most gate dielectric reliability stressing tests rely on DC stressing because of its simplicity. However, in actual CMOS circuit operation, AC gate bias with specific frequency and duty cycle is usually used. AC stress is thus more realistic, and can provide additional insights into the trapping dynamics. It has been reported that AC stressing of SiO2 usually results in longer lifetime than DC stressing [23]-[24]. Fig. 2-31 illustrates the schematics of the measurement setup for threshold voltage instability testing under dynamic stress. During. 17.

(32) the stress, AC square wave pulses from a pulse generator are applied to the gate through the switch; while the other three terminals are grounded. The sum of ‘on-time’ during the stress is defined as the total stress time in unipolar AC stress. For different bias frequencies, cumulative ‘on-time’ under AC unipolar stress is defined as the ‘stress time’. The duty cycle is fixed at 50% for all samples. While for different duty cycles, frequency is fixed at 10KHz for all the samples. Negligible variation in △Nit is observed with increasing frequency and decreasing duty cycle under AC stress for both samples, as shown in Fig. 2-32 and Fig. 2-33. As shown in Fig. 2-34 and Fig. 2-35, △Vth turns around and shifts toward positive gate voltage in AC stress for both samples. Figs. 2-36 (a) and (b) show that △Nit of the F-incorporated sample is smaller than that of the control sample under AC stress for any frequency or duty cycle. This is in agreement with the result in △Nit presented in DC stress. It is observed from Figs. 2-37 (a) and (b) that Vth degradation is strongly dependent on the frequency and duty cycle of the dynamic stress. Vth for both cases shift toward more positive gate voltage as frequency increases. Similar trend is observed as duty cycle decreases. △Vth for F-incorporated sample is lower than the control sample, irrespective of frequency and duty cycle. The film quality of fluorine incorporation is more robust under AC stress. Since Vth degradation of PMOS is primarily caused by charge trapping in the HfO2 film and shifts toward negative gate voltage under DC stress. The bulk traps of HfO2 appears to be. 18.

(33) the dominant factor in the threshold voltage instability of pMOSFETs with the HfO2/SiON dielectric by trapping or detrapping charges during AC stress. This finding suggests that both hole trapping and electron trapping occur during DC stress, and hole trapping is dominant due to the fact that the hole current is larger than the electron current under inversion region from carrier separation experiments. Although holes do not have enough time to get trapped, electrons trapped during on-period result in a significant Vth shift toward positive gate voltage, and electron trapping is dominant under AC stress. Electrons are more likely to be trapped, compared to holes, because holes must first go through SiON before getting trapped in HfO2 film. This observation could be explained by band diagram shown in Fig. 2-10 (a). Higher frequencies and lower duty cycles result in larger Vth shift toward positive gate voltage, and are considered to be due to the fact that holes can not follow the step of high frequency variation, and few hole charges get trapped during on-period in HfO2 gate dielectric.. 2-4 Summary In this work, we find the exponential value of △Nit is about 0.23~0.25 for both samples either under CVS or NBTI. This value of △Nit is similar to that of traditional SiO2 dielectric under stressing, while the exponential value of △Vth is voltage dependent and temperature dependent. As a result, we can confirm again that charge traps in the bulk of HfO2/SiON gate stack are responsible for the instability. We can expect a continuous distribution of charge. 19.

(34) trapping cross sections, instead of a discrete-value capture cross section, in HfO2 high-k film [15]. A better interface is expected to help reduce Vth instability, therefore bulk traps need to be reduced. The experimental results show that hole trapping is dominant in DC stress and electron trapping is dominant in AC stress. Bias frequency and duty cycle dependence under AC dynamic stress lead us to conclude that the bulk trap of HfO2 is primarily responsible for changing △Vth polarity in HfO2/SiON pMOSFETs.. 20.

(35) Chapter 3 Improved Immunity against Plasma Charging Damage of pMOSFETs with HfO2/SiON Gate Stack by Fluorine Incorporation. 3-1 Introduction Plasma processes have been known to cause gate oxide and MOSFET degradations. Many plasma processing steps, such as poly-silicon etching for transistor gate length definition [25]-[26], metal etching [27], and photo-resist ashing [28] are indispensable for wafer fabrication. With the scaling of the transistor gate length and gate oxide thickness, the gate edge damage and gate oxide damage could both become more serious by the poly-silicon etching. Meanwhile, it has been shown that metal etching and its subsequent resist ashing could induce serious plasma charging damages. With the fabrication of multi-level metal interconnect in ULSI circuits, repetitive exposures to plasma processes are unavoidable. Consequently, better understanding of plasma damage is essential to achieve highly reliable ULSI circuits. To detect plasma process-induced damage (P2ID), the typical test structure is a small area capacitor or transistor connected to a large conductive antenna receiver. Metal antenna structures attached to the gate electrode with various antenna area ratios (AAR) were used to. 21.

(36) monitor the plasma charging damage. In conventional pMOSFETs with SiO2 gate, severe charging damage could occur at the center, due to the non-uniform plasma generation caused by the gas injection mode of the asher. In this chapter, HfO2/SiON pMOSFETs with antenna structures are employed as the test devices. We also study the effects of fluorine incorporation on plasma charging damage. The HfO2/SiON gate stack degradation due to the charging damage can be evaluated using constant voltage stress (CVS) and bias-temperature stress (BTS). Furthermore, more detailed information, such as the effects of antenna size, charging polarity and the device location on the wafer, is carefully examined. We for the first time demonstrate that F incorporation into HfO2/SiON gate stack could strengthen the immunity against plasma charging damage [29].. 3-2 Plasma. Charging. Damage. in. Control. and. Fluorine-. Incorporated Samples PMOS transistors with p+ poly-Si gate were fabricated on 6-inch wafers. Metal antennas with various antenna ratios (AAR) were attached to the gate. The AAR is defined as the area ratio between the metal pad and the active device region. Schematic of a transistor with area antenna is shown in Fig. 3-1. In our processing, after metal patterning, the remaining photo-resist layer was stripped off with O2 plasma in a down-stream plasma asher, whose configuration and plasma potential. 22.

(37) can be found in [30]. Previously, CHARM-2 wafer sensor was used to establish the potential distribution in the chamber. Highly negative and positive potential values were identified at the wafer center and edge, respectively, as shown in Fig. 3-2 (a) and Fig. 3-2 (b). Fig. 3-3 (a) and Fig. 3-3 (b) compare the interface state density as function of device location on the wafer before and after H2 sintering. The interface-state density of the antenna devices was also analyzed using the charge pumping technique. Fig. 3-4 (a) and Fig. 3-4 (b) show the results as function of device location on the wafer before and after H2 sintering. It is interesting to find that the |Vth| values for the control devices with AAR of 60K are larger than the other devices, irrespective of sintering. In Fig. 3-3 (b), it is seen that Nit is higher for the control devices with AAR of 60K. This indicates unambiguously that hole trapping is solely responsible for the observed high |Vth| on fresh devices with large antenna, as shown in Fig. 3-4 (b). Both Vth and Nit of two devices are lower after sintering. Forming gas anneal effectively improves MOSFET characteristics. These can be attributed to improved interface quality and reduced bulk trap in HfO2 film by H atoms. Fig. 3-5 (a) and Fig. 3-5(b) display the cumulative probability of the threshold voltage (Vth) and interface trap density (Nit) for the fabricated devices located near the wafer center. Remarkably, the control devices with AAR of 60K depict larger |Vth| and Nit values than their counterparts with F incorporation. Plasma charging damage would cause more charge trapping in HfO2 film and more interface state density, resulting in larger |Vth|.. 23.

(38) Output characteristics for the fresh devices with AAR of 1K and 60K, both with and without F incorporation are shown in Fig. 3-6. It is interesting to find that the drain current in the fresh devices is actually smaller for the control device with AAR of 60K. This is ascribed to a high |Vth| for the fresh devices with a large antenna, implying that more hole trapping events occur after plasma processing. This result is different from the traditional PMOS transistor with SiO2 gate and a larger antenna has a low |Vth|, implying that more electron trapping events occur during plasma processing. Moreover, all these results testify that the plasma antenna charging effect creates more hole traps in the HfO2/SiON gate stack, and F incorporation can significantly reduce the impact of plasma charging effect.. 3-3 Effects of Plasma Charging Damage on NBTI Figs. 3-7 (a) and (b) show the time evolution of threshold voltage shift at 25 oC for devices with area antenna ratios (AAR) of either 1K or 60K, both with and without F incorporation, in linear scale and logarithm scale, respectively. All mesured devices were selected from the same die location on the wafer center. It should be noted that in Fig. 3-7 (a) Vth shift is larger for the control device with AAR of 60K, indicating that negative (i.e., wafer center) plasma charging could degrade the CVS. Fig. 3-7 (b) shows that Vth degradation obeys the power law and the exponential values of all devices at Vg =-4 V (about 0.1~0.13) are similar. Fig. 3-8 (a) and Fig. 3-8 (b) compare △Ntot and △Nit as function of time. It should be. 24.

(39) noted that △Ntot was calculated from △Vth assuming that the charge was trapped at the interface between the dielectric and the substrate. △Ntot is about 1.5~2 order larger than △Nit for all devices, indicating that charge trapping in the bulk trap dominates threshold voltage shift. Apparently, the F incorporation is shown to be effective in suppressing △Ntot and △Nit on the devices with large antenna. The reductions in drain current after CVS for the devices are shown and compared in Fig. 3-9. Due to larger Vth shift caused by plasma charging effect, enhanced drain current degradation is observed for control devices with AAR of 60K. When the antenna size increases, NBTI worsens, as shown in Fig. 3-10 (a). The Vth shift is higher for devices with large AAR (e.g., 60K). This indicates that the generation rates of interface states and the positive charges during the NBTI stressing are degraded due to the plasma charging damages. Fig. 3-10 (b) shows that the exponential values of the devices with AAR of 60K at Vg =-3.5 V (~0.18) are much larger than that of the devices with AAR of 1K at Vg =-3.5 V (~0.1), both with and without F incorporation. This implies that the degradation could be more serious for the devices with AAR of 60K under NBTI stressing. Such Vth shift observed in p-channel MOSFETs can be attributed to the enhanced positive charge build-up in the HfO2 dielectric and an increase in interface state density, as shown in Fig. 3.11 (a) and Fig. 3-11 (b). More hole charges trapped in the HfO2 dielectric cause more severe threshold voltage shift. In Fig 3-12, PMOS with high-k dielectrics also demonstrate. 25.

(40) higher sensitivity to the BTS of the Id degradation parameter on the plasma charging damage with larger antenna. Vth shift in Fig. 3-13 and Ntot and Nit shift in Fig. 3-14 as function of stress time are for the devices with a large antenna (e.g., AAR = 60K) under NBTI stressing at 25 oC and 125 oC. A large degradation in all parameters is observed when stress temperature increases [31]-[34]. These results show that when temperature increases, the increase of the bulk trap generation is higher than the interface state generation, resulting in larger Vth shift. Bulk trap generation is the main degradation in HfO2 high-k film, and becomes even more severe at high temperature. More importantly, F-incorporated films do exhibit better NBTI improvement. The above results confirm that the NBTI of PMOS devices is degraded by plasma charging effect. The possible mechanism is that the enhanced hole trapping events caused by the plasma charging increases the generation of interface states and bulk traps. The hole trapping in the bulk, rather than the interface generation, is the dominant mechanism responsible for the degradation; while it can be significantly improved by the F incorporation.. 3-4 Summary In this study, the effects of metal etching and subsequent resist ashing on the gate oxide integrity and device characteristics were studied. Our results show that the main factor that affects gate oxide integrity is the severe plasma charging damages. As a result, the devices. 26.

(41) with large antenna depict degraded Vth, Nit and Id. The enhanced degradations occurred during photo-resist stripping step. Increase of positive trapped charges in the gate dielectrics is a plausible cause for aggravated NBTI. Finally, we also proposed that the CVS and NBTI characterization could be cleverly employed as a sensitive method for characterizing the antenna effects in the devices with HfO2/SiON gate stack. Both CVS and NBTI on HfO2/SiON pMOSFETs with antenna structures are also found to be primarily due to charge trap generation in the bulk of HfO2 (△Not), instead of at the interface (△Nit). We demonstrated for the first time that plasma charging effect induces hole trapping in the HfO2/SiON gate stack; while it can be effectively suppressed with F incorporation. In other words, F incorporation can reduce hole traps in HfO2 high-k film.. 27.

(42) Chapter 4 Conclusions and Future Work. 4-1 Conclusions In this thesis, the effects of fluorine incorporation into HfO2/SiON gate stack were investigated. Several important phenomena were observed and summarized as follows: First, we have investigated its basic electrical properties. The initial electrical properties of the devices are negligibly affected by fluorine incorporation. The gate leakage current is analyzed by the carrier separation measurement, and can be explained by the band structure of the gate stack. The source/drain current ISD that corresponds to the hole current dominates the leakage current under inversion region, while the substrate current IB that indicates the electron current dominates the leakage current under accumulation region. All leakage currents can be categorized by fitting to be of Frenkel-Poole type. Secondly, we have studied the NBTI mechanism and AC dynamic stressing of the polysilicon gate HfO2 MOSFETs, with and without F incorporation. △Vth is primarily caused by the charge traps in the HfO2 dielectric, not by the interfacial degradation. F incorporation is effective in suppressing △Nit as well as △Not, thus improving threshold voltage instability. For traditional SiO2 gate dielectric, both △Vth and △Nit are improved by fluorine incorporation, maintaining almost the same activation energies of about 0.2 eV. Similar trends. 28.

(43) are observed in our devices. The activation energy of △Vth is 0.08 eV and that of △Nit is 0.14 eV for both devices. Fluorine is found to be able to electrically passivate traps without changing the NBTI mechanism. AC dynamic stressing provides more realistic and precise prediction in estimating device reliability and charging dynamics in high-k HfO2. The experimental results show that threshold voltage shifts toward more negative voltage in DC stress, but shifts toward more positive voltage under AC unipolar stress. This is believed to be due to less hole charge trapping during on-ptime. The interface trap generation depends weakly on both frequency and duty cycle. Instead of interface trap, the bulk trap of HfO2 eventually plays a preponderant role during AC stress. Finally, we have clearly shown that plasma charging damage introduces more hole traps in the HfO2/SiON gate stack, thus aggravating the NBTI. F incorporation can significantly reduce the impact of plasma charging effect. Suppressing the traps in bulk is important for pMOSFETs with HfO2/SiON gate stack. Fluorine incorporation is found to be an excellent technique to improve BTI immunity and strengthen the immunity against plasma charging damage, thus enhances high-k devices’ stability and reliability.. 29.

(44) 4-2 Future Work It is generally conceived that the introduction of high-k gate dielectrics is inevitable for the technology nodes of 50 nm and beyond, in order to satisfy the stand-by power requirement without sacrificing metal oxide semiconductor field effect transistor (MOSFET) performance. HfO2 is considered as one of the most promising high-k dielectrics. However, threshold voltage instability and inadequate mobility of HfO2 MOSFETs are major issues that remain to be solved. For the threshold voltage instability issue, we found that the exponential value of △Vth for pMOSFETs with HfO2 gate dielectric is voltage and temperature dependent due to charge trapping in bulk HfO2. More efforts on the model of time evolution of Vth instability, so that we could extrapolate ten years lifetime for devices by this model, are necessary. Introduction of the strained silicon could enhance channel mobility while locally strained pMOSFETs with HfO2 gate dielectric have not yet been reported. More research efforts are needed to understand channel mobility and reliability of this structure, and their impacts on future ULSI technology.. 30.

(45) Reference [1] See http://public.itrs.net/for most recent updates to the International Technology Roadmap for Semiconductors. [2] C. S. Kang, H. Cho, R. Choi, Y. Kim, C. Y. Kang, S. J. Rhee, C. Choi, M. S. Akbar, and J. C. Lee, “The electrical and material characterization of hafnium oxynitride gate dielectrics with TaN-gate electrode,” IEEE Trans. Electron Devices, vol. 51, pp. 220-227, Feb 2004. [3] C. S. Kang, H. Cho, K. Onishi, R. Choi, Y. H. Kim, R. Nieh, J. Han, S. Krishnan, A. Shahriar, and J. C. Lee, “Nitrogen concentration effects and performance improvement of MOSFETs using thermally stable HfOxNy gate dielectrics,” in IEDM Tech. Dig., 2002, pp. 865-868. [4] T. Iwamoto, T. Ogura, M. Terai, H. Watanabe, N. Ikarashi, M. Miyamura, T. Tatsumi, M. Saitoh, A. Morioka, K. Watanabe, Y. Saito, Y. Yabe, T. Ikarashi, K. Masuzaki, Y. Mochizuki, and T. Mogami, “A highly manufacturable low power and high speed HfSiO CMOS FET with dual Poly-Si gate electrodes, ” in IEDM Tech. Dig., 2003, pp. 639-642. [5] Y. Kim, H. J. Lim, H. Jung, J. Lee, J. Park, S. K. Han, J. H. Lee, S. Doh, J. P. Kim, N. I. Lee, Y. Chung, H. Y. Kim, N. K. Lee, S. Ramanathan, T. Seidel, M. Boleslawski, G. Irvine, B. Kim, H. Lee, and H. Kang, “Characteristics of ALD HfSiOx using new Si precursors for gate dielectrics applications,” in IEDM Tech. Dig., 2004, pp. 511-514.. 31.

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(47) Yamamoto, T. Horikawa, T. Nabatame, and A. Toriumi, “CARRIER SEPARATION ANALYSIS FOR CLARIFYING LEAKAGE MECHANISM IN UNSTRESSED AND STRESSED HFALOX/SIO2 STACK DIELECTRIC LAYERS,” IEEE Reliability Physics Symposium, pp. 188-193, 2004. [12] M. Houssa, M. Naili, V. V. Afanas’ev, M. M. Heyns, and A. Stesmans, “Electrical and Physical Characterization of High-K Dielectric Layers,” in Tech. Dig. Symp. on VLSI Technology, pp. 196-199, 2001. [13] W. J. Zhu, Tso–Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di, “Current Transport in Metal/Hafnium Oxide/Silicon Structure, ” IEEE Electron Device Lett., Vol. 23, pp. 97-99, Feb 2002. [14] T. Yamaguchi, H. Satake, N. Fukushima, and A. Toriumi, “Band Diagram and Carrier Conduction. Mechanism. in. ZrO2/Zr-silicate/Si. MIS. Structure. Fabricated. by. Pulsed-laser-ablation Deposition,” in IEDM Tech. Dig., pp. 19-22, 2000. [15] S. Zafar, A. Callegari, E. gusev, and M. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectrics, ” J. Appl. Phys., vol. 93, pp. 9298-9303, 2003. [16] J. Zhu, T. P. Ma, S. Zafar, and T. Tamagawa, “Charge trapping in ultrathin hafnium oxide,” IEEE Electron Device Lett., vol. 23, pp. 597-599, Oct. 2002. [17] E. P. Gusev and C. P. D’Emic, “Charge trapping in HfO2 high-k gate stacks,” Appl. Phys.. 33.

(48) Lett., vol. 83, pp. 5223-5225, 2003. [18] A. Kerber, E. Carter, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, “Characterization of VT instability in SiO2/HfO2 gate dielectrics,” Proc. 41th Int. Reliability Physics Symp, Texas, 2003, p. 41. [19] A. Shanware, M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, J. McPherson, and L. Colombo, “Characterization and Composition of the Charge Trapping in HfSiON and HfO2 Gate Dielectrics,” in IEDM Tech. Dig., pp. 939-942, 2003. [20] C. H. Liu, M. T. Lee, C. Y. Lin, J. Chen, K. Schruefer, J. Brighten, N. Rovedo, T. B. Hook, M. V. Khare, S. F. Huang, C. Wann, T. C. Chen, and T. H. Ning, “Mechanism and process dependence of negative bia temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics,” in IEDM Tech. Dig., pp. 861-864, 2001. [21] K. O. Jeppson and C. M. Svensson, “Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices,” J. Appl. Phys., vol. 48, pp. 2004-2014, 1977. [22] K. Onishi, R. Choi, C. S. Kang, Hag–Ju Cho, Y. H. Kim, R. E. Nieh, J. Han, S. A. Krishnan, M. S. Akbar, and Jack C. Lee, “Bias-Temperature Instabilities of Polysilicon Gate HfO2 MOSFETs,” IEEE Trans. Electron Devices, vol. 50, pp. 1517-1524, June 2003. [23] Jack C. Lee, “Hf-based High-K Dielectrics,” IEEE IWGI, 2003, pp. 4-9.. 34.

(49) [24] Y. H. Kim, K. Onishi, C. S. Kang, R. Choi, H. –J. Cho, S. Krishnan, and Jack C. Lee, “Dynamic Reliability Characteristics of Ultra-Thin HfO2,” Proc. 41th Int. Reliability Physics Symp, Texas, 2003, p. 46. [25] Calvin T. Gabriel, “Gate Oxide Damage from Polysilicon Etching,” J. Vac. Sci. Technol., B 9 (2), pp. 370, 1991. [26] E. Casta’n, A. de Dios, L. Bailo”n, and J. Barbolla, E. Cabruja, C. Dominguez, and E. Lora-Tamayo, “Characterization of the Electrical Damage due to Polysilicon RIE (SF6 + Cl2 Plasma) Etching,” J. Electrochem. Soc., vol. 139, No. 1, pp. 193, 1992. [27] Bing–Yue Tsui, Shunn–Her Liu, Geeng–Lih, Jau–Hwang Ho, Chia–Haur Chang and Chin–Yuan Lu, “Recovery Phenomenon and Local Field Sensitivity on Wafer Charge-up Effect of Magnetically Enhanced Reactive Ion Etch System,” IEEE Electron Device Lett., Vol. 16, p. 64, 1995. [28] S. Fang, S. Murakawa, and James P. McVittie, “Modeling of Oxide Breakdown from Gate Charging During Resist Ashing,” IEEE Trans. Electron Device, no. 11, p. 1848, 1994. [29] C. –C. Chen, H. –C. Lin, C. –Y. Chang, C. –C. Huang, C. –H. Chien, T. –Y. Huang and M. –S. Liang “Improved Plasma Charging Immunity in Ultra-Thin Gate Oxide with Fluorine. and. Nitrogen. Implantation,”. International. Process-Induced Damage, pp. 121-124, Jan 2000.. 35. Symposium. on. Plasma.

(50) [30] C. C. Chen, H. C. Lin, C. Y. Chang, M. S. Liang, C. H. Chien, S. K. Hsien, and T. Y. Huang, “Improved immunity to plasma damage in ultrathin nitrided oxides,” IEEE Electron Device Lett., Vol. 21, pp. 15-17, Jan 2000. [31] C.. E.. Blat,. E.. H.. Nicolian. and. E.. H.. Poindexter,. “Mechanism. of. negative-bias-temperature instability,” J. Appl. Phys. Vol. 69, pp. 1721-1720, 1991 [32] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai and T. Horiuchi, “ The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling,” in Tech. Dig. Symp. on VLSI Technology, pp. 73-74, 1999. [33] T. Yamamoto, K. Uwasawa and T. Mogami, “Bias temperature instability in scaled p+ polysilicon gate p-MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, pp. 921-926, 1999. [34] N. Kimizuka, K. Yamaguchi, K. Imai, T. Lizuka, C. T. Liu, R. C. Keller and T. Horiuchi, “NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-µm gate CMOS generation,” in Tech. Dig. Symp. on VLSI Technology, pp.92-93, 2000.. 36.

(51) ITRS 2004 Year of Production. 2004. 2005. 2006. 2007. 2008. 1.2. 1.1. 1.0. 0.9. 0.8. 0.8. 0.7. 0.7. 0.4. 0.4. 450. 520. 600. 930. 1100. EOT (physical) for high-performance (nm) Electrical thickness adjustment for gate depletion and inversion layer effects (nm) Nominal gate leakage current density limit (at 25°C) (A/cm2). Manufacturable solutions are known Manufacturable solutions are NOT known Table 1-1 2004 International Technology Roadmap for Semiconductors. The color shade means the solution known and unknown for physical limit.. 37.

(52) z z z z z z z z z z z. Standard LOCOS process RCA clean and HF-last dip RTA 700 oC in N2O ambient ~ SiON 0.7nm MOCVD of 3nm HfO2 (500 oC) PDA 700 oC 20 sec in N2 ambient Poly-Si deposition 200nm and patterning (no PR removal) Split (F implant, Dose:2E15cm-2, E:10Kev, Tilt:0 degree) S/D implant, followed by PR removal Dopant activation: 950 oC, 20 sec Passivation then metallization Sintering in FG: 400 oC, 30 min. Fig. 2-1. Process flow.. HP 81110A Pulse Generator. p+ Poly-Si p+ Source. h+. p+ Drain. Switch GPIB. en-substrate Vr. Fig. 2-2. HP 4156. Basic experimental setup of charge pumping measurement.. 38.

(53) Capacitance (µF/cm2). 2.0 w/o F w F. 1.6. 20µmx20µm. 1.2. EOTinv. 0.8. w/o F w F. 2.29 nm. 0.4 -2. Fig. 2-3. 2.25 nm. -1. 0 Vg (V). C-V curves for pMOSFETs.. 39. 1. 2.

(54) Id (A). Gm (µs). 10-4 100 -5 10 w/o F 10-6 80 w F -7 10 L/W = 1/10µm -8 10 60 -9 10 10-10 40 Vth -11 10 w/o F -0.98 V 10-12 20 w -1.01 V -13 10 10-14 0 -2.0 -1.5 -1.0 -0.5 0.0 Vg (V) (a). Probability(%). 99 90. w/o F w F. 70 50 30 10 1 0.8. 0.9. 1.0 1.1 |Vth| (V). 1.2. (b) Fig. 2-4. (a) Pre-stress Id-Vg and Gm-Vg characteristics for fresh p-channel devices, (b) Cumulative probability of the threshold voltage (Vth).. 40.

(55) 50 40 Id (10-5A). Vg - Vt = −1.2 V. w/o F w F. 30. −0.9 V. 20 −0.6 V. 10. −0.3 V. 0 0.0. Fig. 2-5. -0.5. -1.0 Vd (V). -1.5. Pre-stress Id-Vd characteristics for fresh p-channel devices.. L/W = 1/10µm Fix Amp = 1.2 V. w/o F w F. 8. 2. Nit (10 /cm ). 10. 10. 6 4. S.S = 77.1. 2 0 -0.5. Fig. 2-6. S.S = 76.8. solid : Icp dash : IS/D. 0.0. 0.5 Vgh (V). 1.0. Pre-stress interface trap density (Nit) characteristics for fresh p-channel devices.. 41.

(56) Ig (A) Fig. 2-7. 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 -6. T = 25 oC w/o F - −Vg w/o F - +Vg. -4. -2. w. F - −Vg. w. F - +Vg. 0 2 Vg (V). 4. 6. Gate leakage current versus gate bias for fresh p-channel devices at room temperature.. 42.

(57) Current (A). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12. PMOSFET L/W=1/10µm. T = 25 C o. w/o F-IG w/o F-ISD w/o F-IB. IG = ISD IB. -6. -5. -4. -3 -2 Vg (V). -1. 0. Current (A). (a). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12. PMOSFET L/W=1/10µm. T = 25 oC w. F-IG. w. F-ISD. w. F-IB. IG = ISD IB. -6. -5. -4. -3 -2 Vg (V). -1. 0. (b) Fig. 2-8. Carrier separation under inversion region (a) w/o F sample, and (b) with F sample.. 43.

(58) Current (A). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12. PMOSFET L/W=1/10µm I G = IB. T = 25 oC. w/o F-IG. ISD. 0. 1. 2. 3 4 Vg (V). w/o F-ISD w/o F-IB. 5. 6. Current (A). (a). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12. PMOSFET L/W=1/10µm T = 25 oC. IG = IB. ISD. 0. 1. 2. 3 4 Vg (V). w. F-IG. w. F-ISD. w. F-IB. 5. 6. (b) Fig. 2-9. Carrier separation under accumulation region (a) w/o F sample, and (b) with F sample.. 44.

(59) PMOSFET p+ Gate. eIB (+) HfO2. h+ I SD (+). n-Sub. Interfacial layer (a). Hole Vg (-) injection. (+)I SD. electron injection. +. P. P+. N. Hole current. P+. (+)IB. Inversion Layer. (b). Fig. 2-10 p+-gated pMOSFET with HfO2/SiON gate stack under inversion region (a) Band diagrams, and (b) Schematic illustration of carrier separation experiment.. 45.

(60) PMOSFET eIB (-). n-Sub. p+ Gate HfO2 h+ I SD (-) Interfacial layer (a). Hole Vg (+) injection. (-)I SD. electron injection. +. P. P+. N. Hole current. P+. (-)IB. Inversion Layer. (b). Fig. 2-11 p+-gated pMOSFET with HfO2/SiON gate stack under accumulation region (a) Band diagrams, and (b) Schematic illustration of carrier separation experiment.. 46.

(61) Ig (A). 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 -6. −Vg. +Vg 25 oC 75 oC 100 oC 125 oC. w/o F. -4. -2. 0 2 Vg (V). 4. 6. Ig (A). (a). 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 -6. −Vg. +Vg 25 oC 75 oC 100 oC 125 oC. with F. -4. -2. 0 2 Vg (V). 4. 6. (b) Fig. 2-12 Gate leakage current versus gate bias for fresh p-channel devices at various temperatures (a) w/o F sample, and (b) with F sample.. 47.

(62) -16. ln (JSD/E). -18 -20. 25 oC Frenkel-Poole 75 oC emission 100 oC 125 oC. T. -22. w/o F Inversion Region φB = 0.98 eV. -24. 3000 3200 3400 3600 3800 4000 1/2 1/2 E (V/cm) (a). -16. ln (JSD/E). -18 -20. 25 oC Frenkel-Poole 75 oC emission 100 oC 125 oC. T. -22. with F Inversion Region φB = 1 eV. -24. 3000 3200 3400 3600 3800 4000 1/2 1/2 E (V/cm) (b) Fig. 2-13 Conduction mechanism for source/drain current fitting under inversion region (a) w/o F sample, and (b) with F sample.. 48.

(63) -16. ln (JB/E). -18 -20. 25 oC Frenkel-Poole 75 oC emission 100 oC 125 oC. -22. T w/o F Inversion Region φB = 1.16 eV. -24 -26. 3200 3400 3600 3800 4000 1/2 1/2 E (V/cm) (a). -16. ln (JB/E). -18 -20. 25 oC Frenkel-Poole 75 oC emission 100 oC 125 oC. -22. T with F Inversion Region φB = 1.17 eV. -24 -26. 3200 3400 3600 3800 4000 1/2 1/2 E (V/cm) (b) Fig. 2-14 Conduction mechanism for substrate current fitting under inversion region (a) w/o F sample, and (b) with F sample.. 49.

(64) 5nm. 31.8Å 11.4Å. Fig. 2-15 HRTEM image of a device with HfO2/SiON gate stack.. 50.

(65) 10-8 w/o F w/o small stress. 10-10. Id (A). Id (A). 10-9 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 -2.0. -1.5. -1.0. -0.5. forward-1 reverse-1 forward-2 reverse-2. 0.0. Vg (V). 10-11. -0.8. -0.7 Vg (V). -0.6. (a). 10-8 w/o F with small stress. 10-10. Id (A). Id (A). 10-9 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 -2.0. -1.5. -1.0. -0.5. forward-1 reverse-1 forward-2 reverse-2. 0.0. Vg (V). 10-11 -0.8. -0.7 Vg (V). -0.6. (b) Fig. 2-16 Id-Vg characteristics for p+-gate pMOSFET without F incorporation (a) w/o small stress, and (b) with small stress.. 51.

(66) 10-8. with F w/o small stress. 10-10. Id (A). Id (A). 10-9 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 -2.0. -1.5. -1.0. -0.5. forward-1 reverse-1 forward-2 reverse-2. 0.0. Vg (V). 10-11 -0.8. -0.7 Vg (V). -0.6. (a). 10-8. with F with small stress. 10-10 10-11. Id (A). Id (A). 10-9 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 -2.0. -1.5. -1.0. -0.5. forward-1 reverse-1 forward-2 reverse-2. 0.0. Vg (V). -0.8. -0.7 Vg (V). -0.6. (b) Fig. 2-17 Id-Vg characteristics for p+-gate pMOSFET with F incorporation (a) w/o small stress, and (b) with small stress.. 52.

(67) e. h h h. hh hh h h. h h. Fresh IdVg. h h h h. h h hh. IdVg_1. Stress Off Time. h h. h. hh hh h h h h. h h h. Fig. 2-18 Schematic illustrations for possible fast charging effects (FCE).. Vg < 0. p+ Poly-Si p+ Drain. p+ Source. n-substrate. Fig. 2-19 Configuration for NBTI stressing.. 53.

(68) Id (A). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 -2.0. Vg = − 4 V T = 25 oC w/o F t=0s t = 1000 s. -1.5. -1.0 -0.5 Vg (V). 0.0. (a). Id (A). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 -2.0. Vg = − 4 V T = 25 oC with F t=0s t = 1000 s. -1.5. -1.0 -0.5 Vg (V). 0.0. (b) Fig. 2-20 Id-Vg characteristics for p+-gate pMOSFETs before stress and after stress 1000 s at 25 oC (a) w/o F sample, and (b) with F sample.. 54.

(69) 0 − 3.5 V. ∆Vth (mV). -50 -100 T = 25 C o. -150. −4V. w/o-F w- F Vg = − 3.5 V. -200 -250 10-1. Vg = − 4 V. 100. 101 102 103 Stress Time (s). 104. (a). 400 w/o-F w- F. −∆Vth (mV). Vg = − 3.5 V. α t0.12. Vg = − 4 V α t0.12. 100. α t0.04 α t0.03. 10-1. 100. 101 102 103 Stress Time (s). 104. (b) Fig. 2-21 Threshold voltage shift as a function of stress time, stressed at 25 oC, Vg =-3.5 V &-4 V with (a) linear scale, and (b) logarithm scale.. 55.

數據

Table 1-1  2004 International Technology Roadmap for Semiconductors.
Fig. 2-3  C-V curves for pMOSFETs.
Fig. 2-6  Pre-stress interface trap density (N it ) characteristics for fresh p-channel devices
Fig. 2-7  Gate leakage current versus gate bias for fresh p-channel devices at room  temperature
+7

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