Basic Storage Elements

Recall our statement at the beginning of Section 3.3 that there are two kinds of logic structures, those that involve the storage of information and those that do not. We have discussed three examples of those that do not: the decoder, the mux, and the full adder. Now we are ready to discuss logic structures that do include the storage of information.

3.4.1 The R-S Latch

A simple example of a storage element is the R-S latch. It can store one bit of information. The R-S latch can be implemented in many ways, the simplest being

3.4 Basic Storage Elements

the one shown in Figure 3.18. Two 2-input NAND gates are connected such that the output of each is connected to one of the inputs of the other. The remaining inputs S and R are normally held at a logic level 1.

The R-S latch works as follows: We start with what we call the quiescent (or quiet) state, where inputs S and R both have logic value 1. We consider first the case where the output a is 1. Since that means the input A equals 1 (and we know the input R equals 1 since we are in the quiescent state), the output b must be 0.

That, in turn, means the input B must be 0, which results in the output a equal to 1. As long as the inputs S and R remain 1, the state of the circuit will not change.

We say the R-S latch stores the value 1 (the value of the output a).

If, on the other hand, we assume the output a is 0, then the input A must be 0, and the output b must be 1. This, in turn, results in the input B equal to 1, and combined with the input S equal to 1 (again due to quiescence) results in the output a equal to 0. Again, as long as the inputs S and R remain 1, the state of the circuit will not change. In this case, we say the R-S latch stores the value 0.

The latch can be set to 1 by momentarily setting S to 0, provided we keep the value of R at 1. Similarly, the latch can be set to 0 by momentarily setting R to 0, provided we keep the value of 5 at 1. We use the term set to denote setting a variable to 0 or 1, as in "set to 0" or "set to 1." In addition, we often use the term clear to denote the act of setting a variable to 0.

If we clear S, then a equals 1, which in turn causes A to equal 1. Since R is also 1, the output at b must be 0. This causes B to be 0, which in turn makes a equal to 1. If we now return S to 1, it does not affect a, since B is also 0, and only one input to a NAND gate must be 0 in order to guarantee that the output of the NAND gate is 1. Thus, the latch continues to store a 1 long after S returns to 1.

In the same way, we can clear the latch (set the latch to 0) by momentarily setting R to 0.

We should also note that in order for the R-S latch to work properly, one must take care that it is never the case that both S and R are allowed to be set to 0 at the same time. If that does happen, the outputs a and b are both 1, and the final state of the latch depends on the electrical properties of the transistors making up the gates and not on the logic being performed. How the electrical properties of the transistors will determine the final state in this case is a subject we will have to leave for a later semester.

Figure 3.18 An R-S latch

3.4.2 The Gated D Latch

To be useful, it is necessary to control when a latch is set and when it is cleared.

A simple way to accomplish this is with the gated latch.

Figure 3.19 shows a logic circuit that implements a gated D latch. It consists of the R-S latch of Figure 3.18, plus two additional gates that allow the latch to be set to the value of D, but only when WE is asserted. WE stands for write enable.

When WE is not asserted (i.e., when WE equals 0), the outputs S and R are both equal to 1. Since S and R are also inputs to the R-S latch, if they are kept at 1, the value stored in the latch remains unchanged, as we explained in Section 3.4.1.

When WE is momentarily asserted (i.e., set to 1), exactly one of the outputs S or R is set to 0, depending on the value of D. If D equals 1, then S is set to 0. If D equals 0, then both inputs to the lower NAND gate are 1, resulting in R being set to 0. As we saw earlier, if S is set to 0, the R-S latch is set to 1. If R is set to 0, the R-S latch is set to 0. Thus, the R-S latch is set to 1 or 0 according to whether D is 1 or 0. When WE returns to 0, S and R return to 1, and the value stored in the R-S latch persists.

3.4.3 A Register

We have already seen in Chapter 2 that it is useful to deal with values consisting of more than one bit. In Chapter 5, we will introduce the LC-3 computer, where most values are represented by 16 bits. It is useful to be able to store these larger numbers of bits as self-contained units. The register is a structure that stores a number of bits, taken together as a unit. That number can be as large as is useful or as small as 1. In the LC-3, we will need many 16-bit registers, and also a few one-bit registers. We will see in Figure 3.33, which describes the internal structure of the LC-3, that PC, IR, and MAR are all 16-bit registers, and that N, Z, and P are all one-bit registers.

Figure 3.20 shows a four-bit register made up of four gated D latches. The four-bit value stored in the register is Qi, Qi, Qo- The value D³, D², D^u Do can be written into the register when WE is asserted.

Note: A common shorthand notation to describe a sequence of bits that are numbered as just described is Q[3:0]. That is, each bit is assigned its own bit number. The rightmost bit is bit [0], and the numbering continues from right to

D

W E

Figure 3 . 1 9 A gated D latch

3.5 The Concept of Memory

Figure 3 . 2 0 A four-bit register

left. If there are n bits, the leftmost bit is bit [n — 1]. For example, in the following 16-bit pattern,

0011101100011110

bit [15] is 0, bit [14] is 0, bit [13] is 1, bit [12] is 1, and so on.

We can designate a subunit of this pattern with the notation Q[l:r], where I is the leftmost bit in the subunit and r is the rightmost bit in the subunit. We call such a subunit a field.

In this 16-bit pattern, if A[15:0] is the entire 16-bit pattern, then, for example:

A [ 15 : 12] is 0011 A [ 13 : 7] is 1110110 A [2 : 0] is 110

A [ 1:1] is 1

We should also point out that the numbering scheme from right to left is purely arbitrary. We could just as easily have designated the leftmost bit as bit [0] and numbered them from left to right. Indeed, many people do. So, it is not important whether the numbering scheme is left to right or right to left. But it is important that the bit numbering be consistent in a given setting, that is, that it is always done the same way. In our work, we will always number bits from right to left.