Instruction Processing

instruction register (IR) is also an input to the finite state machine since what LC-3 instruction is being processed determines what activities must be carried out. The program counter (PC) is also a part of the control unit; it keeps track of the next instruction to be executed after the current

instruction finishes.

Note that all the external outputs of the finite state machine in Figure 4.3 have arrowheads that are not filled in. These outputs control the processing throughout the computer. For example, one of these outputs (two bits) is ALUK, which controls the operation performed in the ALU (add, and, or not) during the current clock cycle. Another output is GateALU, which determines whether or not the output of the ALU is provided to the processor bus during the current clock cycle.

The complete description of the data path, control, and finite state machine for one implementation of the LC-3 is the subject of Appendix C.

4.3 Instruction Processing

The central idea in the von Neumann model of computer processing is that the program and data are both stored as sequences of bits in the computer's memory, and the program is executed one instruction at a time under the direction of the control unit.

4.3.1 The Instruction

The most basic unit of computer processing is the instruction. It is made up of two parts, the opcode (what the instruction does) and the operands (who it is to do it to). In Chapter 5, we will see that each LC-3 instruction consists of 16 bits (one word), numbered from left to right, bit [15] to bit [0]. Bits [15:12] contain the opcode. This means there are at most 24 distinct opcodes. Bits [11:0] are used to figure out where the operands are.

The ADD Instruction The ADD instruction requires three operands: two source operands (the data that is to he added) and one destination operand (the sum that is to be stored after the addition is performed). We said that the processing unit of the LC-3 contained eight registers for purposes of storing data that may be needed later. In fact, the ADD instruction requires that at least one of the two source operands (and often both) is contained in one of these registers, and that the result of the ADD is put into one of these eight registers. Since there are eight registers, three hits are necessary to identify each register. Thus the 16-bit LC-3 ADD instruction has the following form (we say format):

The 4-hii opcode lor ADD. contained in hits 115:121. is 0001. Hits 1 1 i d e n t i f y the location Lo he used for storing ihe result, in this case register 6 (R6). Bits |K:ft| and hits 12:0| identify the regislers lo he used lo obtain Ihe source operands, in this case R2 and Rft. Mils 15:31 have a purpose that it is not necessary lo understand in the context of this example. We will save Ihe explanation of hils [5:31 for Section 5.2.

Thus, the instruction we have just encoded is interpreted, "Add the contents of register 2 (R2) to the contents of register 6 (Rft) and store the result back into register 0 ( K 6 i ;

The LDR Instruction The LDR instruction requires two operands. LD stands for load, which is computerese for "go to a particular memory location, read the value that is contained there, and store it in one of the registers." The two operands that are required are the value to be read from memory and the destination register, which will contain that value after the instruction is processed. The R in LDR identifies the mechanism that will be used to calculate the address of the memoiy location to be read. That mechanism is called the addressing mode, and the particular addressing mode identified by the use of the letter R is called Base+offset. Thus, the 16-bit LC-3 LDR instruction has the following format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 0

LDR R2 R3 6 The four-bit opcode for LDR is 0110. Bits [11:9) identify the register that will contain the value read from memory after the instruction is executed. Bits [8:0] are used to calculate the address of the location to be read. In particular, since the addressing mode is BASE+offset, this address is computed by adding the 2's complement integer contained in bits [5:0| of the instruction to the contents of the register specified by bits 18:6]. Thus, the instruction we have just encoded is interpreted: "Add the contents of R3 to the value 6 to form the address of a memory location. Load the contents stored in that memory location into R2."

4.3.2 The Instruction Cycle

Instructions are processed under the direction of the control unit in a very system-atic, step-by-step manner. The sequence of steps is called the instruction cycle, and each step is referred to as a phase. There are fundamentally six phases to the instruction cycle, although many computers have been designed such that not all instructions require all six phases. We will discuss this momentarily.

But first, w e will examine the six phases of the instruction cycle:

FETCH DECODE

EVALUATE ADDRESS FETCH OPERANDS

4.3 Instruction Processing 1 0 5

EXECUTE STORE RESULT

The process is as follows (again refer to Figure 4.3, our simplified version of the LC-3 data path):

FETCH

The FETCH phase obtains the next instruction from memory and loads it into the instruction register (IR) of the control unit. Recall that a computer program consists of a collection of instructions, that each instruction is represented by a sequence of bits, and that the entire program (in the von Neumann model) is stored in the computer's memory. In order to carry out the work of the next instruction, we must first identify where it is. The program counter (PC) contains the address of the next instruction. Thus, the FETCH phase takes multiple steps:

First the MAR is loaded with the contents of the PC.

Next, the memory is interrogated, which results in the next instruction being placed by the memory into the MDR.

Finally, the IR is loaded with the contents of the MDR.

We are now ready for the next phase, decoding the instruction. However, when the instruction cycle is complete, and we wish to fetch the next instruction, we would like the PC to contain the address of the next instruction. Therefore, one more step the FETCH phase must perform is to increment the PC. In that way, at the completion of the execution of this instruction, the FETCH phase of the next instruction will load into IR the contents of the next memory location, provided the execution of the current instruction does not involve changing the value in the PC.

The complete description of the FETCH phase is as follows:

Step 1: Load the MAR with the contents of the PC, and simultaneously increment the PC.

Step 2: Interrogate memory, resulting in the instruction being placed in the MDR.

Step 3: Load the IR with the contents of the MDR.

Each of these steps is under the direction of the control unit, much like, as we said previously, the instruments in an orchestra are under the control of a conductor's baton. Each stroke of the conductor's baton corresponds to one machine cycle. We will see in Section 4.4.1 that the amount of time taken by each machine cycle is one clock cycle. In fact, we often use the two terms interchangeably. Step 1 takes one machine cycle. Step 2 could take one machine cycle, or many machine cycles, depending on how long it takes to access the computer's memory. Step 3 takes one machine cycle. In a modern digital computer, a machine cycle takes a very small fraction of a second. Indeed, a 3.3-GHz Intel Pentium IV completes 3.3. billion

machine cycles (or clock cycles) in one second. Said another way, one machine cycle (or clock cycle) takes 0.303 billionths of a second (0.303 nanoseconds).

Recall that the light bulb that is helping you read this text is switching on and off at the rate of 60 times a second. Thus, in the time it takes a light bulb to switch on and off once, today's computers can complete 55 million machine cycles!

DECODE

The DECODE phase examines the instruction in order to figure out what the microarchitecture is being asked to do. Recall the decoders we studied in Chap-ter 3. In the LC-3, a 4-to-16 decoder identifies which of the 16 opcodes is to be processed. Input is the four-bit opcode IR[15:12]. The output line asserted is the one corresponding to the opcode at the input. Depending on which output of the decoder is asserted, the remaining 12 bits identify what else is needed to process that instruction.

EVALUATE ADDRESS

This phase computes the address of the memory location that is needed to process the instruction. Recall the example of the LDR instruction: The LDR instruction causes a value stored in memory to be loaded into a register. In that example, the address was obtained by adding the value 6 to the contents of R3. This calculation was performed during the EVALUATE ADDRESS phase.

FETCH OPERANDS

This phase obtains the source operands needed to process the instruction. In the LDR example, this phase took two steps: loading MAR with the address calculated in the EVALUATE ADDRESS phase, and reading memory, which resulted in the source operand being placed in MDR.

In the ADD example, this phase consisted of obtaining the source operands from R2 and R6. (In most current microprocessors, this phase [for the ADD instruction] can be done at the same time the instruction is being decoded. Exactly how we can speed up the processing of an instruction in this way is a fascinating subject, but one we are forced to leave for later in your education.)

EXECUTE

This phase carries out the execution of the instruction. In the ADD example, this phase consisted of the single step of performing the addition in the ALU.

STORE RESULT

The final phase of an instruction's execution. The result is written to its designated destination.

Once the sixth phase (STORE RESULT) has been completed, the control unit begins anew the instruction cycle, starting from the top with the FETCH phase.

4.4 Changing the Sequence of Execution 1 0 7

Since the PC was updated during the previous instruction cycle, it contains at this point the address of the instruction stored in the next sequential memory location.

Thus the next sequential instruction is fetched next. Processing continues in this way until something breaks this sequential flow.

A D D leax I, edx This is an example of an Intel x86 instruction that requires all six phases of the instruction cycle. All instructions require the first two phases, FETCH and DECODE. This instruction uses the eax register to calculate the address of a memory location (EVALUATE ADDRESS). The contents of that memory location are then read (FETCH OPERAND), added to the contents of the edx register (EXECUTE), and the result written into the memory location that origiuallx contained the lirst source .i|»cr;md (STORE RESULT).

The I.C-3 ADD and LDR instructions do not require all six phases. In particular, the ADD instruction does not require an EVALUATE ADDRESS phase. The LDR instruction does not require an EXECUTE phase.