Buffer Modeling

In this stage, we build a lookup table for various type of buffer blocks based on the number of the cells it connected. As mentioned in Chapter 2, buffer blocks can share the clearance region for minimal spacing between ESD structures and active devices because of foundry rules. As a result, a buffer block with more single buffer grouped

together can reduce more area cost. In order to fit with the style of standard cell design and simplify the problem, we build our I/O buffer blocks with the same hight as the original row height of standard cell design, although real I/O buffer block may exceed the row height of standard cell design. The way we model our I/O buffer block is shown in Figure 3.2. For example, the I/O buffer block which clustered 4 buffers mean a signal buffer block which is able to drive 4 cells.

Figure 3.2: The model of our I/O buffer block

In the process of buffer modeling, we select the type of buffer block for every input/output based on the number of cells it connected. For example, an input pin connected with 8 cells will select a buffer block which is fit with the ability to drive 8 cells. In real design issue, the I/O buffer for output usually has bigger area than input because of the requirement for driven ability. In our buffer model, we simply treat those two kind of I/O buffer block as the same type. The size of each buffer block comes with two part. One is the minimal spacing between ESD structures and active devices. The other is the area of the buffer block itself with

ESD structure, latch-up ring, testing logic and driver circuit. The size of buffer block used in MCNC benchmark struct is shown in Figure 3.3.

Figure 3.3: The size of buffer block used in MCNC benchmark struct

3.2 BufBlockPlacer

In execution of this buffer block placer, we first compute the geometry center of each net then we order the nets by the position of their geometry center from bottom to top then left to right. Second, we determine the size of the buffer block of each net by the table we made in buffer modeling. We place buffer blocks at the geometry center of every net to minimize the longest path from cells to the buffer block and also reduce the interconnection length on the side. We have three operations to place those I/O buffer blocks into the core :

• Cell Squeeze : squeeze away the cell which occupied the location

• Buffer Merge : merge two nearby buffer blocks into a single buffer block

• Local Legalization : legalize the row length of the local rows

We use Squeeze to squeeze the cell away from it’s location and place the buffer in that location until we get enough free space. We use Merge to merge two buffer blocks into one buffer block if they are physically neighbored. Merging two different buffer block together can reduce the total area by our look-up table. After some operations of Squeeze or Merge, the local rows may exceed the constraint of the length of row. We can use Wave to adjust them to maintain the rectangular shape of the chip.

3.2.1 Cell Squeeze

Once we determine the location of the buffer block, we have to move out the cell which occupied the target location. We focus on the movement of the cell while it is been squeezing away. We define that our Squeeze operation has three directions to squeeze cells right, up and down. If we squeeze the cell right, all the cells on the right side of it including the cell itself will shift right. If we squeeze the cell up or down, the cell will move to the target row and take the same operation like squeeze right. The offset distance of shift right is the width of the cell which squeezes. The operation of the Squeeze is shown in Figure 3.4.

We calculate the cost of Squeeze in all three directions by summing up the weight of every cell which have been moved. If the movement of the cell has changed the boundary box of the net it connected, the weight is recorded. The calculation of the weight is shown in Figure 3.5. Squeeze will choose the less cost direction to squeeze the cell. After the operation of Squeeze, the position of cell and free space will be updated to let BufBlockPlacer calculate the free space needed for the buffer block to be placed in. If the free space needed is less than the width of the cell we plan to squeeze, we will simply shift the cells right for the distance of free space needed instead of choosing which direction to squeeze. Once we get enough free space for the buffer block, we place the I/O buffer block into the free space.

Figure 3.4: The Squeeze has three direction to squeeze cells right, up and down

Figure 3.5: Moving the cell at the boundary of the net will change wire length of the net

3.2.2 Local Legalization

After some operations of Squeeze, the length of the certain rows may exceed the constraint of the length of row. We develop a local legalization process which is

inspired by the method used in Mongrel[20] to fix this problem. Once we squeeze some cells away from the positions they belong, we use Wave to move cells in the nearby area to reduce the impact on the change of length of the row caused by the operation of Squeeze. In our legalization procedure, we start with the initial placement (after Squeeze) and then sequentially move each less cost cell to it’s relaxed target location. The key point is that after each move we produce a feasible placement with free space for our buffer block.

In the process of Wave, we set up a wave zone by the x-coordinate of the cell which has been squeezed in and the user-specified parameter W aveRange. If there is any buffer block in the wave zone, we redefine the range of the wave zone to avoid those buffer blocks. As shown in Figure 3.6, we sequentially move each less connectivity cell from the longest row to the shortest row. Every selected cell will move up/down to the cell in the next row and squeeze right the cells which are on the right side of it. The order we squeeze the cell is from bottom to top then left to right. As a result, the move in Wave will not affect the position of the buffer blocks which have been placed.

The method we evaluate the weight of the cell which will be moved up or down are similar to the method we used in Figure 3.5. There are two sources of the weight while moving cell up/down. First, when we move out one cell from the row the cells on the right side of it should be pulled left. At the same time, when this cell move in the next row, the cells on the right side of it should be pushed right. The way we evaluate the weight of first part is shown in Figure 3.7. Second, the width of the cell which will be moved to the other row will affect the efficiency of legalization.

Moving big cell out of the longest row means less legalization process will be needed.

As a result, bigger cell will get lesser weight. We set up a parameter to adjust the ratio of weight between run time and wirelength reduction. We calculate the weight of every cell in the row then we can choose a less cost cell to move up/down.

Figure 3.6: Wave sequentially move cells from min row to max row in the wave zone

Figure 3.7: The weight in wave calculate the wire length cost in the operation pull and push

3.2.3 Buffer Merge

In BufBlockPlacer, some operations like Squeeze and Merge may encounter that two buffers are physically neighbored. In order to reduce as much area as possible, we

use Merge to merge two buffer blocks into one. Due to the share of the clearance region of minimum spacing between ESD structures and active devices, the area of the merged single buffer block is less than the sum of two individual buffer blocks.

We use look-up table to determine the size of the merged buffer block.

3.2.4 The BufBlockPlacer Algorithm

In this section, we present a force-directed algorithm to place the buffer blocks into the location where the longest path from buffer block to the cells is minimized and the connection length is reduced as well. We place the buffer blocks in the order from bottom to top then left to right. As a result, every operation of cell squeeze, local legalization and buffer merge will not affect each other and the position of the placed buffer block will not be modified by the later move.The algorithm of the BufBlockPlacer is shown in Figure 3.8.