C OMPARISON WITH R ELATED W ORKS

Table 5.2 lists the comparison with related works about motion compensation. We only focus on memory bandwidth reduction and interpolator design comparison. This is because memory bandwidth always is bottleneck of motion compensation and interpolator is key module in motion compensation. For another reason, each related works support different specification. We can see our memory bandwidth optimization is better than previous works although our storage is not least. However, our storage size is after trade-off and can get better performance. In terms of interpolator, [10] and [11] use hardware sharing to operate twice to achieve area efficiency. Even though these hardware sharing is suitable for Baseline Profile, but the poor throughput is not meet real-time decode in Main/High Profile. Moreover, our interpolator gate count is very close to these previous work [10] [11] and provide enough throughput performance in Main/High Profile.

Table 5.2 H.264decoder comparison with related work

ISCAS

Interpolator 20,686 15,000 13,027 21,506 11,823 13,201

total 43k 61k 32k 47k N/A 68k

Chapter 6

Conclusion and Future Work

6.1 Conclusion

Motion compensation engine consists of three parts: motion vector generator, interpolator, and weighted predictor. Firstly, motion vector generator needs to support many tools in Main/High Profile. The challenge of motion vector generator is high complexity. We use hardware sharing to deal with double motion vectors, use coordinate mapping method to process direct modes, and merge MBAFF mode LUT and non-MBAFF mode LUT effectively to reduce the complexity. The design of interpolator, 4-parallel separate 1-D architecture gives the most space on high throughput compared with other proposed architectures. Hence, our interpolator is suitable for B slice and our restructured design can significantly reduce area cost. Lastly, weighted predictor located on last stage of motion compensation engine, we use LUT to deal with complicated implicit mode and collocate with interpolator in order to execute operation only occupies one cycle.

The design target of memory bandwidth reduction is to reduce external memory access and improve throughput of motion compensation engine. The proposed reduction strategies of memory bandwidth for motion compensation need 319 pixel storages is after trade-off and own better performance than other works. After applying these strategies, the memory bandwidth requirement can save the required bandwidth about 71~80 %. Moreover, achieve efficient memory access scheduling.

6.2 Future Work

The proposed motion compensator for H.264/AVC standard only supports up to Main/High Profile. If we want to support H.264/SVC/MVC, there are many issues should be taken into account. For example, hierarchical B pictures [18] [19]. In addition, a successor to H.264/AVC, High Efficiency Video Coding (HEVC) [20], is a proposed video compression standard, currently under development. If we want to support HEVC, the subjects such as extended macroblock size (EMS), decoder-side motion vector derivation (DMVD), 2-D non-separable adaptive interpolation filter (AIF), separable AIF, Direction AIF, Competition-based scheme for motion vector selection and coding, and so on tools should be taken into account for a next generation motion compensator.

In terms of memory bandwidth, our proposed mechanism can effectively reduce bandwidth requirement. However, there only focus on one single module in system view.

Hence, there are still many important issues should be considered in order to provide bandwidth reduction in the viewpoint of overall system. For example, when embedded compressor/decompressor is disabled, a smarter SDRAM controller should be designed include scheduled memory accesses.

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Vita

姓名：陳浩民

出生地：台灣省彰化市 出生日期：1977.11.18

學歷： 彰化縣立南興國民小學 彰化縣立彰安國民中學

國立虎尾科技大學 電機工程科

明新科技大學 電機工程系

國立交通大學 電機學院 (電子與光電學程) 碩士班

工作經歷： 太和科技服份有限公司 研發一處 工程師

研發處專案一部 高級工程師

研發處硬碟陣列部 科長

研發處硬碟陣列部 經理