Chapter 4 Formation and Nonvolatile Memory Characteristics of
4.2 Summary II
Table 4-2 is the comparison results of memory characteristic for NC memories in our work. By taking account of the memory window, it indicates no difference for two different processes. A steep (C-V) hysteresis slope and greater endurance characteristic are considered less damage of tunneling oxide during the RTO process.
Sputter in O2 ambiance can avoid over oxidation and degradation by conventional RTO process. A superior memory characteristic in term of retention characteristic is found. It’s considered that less oxygen concentration cause deeper trap level and much trap density due to oxygen vacancy.
Figure 4-1 Schematics of sputter in O2 ambiance process
Figure 4-2 Transmission electron microscope (TEM) analysis of cross-sectional MOIOS structure with MnSiOx NCs by sputter in O2 ambiance process. The diameter and density of the NCs is approximately 6 nm and 2.13×1012 cm-2.
54
Figure 4-3 Capacitance-voltage (C-V) hysteresis of MOIOS structure by (a) sputter in O2, and (b) RTO process. The memory windows of two samples are nearly equal to 1 and 2.5 V under VG-VFB=±5 dash line and ±10 V solid line gate voltage operation, respectively.
Figure 4-4 Endurance characteristics of the NC memory structure by (a) sputter in O2, and (b) RTO process. Pulses condition of VG−VFB= ± 10V for 10ms.
55
Figure 4-5 Retention of the NC memory structure by RTO process is 35%. Charge holding rate of the NC memory structure by sputter in O2 process is 52%.
56
Figure 4-6 Current–density JG as a function of the inverse temperature for SiOx /MnSiOx gate dielectric stacks. The solid lines are fits to the data .
57
Figure 4-7 The trap level of MnSiOx NCs by RTO blue line and sputter in O2 blue line process.
Oxygen Concentration (%)
Trap Level (eV)
Trap density (cm-3) sputter in Ar
ambiance RTO
70 1.26 5.4×1017
sputter in Ar/O2
ambiance RTN
58 1.83 6.6×1017
Table 4-1 Comparisons of oxygen concentration for different process by ESCA analysis
Table 4-2 Comparisons of memory characteristics for different process
58
59
Chapter 5
Multi-Layer Manganese Silicate Nanocrystals Memory
5.1 Formation of Multi-Layer MnSiO
xNCs Memory
5.1.1 Experimental Procedures
Figure 5-1 exhibits schematics of the experimental procedures. The fabrication of NVM structure was started with a thermal dry oxidation at 950°C to form a tunnel oxide about 5 nm on p-type (100) Si wafer which had been removed native oxide and micro-particles by RCA process, and then a 1-nm-thick a-Si and 9-nm-thick Mn0.2Si0.8
served as a charge tapping layer was deposited by reactive sputtering in the Ar/ O2
[24/ 1 SCCM (SCCM denotes cubic centimeter per minute at STP)] ambiance at room temperature. Before the rapid thermal annealing (RTA) process at 800 °C for 30 s in the N2 ambiance, the Mn0.2Si0.8 layer was capped by a 10-nm-thick oxide using a plasma enhanced chemical vapor deposition (PECVD) system at 300°C. The RTN process was performed to cause the self-assembly of MnSiOx nanocrystal in the charge trapping layer. After RTN process, a 20-nm-thick blocking oxide was deposited by PECVD and then deposited Al gate electrodes to form a metal/oxide/insulator/oxide/silicon (MOIOS) structure. Electrical characteristics of the capacitance-voltage (C-V) hysteresis were also measured by HP4284 precision LCR meter with high frequency of 1 MHz. In addition, transmission electron microscope (TEM) and x-ray photoelectron spectroscopy (XPS) were adopted for the microstructure analysis, chemical material analysis of NCs.
60
5.1.2 Comparison of Electrical Characteristics between Multi-Layer and Single-Layer MnSiOx NCs Memories
The cross-sectional TEM image of MOIOS structure containing spherical and separated NCs was shown in Fig.5-2. There are obvious double layer of MnSiOx NCs because Mn diffuse into pre-cap control oxide during RTA process. From TEM analysis, the average diameter of the NCs is approximately 6 nm.
Endurance characteristics of the single and double layer NCs memory structure are shown in Fig.5-3. Pulses conditions are VG−VFB= ± 9V for 10ms. There are no greater differences between single and double NCs memories after 106 P/E cycles.
Fig.5-4. shows capacitance-voltage (C-V) hysteresis of single and double layer NCs memories. The memory windows of two samples are nearly equal to 1 V under VG-VFB=±5 gate voltage operation, respectively. But under VG-VFB=±10 gate voltage operation, the memory windows of double and single layer NCs memories are 4.5V and 2.5V, respectively. Fig. 5-5(a) shows memory windows under gate voltage sweep.
Comparison of Fig. 5-5(b) the electrons capably inject into second layer under high voltage operation as shown in Fig. 5-5(c).
Fig.5-6(a) shows the retention characteristic of double and single layer NCs memories. A simple energy band diagram of single-layer and multi-layer NCs are shown in Fig.5-6(b) and (c). If the electron stored in the traps of the second NC, it difficultly leaks to Si-subtrate. The charge holding rate of double layer NCs memory is better than single layer NCs memory.
5.2 Summary Ⅲ
Multi-layer MnSiOx NCs memory was easily fabricated. It exhibits superior memory characteristics for the application of low-power nanoscaled nonvolatile
61
memory. The nanocrystal can be simple and uniform to fabricate in this study. The memory window of MnSiOx NCs enough to define “1” and “0” states is clearly observed for the nonvolatile memory application. The retention and endurance characteristic are better to be maintained after 10 years and 106 P/E cycles than single layer MnSiOx NCs.
Figure 5-1 Schematics of double layer MnSiOx NCs process
Figure 5-2 Transmission electron microscope (TEM) analysis of cross-sectional MOIOS structure with double-layer MnSiOx NCs. The diameter and density of the NCs is approximately 6nm.
62
Figure 5-3 Endurance characteristics of (a) double layer and (b) single layer NCs memory structure. Pulses condition of VG−VFB= ± 9 V for 10 ms.
Figure 5-4 Capacitance-voltage (C-V) hysteresis of (a) double layer and (b) single layer NCs memory structure. The memory windows of two samples are nearly equal to 1 under VG-VFB=±5 dash line. Double layer NC shows larger than single layer NC under VG-VFB=±10 V solid line gate voltage operation.
63
Figure 5-5 (a) Memory window characteristics of the multi-layer MnSiOx nanocrystal memory as compared with single-layer MnSiOx nanocrystal memory (b) A simple energy band diagram of small gate voltage (c) high gate voltage operation.
(b)
(a)
(c)
Figure 5-6 (a) Retention characteristics of the multi-layer MnSiOx nanocrystal memory as compared with single-layer MnSiOx nanocrystal memory (b) A simple energy band diagram of single-layer (c) multi-layer NCs.
64
65
Chapter 6 Conclusions
6.1 Conclusions
The nonvolatile memory structure of MnSiOx NCs embedded in the SiOx layer was fabricated by sputtering (Mn0.2Si0.8/Si) in an Ar environment at room temperature.
The MnSiOx NCs can be explained that the MnO react with SiOx during RTO process.
The nanocrystal can be simple and uniform to fabricate in this study. The memory window of MnSiOx NCs enough to define “1” and “0” states is clearly observed for the nonvolatile memory application. The retention and endurance characteristic are enough to be maintained after 10 years and 106 P/E cycles.
XPS were adopted to identify the MnSiOx NCs. The band gap of MnSiOx, VBO and CBO between the MnSiOx films and Si substrates are obtained by XPS measurements, and the values of VBO and CBO to Si are found to be about 2.8 and 1.9 eV, respectively. The analysis of the temperature dependence of the current density in MnSiOx gate stacks is allowed to estimate the energy levels responsible for the leakage current in these layers. The estimation of these energy levels requires the knowledge of the band offsets between the different layers. In this study, the trap level in MnSiOx is about 1.26 eV below the conduction band of MnSiOx. The reliability of electric characteristic are investigated according to above band diagram.
In order to modify over oxidation by conventional RTO process, sputtering in the Ar/ O2 ambiance is adopted. Compare results of memory characteristic for MnSiOx
NC memories by different process. By taking account of the memory window, it indicates no difference for two different processes. A steep (C-V) hysteresis slope and greater endurance characteristic are considered less damage of tunneling oxide during the RTO process. Sputter in O2 ambiance can avoid over oxidation and degradation by
66
conventional RTO process. A superior memory characteristic in term of retention characteristic is found. It’s considered that less oxygen concentration cause deeper trap level and much trap density due to oxygen vacancy.
Multi-layer MnSiOx NCs memory was easily fabricated. It exhibits superior memory characteristics for the application of low-power nanoscaled nonvolatile memory. The nanocrystal can be simple and uniform to fabricate in this study. The memory window of MnSiOx NCs enough to define “1” and “0” states is clearly observed for the nonvolatile memory application. The retention and endurance characteristic are good to be maintained after 10 years and 106 P/E cycles.
67
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Chapter 4
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[4.1] Wei-Ren Chen and Ting-Chang Chang, APPLIED PHYSICS LETTERS 91, 222105 (2007)
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Chapter 5
[5.1] Seong-Wan Ryu, JOURNAL OF APPLIED PHYSICS 101, 026109 (2007)