Cascaded nonlinear stages

where Apm is the available power gain of the m-th stage. This is called the Friis equation.

The Friis equation indicates that the noise contributed by each stage decreases as the gain preceding the stage increases, implying that the first few stages in a cascade are the most critical [2].

2.3 Cascaded Nonlinear Stages

Since in RF systems, signals are processed by cascaded stages, it is important to know how the nonlinearity of each stage is referred to the input of the cascade. Consider two nonlinear stages in cascade. As shown in Fig.2-4. Assuming that the input-output relationship is

y₁(t)=α₁x(t)+α₂x²(t)+α₃x³(t) (14)

y₂(t)=β₁y₁(t)+β₂y₁²(t)+β₃y₁³(t). (15) Substitute (14) into (15) results in the relation

y₂(t)=α₁β₁x(t)+(α₃β₁+2α₁α₂β₂ +α₁³β₃)x³(t) (16) . If we consider only the first- and third-order terms, then

From equation (17) can be simplified if the two sides are inverted and squared:

where A

_IP3,1

and A

_IP3,2

represent the input IP

₃

points of the first and second

stages, respectively. From the above result, we note that as

α₁

increases,

the overall IP

₃

decreases. This is because with higher gain in the first stage,

the second stage senses larger input levels, thereby producing much greater

IM

₃

products [2].

20 log A _out

20 log A _in 1 dB

A

_1-dB

(a)

f

Interferers

Desired Channel

LNA

f

(b)

IIP ₃ OIP ₃

20 log A

20 log(¾α ₃ A ³ ) 20 log(α ₁ A )

(c)

Fig. 2-1 (a) Definition of the 1-dB compression point, (b) Corruption of a signal due to intermodulation, (c) The third-order intercept point

21

In Vn

²₂

Vn , ² out

(a)

Vn , ² out Vn ,

² in

(b)

Fig. 2-2 Determination of input-referred noise voltage.

Noisy network R

_s

(a)

Noiseless network R

_s

2

v

i

2

i

i

(b)

Fig. 2-3 Representation of noise in a two-port network by equivalent input voltage and current sources.

1

IIP

3,

IIP

_3,2

Fig. 2-4 Cascaded nonlinear stages.

Chapter 3

Basic Low-Noise Amplifiers Design 3.1 General consideration in Low-Noise Amplifiers

The stability of an amplifier is a very important consideration in a design and can be determined from the S parameters, the matching networks, and the terminations. A two-port network to be unconditionally stable can be derived from (19) to (22).

Γ_s <1 (19)

The two-port network is shown in Fig. 3-1. For unconditional stability any passive load or source in the network must produce a stable condition. The solution of (19) to (22) gives the required conditions for the two-port network to be unconditionally stable [].

A convenient way of expressing the necessary and sufficient conditions for

unconditional stability is

k >1 (25) Δ <1. (26)

The need for matching networks arises because amplifiers, in order to deliver maximum power to a load or to perform in a certain desired way, must be properly terminated at both the input and the output ports. Figure 3.2 illustrates a typical situation in which a transistor, in order to deliver maximum power to the 50-ohm load, must have the terminations ZS and ZL. The input matching network is designed to transform the generator impedance to the source impedance ZS, and the output matching network transforms the 50-ohm termination to the load impedance ZL. In a resonant circuit, the ratio of its resonant frequency fo to its bandwidth is known as the loaded Q of circuit.

That is,

Q_{L =} BWω^o

(27) The matching networks in Fig. 3-3 are used to provide a match at a certain frequency.

The frequency response of a matching network can be classified as either a two-pole low-pass filter or a high-pass filter. At each node of the matching networks, there is an equivalent series input impedance, denoted by RS+jXS. Hence, a circuit node Q, denoted by Qn, can be defined at each node as

S S

n R

Q = X (28)

If the equivalent parallel input admittance at the node is GP+jBP, the circuit node Q can be expressed in the form

P P

n G

Q = B (29)

In order to obtain a high value of QL, the circuit node Q must be high. Higher values of QL than those obtained with the matching networks in Fig 3-3 can be obtained using matching circuits with three elements. The addition of a third element to a matching networks in Fig 3-3 results in either the lossless Tee network or the lossless Pi network.

The addition of a third element introduces flexibility in the selection of the loaded Q, since the equivalent series impedance at the nodes in the circuit will determine various

values of Qn. Obviously, a high value of Qn in the circuit will result in a high value of QL. However, it is not simple to exactly relate Qn to QL in these circuits. The Q of a Tee or Pi network is normally taken as the highest value of Qn in the circuit. The upper and lower parts of the constant-Q contours can be shown to satisfy a circle equation as follows. Since which can be written as

The plus sign applies when x is positive, and the minus sign when x is negative.

Equation (32) is recognized as the equation of a circle. For x>0, the center in the Г plane is at (0, -1/Qn), and for x<0 at (0, 1/Qn); the radius of the circle is

Q²n

1+ 1 (33)

In a RF amplifier, the input and output matching networks provide the appropriate ac impedances to the transistor. The transistor must also be biased at an appropriate quiescent point. A complete RF amplifier contains both dc bias components and the ac matching network. RFCS, bypass capacitors, and coupling capacitors need to be introduced so the dc bias components do not affect the ac performance of the amplifier.

Illustrate conceptually in Fig. 3-4. [5]

E _S

Z _s ^Γ

^s

^Γ

^IN

Z _IN

Two-port network

Γ

OUT

Γ

L

Z _OUT

Z _L

Fig. 3-1 Stability of two-port networks.

E

Input matching

network

Input matching

network

Z_S

Input matching

network

Z_L Z_S=50Ω

Z_L=50Ω

Fig. 3-2 Block diagram of an amplifier.

Z

_LOAD

L

C

Z

_LOAD

L

C

Z

_LOAD

L

C

Z

_LOAD

C

L

Fig. 3-3 Matching networks.

V_S

R₁ R_C

RFC

RFC

L₁ RFC C₁

C_B R₂ R_E C_E L₂

C_B 50Ω 50Ω

C₂ V_CC

(a)

R

_E

V

_CC

R

_C

R

₁

R

₂

(b)

V_S

L₁ C₁

L₂ 50Ω

50Ω

C₂

(c)

Fig. 3-4 (a) A discrete RF amplifier; (b) the dc model; (c) the ac model.

3.2 Conventional LNA design

3.2.1 Narrow band LNA design

In the design of low noise amplifier, there are many important goals. These include noise figure minimization, providing sufficient gain with good linearity, and the

reasonable power consumption. Fig 3-5 illustrates the input stage of the low noise amplifier with source degeneration. A simple calculation is

_s

If choose appropriate value of inductance and capacitance, then Lg+Ls and Cgs will resonate at certain frequency. By choosing Ls appropriately, the real term can be made equal to 50Ω. The gate inductance Lg is used to set the resonance frequency once Ls is chosen to satisfy the criterion of a 50Ω input impedance. The matching method in noise performance is better than using resistance termination of the input end.

The reverse isolation of low noise amplifier determines the amount of LO signal that leaks from the mixer to the antenna. The leakage arises from capacitive paths, substrate coupling, and bond wire coupling. In heterodyne receivers with a high first IF, the image-reject filter and the front-end duplexer significantly suppress the leakage because the LO frequency falls in their stop-band. In homodyne topology, the leakage is attenuated primarily by the LNA reverse characteristics. Equation (23) suggests that stability improves as S12 decrease, i.e., as the reverse isolation of the circuit increases.

The feedback can be suppressed through the use of a cascade configuration, but at the cost of a somewhat higher noise figure. The common-gate transistor in the Fig 3-5, M1, plays two important roles by increasing the reverse isolation of the LNA: (1) it lowers the LO leakage produced by the following mixer, and (2) it improves the stability of the circuit by minimizing the feedback from the output to the input [6].

L_g

L_s Z_IN

M₁

M₂

Fig. 3-5 Common source stage use inductance degeneration.

E

V_DD V

DD

VG1

VG2

M2

M1

50Ω C₁

C₂

Cf C

3

R_bias R_f L_f

L1 L₂

R_L

Fig. 3-6 Wide-band LNA circuit schematic.

3.2.2 wide-band LNA design

Figure 3-6 is the LNA circuit schematic. We discuss this circuit step by step from the first stage. First, to make1/g_m = 50Ω, the gm value of common gate amplifier is going to be fixed at certain trans-conductance. An additional stage is required to provide sufficient gain over the desired band. A shunt feedback common source amplifier is used in the second stage for this purpose. The first step is the selection of transistor size and bias condition of the M1 to yield ReZ₁₁ =1/g_m =50Ω. This ensures input matching condition for wide-band of frequency. But this condition is violated with optimum noise condition. There is a trade-off between noise and impedance matching in the LNA circuit. One of the major problems in the wide bandwidth amplifier design is the limitation imposed by the gain-bandwidth product of the active device. We know that any active device has a gain roll off at high frequency because of the gate-drain and gate-source capacitance in the transistor. This effect degrades the forward gain as the frequency increases and eventually the transistor stops functioning as an amplifier at the high frequency. Therefore the second design step is the selection of optimal bias point of second stage of LNA so that it operates at its maximum fT. In addition to this S₂₁ degradation with frequency other complications that arises in wide-bandwidth amplifier design includes, increase in reverse gain S₁₂ and noise figure at high frequency.

Negative feedback configuration is used to reduce these effects and increase the bandwidth. An inductor L is connected in series with Rf such that after certain frequency the negative feedback decreases in proportion to the S21 roll-off. This technique improves gain flatness at high frequency. The load inductance of L1 and L2 replace the resistor load which is used conventionally. The magnitude of the inductor’s impedance increases as frequency increases. This increase inductor impedance compensates the active device gain degradation that occurs at high frequency [7].

Another wide-band LNA design schematic is shown in Fig. 3-7. In figure 3-7, the R_f is added as a shunt feedback element to the conventional cascade narrow band LNA and Lload is used as shunt peaking inductor at the output. The capacitor Cf is used for the ac coupling purpose. The source follower, composed of M3 and M4, is added for measurement proposes only, and provides wideband output matching. C1 and C2 are ac coupling capacitor. The small-signal equivalent circuit at he input of the LNA is shown in Fig. 3-8. The resistor R_fM =R_f /(1−A_v) represents the Miller equivalent input resistance of Rf, where Av is the open-loop voltage gain of the LNA. From equivalent circuit, the value of Rf can be much larger than that of the conventional resistance shunt-feedback. In the conventional resistance shunt-feedback, the size of Rf is limited as RfM determines the input impedance. One of the key roles of the feedback resistor Rf

is to reduce the Q-factor of the resonating narrowband LNA input circuit. The Q-factor of the circuit shown in Fig. 3-8 can be approximately given by

From equation (35), and considering the inversely linear relation between the -3dB bandwidth and the Q-factor, the narrowband LNA in Fig. 3-7 can be converted into a wideband amplifier by the proper selection of Rf. To design a wideband amplifier that covers a certain frequency band, the narrowband amplifier will be optimized at the center frequency. The feedback resistor Rf also provides its conventional roles of flattening the gain over a wider bandwidth of frequency with much smaller noise figure degradation [8].

L_g

C1R_bias

V_g1

L_s L_load

R_load

M₁ M₂

M₃ M₄

C₂ R_f

C_f IN

OUT V_DD V_DD

Vg2

Fig. 3-7. Another wide-band LNA schematic.

R

_S

L

_g

R

_fM

C

_gs

s T

L ω

L

_s

Fig. 3-8. Small-signal equivalent circuit at the input.

Another circuit topology for wide-band application is distributed amplifier (DA).

Distributed amplifier was first introduced by [9]. MMIC DA was mainly implemented using GaAs-based or SiGe devices. The distributed amplifier schematic is shown in Fig.

3-9. From the Fig. 3-9, we can observe that the power gain of a cascade pair is considerably higher than that of a common-source single transistor. The input signal propagates down the gate line, with each FET tapping off some of the input power. The amplified output signals from the FETs form a traveling wave on the drain line. The propagation constants and lengths of the gate and drain lines are chosen for constructive phasing of the output signals, and the termination impedanc3es on the lines serve to absorb waves traveling in the reverse directions. According to equivalent circuit of a single unit cell of the gate line and drain line, we can get optimal number of section [10].

A small resistor Rgx is added in the gate of common-gate transistor to improve the entire circuit stability. The input and output impedances of the cascade device are needed. In the DA design, the input and output of the cascade FETs used in the

distributed amplifier were terminated by the gate line characteristic impedance Zog and drain line characteristic impedance Zod, respectively. Higher gain can be obtained by choosing higher characteristic impedance of gate (Zog) and drain lines (Zod) but the cutoff frequency will be lower, which will limit the bandwidth. The m-derived matching section is used in our design to overcome the well-known non-constant image

impedance from the constant-k sections. A de-embedded m-derived πequivalent circuit is shown in Fig. 3-10. Distributed amplifiers are not capable of very high gains or very low noise figure, however, and generally are larger in size than an amplifier having comparable gain over a narrower bandwidth.

V_DD

V_G1 V_G2

Output

Input

M-Derived matching section

R_gx R_gx R_gx

Fig. 3-9. Schematic circuit diagram of the cascade distributed amplifier.

2Z

₂

/m

2 1

2 1 4

m Z m

⎛ − ⎞

⎜ ⎟

⎝ ⎠

mZ

₁

Fig. 3-10. A de-embedded m-derivedπ-equivalent.

Chapter 4

Ultra-Wideband CMOS LNA Design 4.1 Circuit topology and Design flow

4.1.1 Overall circuit introduction

Figure 4-1 shows the proposed ultra-wideband CMOS low noise amplifier topology. From Fig. 4-1, we can observe that it is a two stage low noise amplifier.

Where, the output stage is formed by Darlington pair. Because any MOSFET has a property of gain decreases as frequency increases. The parameter ω_T represents the gain-bandwidth frequency. It is the frequency where the short circuit gain approximates unity. So, it is expected that the parameter ω_T can decide high frequency performance.

Device fT is bounded within any given technology, so it would seem that once biasing conditions that maximize fT have been established. Equation (37) represents the fT.

s gd g

m

T C C

f g

= + π

2 (37) Briefly speaking, fT is the ratio of trans-conductance to input capacitance. If a way could be found to, say, decreasing trans-conductance, fT would increase. The ordinary

differential pair may be considered an fT doubler by this definition, for the device capacitances are in series as far as a differential input is concerned. Hence, the differential input capacitance is one half that of each transistor. The differential

trans-conductance, on the other hand, is unchanged because, although the input voltage divides equally between the two transistors, the differential output current is twice the current in each device. Hence, the overall stage trans-conductance is equal to that of each transistor, and a doubling of fT results [3].

The ultra-wideband is for 3.1 to 10.6 GHZ application. The flat forward gain over the whole bandwidth is essential. A technique that satisfied this requirement of large

bandwidth at low cost is known as shunt peaking. The resistance Rd improves the gain at lower frequency. At high frequency, the Ld can improve the gain.

L-section matching network is used for measurement purposes to drive an external 50Ω load. And C_in and Cout is AC coupling capacitor. Between the first and second stage is Cinter-stage that block the DC bias point and provide an AC path from the first stage to next stage.

The cascode topology improves the reverse isolation (S12) and the frequency response of the amplifier. Because the M2 of the cascode topology has the small input impedance, it can yield the small Miller capacitor. The cascode component is chosen as small as possible to reduce the parasitic capacitors.

4.1.2 Noise analysis

The noise contribution of the input network is due to the finite quality factor Q of the integrated inductors. The MOSFET transistor noise sources are shown in figure 4-2.

In reference [11], the noise generator i²d is As shown in figure 4-2 (b), because the current gain of the source degeneration is

ω

DC RF_in

DC

Output V_DD=1.8 volts V_DD=1.8 volts

V_G1

V_G2 M₁

M₂ M4

M₃

L_g1 C₁

L_g2 L_g3

C₂

L_s1

L_s2 C_s

Cinter-stage

L_d

R_d

L_d

R_d L_O

C_O

R_bias R_G

Fig.4-1. Proposed Low noise amplifier schematic.

i

²d

i²g

M

₁

L

_s1

L

_s2

C

_s

(a)

i²n

M₁

L_s1

L_s2 C_s

v²n

(b)

L_g3

C₁ L_g2

L_g1

C₂ NF=Loss

Y₁

Y₂

Y₃ Z

(c)

Fig. 4-2. (a) M1 noise sources. (b) Input-referred equivalent noise sources. (c) The part of the passive matching network.

0 2 4 6 8 10 12

2 4 6 8

Loss(dB)

Frequency(GHZ)

Square:Ideal component simulated Circle:Equivalent model simulated Triangle:Equation Calculated Star:Noise Figure

Fig.4-3. The power loss of passive network.

where Z is For a lossy passive reciprocal network the noise figure is equal to the loss [10]. The noise contribution of the passive network in the figure 4-2 (c) is

(

21²

)

The transmission matrix parameters [10] A is equal to

1−ω²C₂L_g2, (46)

The loss of the passive network is shown in figure 4-3.

4.1.3 Input matching and output matching

The input impedance of the MOS transistor with the inductive source degeneration is a series RLC circuit. The input impedance Z2 is

( )

_⎟⎟

And the parallel impedance Z1 is

Figure 4-4 shows the two port network for calculating input impedance.

According to transmission matrix theory, we can find the input impedance from ABCD parameters.

The Z2 involves the real part and imaginary part. The real part of the Z2 is dependant of the operation frequency. Because in reference[6], the real part of the input impedance

is _s

gs

m L

C

g . Assume that the inductance of the Ls has fifteen percent error due to the

process variation. The real part of the input impedance would have fifteen percent error.

But in equation (50), the real part of the Z2 would have only six percent error. It proves that the LC parallel network in series at the source would reduce the real part of the input impedance error.

The output impedance Rout of the Darlington pair is

R_out =

[

R_bias+(1+g_m3R_bias)r_o3

]

//r_o4 ≈r_o4. (55) Because the real part of the impedance is ro2 parallel Rd, but the value of ro2 is larger than Rd. So the real part of the output impedance is about Rd. Choosing proper the value

of the Rd, can reach purpose of the output matching. The imaginary part of the output

And the L-section method is used for cancel the imaginary part of the output impedance over the entire operation band.

4.1.4 Darlington pair

The schematic is shown in Fig. 4-9. By proper choosing size of the transistor, the overall trans-conductance is

₄

and the overall parasitic capacitance is

3 4

(

4 4

)

Then, the overall cut-frequency would approximately twice with single transistor at same power consumption level. With fT doubling circuits it is often possible to obtain 80% increase in bandwidth, although the exact improvement depends on numerous and variable factors. The simulation result is shown in figure 4-10. From simulation result we can observe that the fT is similar, but the gain of the Darlington pair in the desired frequency band is higher than single transistor’s gain.

Z

₂

L

_g3

C

_gs1

g

_m1

V

_gs

L

_s1

L

_s2

C

_s

Fig. 4-4. The equivalent circuit of the Z2 input impedance.

Z

₂

Z

_in

Y

₁

=1/Z

₁

C

₂

Y

₃

=1/sL

_g2

Y

₂

=(sC

₂

+1/Z

₂

)

^-1

Fig. 4-5. The equivalent circuit of the Zin input impedance.

0.5j 1.0j 2.0j 5.0j

-0.5j 0.5j

-1.0j 1.0j

-2.0j 2.0j

-5.0j 5.0j

Fig. 4-6. The simulated S11 of the proposed LNA.

4 6 8 10

0.0 0.2 0.4 0.6 0.8 1.0

Q n

Frequency(GHZ)

Fig. 4-7. The Qn of the proposed LNA.

0.5 1.0 2.0 5.0

-0.5j 0.5j

-1.0j 1.0j

-2.0j 2.0j

-5.0j 5.0j

Fig. 4-8. The simulated S22 of the proposed LNA.

M₃

M₄

I_BIAS Drain

Gate

Source

Fig. 4-9. The Darlington pair schematic.

0.1 1 10 100 0

8 16 24 32 40

Gain(dB)

Frequency(GHZ) Square:Darling pair Circle:Single transistor

Fig.4-10. The simulation result of the Darlington pair compared with single transistor.

4.1.5 Shunt peaking

A model of shunt peaking amplifier is shown in Fig. 4-11. The capacitance C may be taken to represent all the loading on the output node, including that of a subsequent stage. The resistance R is the effective load resistance at that node and the inductor provides the bandwidth enhancement. It’s clear from the model that the transfer function

in outi

v is just the impedance of the RLC network, so it should be straightforward to analyze. The addition of an inductance in series with the load resistor provides an impedance component that increases with frequency, which helps offset the decreasing impedance of the capacitance, leaving net impedance that remains roughly constant over a broader frequency range than that of the original RC network. The impedance of the RLC network may be written as

( )

In addition to a zero, there are two poles. We introduce a factor m, defined as the ratio of the RC and L/R time constant:

R L m RC

= / (61) Then, the transfer function becomes

The magnitude of the impedance, normalized to the DC value as a function of frequency, is then

1) ( 2

) 2 1

( ^{2 2 2 2}

1

+ +

− + + + +

−

= m m

m m m

ω

ω , (64)

where ω1 is the uncompensated -3dB frequency. If chosem= 2 ≈1.414, then can extend the bandwidth to a value about 1.85 times as large as the uncompensated bandwidth. However, this choice of m leads to nearly a 20% peak in the frequency response, a value often considered undesirably high. If chosem=1+ 2≈2.414, then can lead to a bandwidth that is about 1.72 times as large as the un-peaked case. Hence,

where ω1 is the uncompensated -3dB frequency. If chosem= 2 ≈1.414, then can extend the bandwidth to a value about 1.85 times as large as the uncompensated bandwidth. However, this choice of m leads to nearly a 20% peak in the frequency response, a value often considered undesirably high. If chosem=1+ 2≈2.414, then can lead to a bandwidth that is about 1.72 times as large as the un-peaked case. Hence,

在文檔中 1.8伏金氧半低雜訊放大器應用於超寬頻3.1-10.6GHZ無線接收端 (頁 15-0)